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增加时序约束注释

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RuigeLee
2026-02-13 17:54:23 +08:00
parent a46c7008b8
commit 44b7aa2a5d
1 changed files with 19 additions and 0 deletions
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19
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -33,7 +33,26 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val isPing_async = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } val isPing_async = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
/* 以SCK : CLOCK = 1 : 2 进行分析
@ SCK 5 posedge isEnR_Async(0) @ SCK 8 negedge exRego
@ SCK 7 posedge isEnR_Async(1) @ SCK 10 negedge exRego
@ SCK 9 posedge isEnR_Async(0) @ SCK 12 negedge exRego
约束 datar_sync(0) -> exRego
约束 datar_sync(1) -> exRego
datar_sync保持时间4*SCK
min 0
max < 2*SCK
*/
/*
约束 addrw_async -> io_addrw
约束 addrr_async -> io_addrr
约束 dataw_async -> io_dataw
两次isEnX间隔 2*SCK 1：2频率 有4*CLOCK 最坏仅需3*clock
dataw_async保持时间4*SCK
min 0
max < 2*clock
*/
val isPong_sync = RegInit(false.B) val isPong_sync = RegInit(false.B)