From 44b7aa2a5d1aef2ea616ec88f7b8ae79d88aaba6 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Fri, 13 Feb 2026 17:54:23 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=97=B6=E5=BA=8F=E7=BA=A6?=
 =?UTF-8?q?=E6=9D=9F=E6=B3=A8=E9=87=8A?=
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---
 .../scala/backBoard/shin/NSpiInterface.scala  | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index eac74bc..173bbf2 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -33,7 +33,26 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
   val isPing_async = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
 
 
+  /*  以SCK : CLOCK = 1 : 2 进行分析
+  @ SCK 5 posedge isEnR_Async(0) @ SCK  8 negedge exRego
+  @ SCK 7 posedge isEnR_Async(1) @ SCK 10 negedge exRego
+  @ SCK 9 posedge isEnR_Async(0) @ SCK 12 negedge exRego
+  约束 datar_sync(0) -> exRego 
+  约束 datar_sync(1) -> exRego 
+  datar_sync保持时间4*SCK
+  min 0
+  max < 2*SCK
+  */
 
+  /*
+  约束 addrw_async -> io_addrw
+  约束 addrr_async -> io_addrr
+  约束 dataw_async -> io_dataw
+  两次isEnX间隔 2*SCK 1：2频率 有4*CLOCK 最坏仅需3*clock
+  dataw_async保持时间4*SCK
+  min 0
+  max < 2*clock
+  */
 
 
   val isPong_sync = RegInit(false.B)