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增加144模式的同步异步qspi

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This commit is contained in:
RuigeLee
2026-02-06 10:39:02 +08:00
parent aa25ae5b6a
commit 41bb316926
4 changed files with 125 additions and 33 deletions
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82
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -29,6 +29,12 @@ class RegAccessInterfaceIO extends Bundle{
}
abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
def SLOW : Boolean
def FAST : Boolean
def OPER444 : Boolean
def OPER114 : Boolean
val io = IO(new RegAccessInterfaceIO)
val sck = Wire(Bool())
@@ -40,6 +46,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
val shiftMOSI = Wire(Bool())
val shiftDat = Wire(UInt(4.W))
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
@@ -91,18 +98,35 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
spiLenTemp := 0.U
spiLen := 2.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 2.U){ //CS为低，且SCK上跳的第0byte
spiLenTemp := Cat( exRegi(2,0), shiftMOSI, 0.U(8.W) )
if( OPER444 ){
spiLenTemp := Cat( shiftDat, 0.U(8.W) )
} else if( OPER114 ){
spiLenTemp := Cat( exRegi(2,0), shiftMOSI, 0.U(8.W) )
}
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 3.U) {//CS为低，且SCK上跳的第0byte
spiLenTemp := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
spiLen := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
if( OPER444 ){
spiLenTemp := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
spiLen := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
} else if( OPER114 ){
spiLenTemp := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
spiLen := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(6,0), shiftMOSI )
if( OPER444 ){
addrr := Cat( exRegi(3,0), shiftDat )
} else if( OPER114 ){
addrr := Cat( exRegi(6,0), shiftMOSI )
}
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
if( OPER444 ){
addrr := Cat(addrr(7,0), exRegi(3,0), shiftDat)
} else if( OPER114 ){
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
}
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){
addrr := addrr + 1.U
@@ -112,9 +136,17 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(6,0), shiftMOSI )
if( OPER444 ){
addrw := Cat( exRegi(3,0), shiftDat )
} else if( OPER114 ){
addrw := Cat( exRegi(6,0), shiftMOSI )
}
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI )
if( OPER444 ){
addrw := Cat(addrw(7,0), exRegi(3,0), shiftDat )
} else if( OPER114 ){
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI )
}
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 4.U & bitSelNext.andR ){
addrw := addrw + 1.U
@@ -129,8 +161,15 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
}
class SSpiInterface extends SpiInterfaceBase{
def SLOW = true
def FAST = false
def OPER444 = false
def OPER114 = true
val spi = IO(new SSPIInterfaceIO)
shiftMOSI := ShiftRegister(spi.mosi, 2, false.B, true.B)
shiftDat := DontCare
sck := spi.sck
csn := spi.csn
@@ -168,10 +207,21 @@ class SSpiInterface extends SpiInterfaceBase{
}
class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
class QSpiInterface(mode: Int) extends SpiInterfaceBase{
def SLOW_444 = 0
def SLOW_114 = 1
def FAST_444 = 2
def FAST_114 = 3
def SLOW = if ( mode == 0 || mode == 1 ) {true} else {false}
def FAST = if ( mode == 2 || mode == 3 ) {true} else {false}
def OPER444 = if ( mode == 0 || mode == 2 ) {true} else {false}
def OPER114 = if ( mode == 1 || mode == 3 ) {true} else {false}
val qspi = IO(new QSPIInterfaceIO)
val shiftDat = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
shiftMOSI := shiftDat(1).extract(0)
shiftDat := ShiftRegister(qspi.mosi, 2, 0.U(4.W), true.B)
shiftMOSI := shiftDat.extract(0)
sck := qspi.sck
csn := qspi.csn
@@ -196,7 +246,7 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( byteSel <= 3.U ){
when( (if( OPER114 ) {byteSel <= 3.U} else {false.B}) ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI )
}.otherwise{
@@ -204,9 +254,9 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
}
} .otherwise{
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftDat(1) )
exRegi := Cat( 0.U, shiftDat )
}.otherwise{
exRegi := Cat( exRegi(3,0), shiftDat(1) )
exRegi := Cat( exRegi(3,0), shiftDat )
}
}
}
@@ -215,11 +265,11 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0
} .elsewhen(
(if( edge ) {isSckPosedge} else {isSckNegedge})
(if( FAST ) {isSckPosedge} else {isSckNegedge})
& ~shiftCSn(1)
){
when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
when( byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || ( if( edge ) { false.B } else { byteSel === 3.U } ) ){
when( (if( FAST ) { bitSel.andR } else { bitSel === 0.U }) ){
when( byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || ( if( FAST ) { false.B } else { byteSel === 3.U } ) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar