diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index d70d55f..7717337 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -40,7 +40,7 @@ class CommonRegisterBundle extends Bundle{
   val hwSerial  = UInt(48.W)
   val busRate   = UInt(8.W)
 
-  val spiSel    = UInt(2.W)
+  val spiSel    = UInt(3.W)
 
   val uniCode = UInt(64.W)
 
@@ -145,7 +145,9 @@ class InterfaceIO extends Bundle{
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
   val iqspi = new QSPIInterfaceIO
+  val vqspi = new QSPIInterfaceIO
   val aqspi = new QSPIInterfaceIO
+  val bqspi = new QSPIInterfaceIO
 
   val lvds  = Flipped(new RegAccessInterfaceIO)
 
@@ -211,15 +213,25 @@ class InterfaceIO extends Bundle{
 abstract class InterfaceBase extends Module with RequireAsyncReset{
   val io: InterfaceIO = IO(new InterfaceIO)
 
+
+  def SLOW_444 = 0
+  def SLOW_114 = 1
+  def FAST_444 = 2
+  def FAST_114 = 3
+
   val oSpi  = Module(new SSpiInterface)
-  val oQSpi = Module(new QSpiInterface(true))
-  val iQSpi = Module(new QSpiInterface(false))
-  val aQSpi = Module(new SyncQSpiInterface)
+  val oQSpi = Module(new QSpiInterface(FAST_114))
+  val iQSpi = Module(new QSpiInterface(SLOW_114))
+  val vQSpi = Module(new QSpiInterface(SLOW_444))
+  val aQSpi = Module(new SyncQSpiInterface(0))
+  val bQSpi = Module(new SyncQSpiInterface(1))
 
   io.ospi <> oSpi.spi
   io.oqspi <> oQSpi.qspi
   io.iqspi <> iQSpi.qspi
+  io.vqspi <> vQSpi.qspi
   io.aqspi <> aQSpi.qspi
+  io.bqspi <> bQSpi.qspi
 
   val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
   val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
@@ -536,6 +548,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnW,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
     ( cReg.spiSel === 3.U ) -> aQSpi.io.isEnW,
+    ( cReg.spiSel === 4.U ) -> vQSpi.io.isEnW,
+    ( cReg.spiSel === 5.U ) -> bQSpi.io.isEnW,
   ))
     
   addrr := Mux1H(Seq(
@@ -543,6 +557,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     ( cReg.spiSel === 1.U ) ->  oSpi.io.addrr,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.addrr,
     ( cReg.spiSel === 3.U ) -> aQSpi.io.addrr,
+    ( cReg.spiSel === 4.U ) -> vQSpi.io.addrr,
+    ( cReg.spiSel === 5.U ) -> bQSpi.io.addrr,
   ))
 
   addrw := Mux1H(Seq(
@@ -550,6 +566,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     ( cReg.spiSel === 1.U ) ->  oSpi.io.addrw,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.addrw,
     ( cReg.spiSel === 3.U ) -> aQSpi.io.addrw,
+    ( cReg.spiSel === 4.U ) -> vQSpi.io.addrw,
+    ( cReg.spiSel === 5.U ) -> bQSpi.io.addrw,
   ))
 
   dataw := Mux1H(Seq(
@@ -557,6 +575,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     ( cReg.spiSel === 1.U ) ->  oSpi.io.dataw,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
     ( cReg.spiSel === 3.U ) -> aQSpi.io.dataw,
+    ( cReg.spiSel === 4.U ) -> vQSpi.io.dataw,
+    ( cReg.spiSel === 5.U ) -> bQSpi.io.dataw,
   ))
 
   isEnR := Mux1H(Seq(
@@ -564,6 +584,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnR,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
     ( cReg.spiSel === 3.U ) -> aQSpi.io.isEnR,
+    ( cReg.spiSel === 4.U ) -> vQSpi.io.isEnR,
+    ( cReg.spiSel === 5.U ) -> bQSpi.io.isEnR,
   ))
 
   datar := MuxCase( 0.U, Array(
@@ -582,6 +604,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
    oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
   oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
   aQSpi.io.datar := Mux(cReg.spiSel === 3.U, datar, 0.U)
+  vQSpi.io.datar := Mux(cReg.spiSel === 4.U, datar, 0.U)
+  bQSpi.io.datar := Mux(cReg.spiSel === 5.U, datar, 0.U)
 
   // when( isEnW ){
   //   printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw)
diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 52ac6c8..0a9d7d8 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -12,7 +12,9 @@ class TopBase_IO_Bundle extends Bundle{
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
+  val vqspi = new QSPIInterfaceIO
   val aqspi = new QSPIInterfaceIO
+  val bqspi = new QSPIInterfaceIO
 
   val iSync = Output(Vec(4, Bool()))
 
@@ -24,7 +26,7 @@ class TopBase_IO_Bundle extends Bundle{
   val hwSerial = Input(UInt(48.W))
   val uniCode = Input(UInt(64.W))
 
-  val spiSel  = Output(UInt(2.W))
+  val spiSel  = Output(UInt(3.W))
 }
 
 
@@ -90,6 +92,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   io.iqspi <> interface.io.iqspi
   io.oqspi <> interface.io.oqspi
   io.aqspi <> interface.io.aqspi
+  io.vqspi <> interface.io.vqspi
+  io.bqspi <> interface.io.bqspi
 
   io.iSync := interface.io.sync
 
diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index bf29881..53c2426 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -6,6 +6,9 @@ import chisel3.util._
 
 
 abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
+  def OPER444: Boolean
+  def OPER114: Boolean
+
   val io = IO(new RegAccessInterfaceIO)
   val qspi = IO(new QSPIInterfaceIO)
 
@@ -48,7 +51,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
   qspi.miso := exRego(7, 4)
   qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
 
-  when( byteSel <= 3.U ){ //单线操作
+  when( (if( OPER114 ) { byteSel <= 3.U } else {false.B}) ){ //单线操作
     bitSel := bitSel + 1.U
   } .otherwise{ //4线操作
     bitSel := ~bitSel
@@ -59,7 +62,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
   }
 
 
-  when( byteSel <= 3.U ){ //单线操作
+  when( (if( OPER114 ) { byteSel <= 3.U } else {false.B}) ){ //单线操作
     when( bitSel === 0.U ){
       exRegi := Cat( 0.U, qspi.mosi.extract(0) )
     }.otherwise{
@@ -98,12 +101,20 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     spiCnt := spiCnt + 1.U
   }
 
-  //单线操作
-  when( (byteSel === 2.U & bitSel >= 4.U) || (byteSel === 3.U) ){
-    spiLenTemp := Cat( spiLenTemp, qspi.mosi.extract(0) )
-  }
-  when( byteSel === 3.U & bitSel.andR ){
-    spiLen := Cat( spiLenTemp, qspi.mosi.extract(0) )
+  if( OPER114 ){//单线操作
+    when( (byteSel === 2.U & bitSel >= 4.U) || (byteSel === 3.U) ){
+      spiLenTemp := Cat( spiLenTemp, qspi.mosi.extract(0) )
+    }
+    when( byteSel === 3.U & bitSel.andR ){
+      spiLen := Cat( spiLenTemp, qspi.mosi.extract(0) )
+    }
+  } else if( OPER444 ){
+    when( (byteSel === 2.U & bitSel.andR) || (byteSel === 3.U) ){
+      spiLenTemp := Cat( spiLenTemp, qspi.mosi )
+    }
+    when( byteSel === 3.U & bitSel.andR ){
+      spiLen := Cat( spiLenTemp, qspi.mosi )
+    }
   }
 
 
@@ -136,9 +147,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     }  
   }
 
-  //单线操作
+  
   when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
-    when( qspi.mosi.extract(0) ){
+    when( (if( OPER114 ){ qspi.mosi.extract(0)} else { qspi.mosi.extract(3)}) ){ //单线操作or4线
       isSpiRead := true.B
     } .otherwise{
       isSpiWrite := true.B
@@ -156,7 +167,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
   }
 
   when( 
-    (byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi.extract(0) ) || //单线操作
+    (byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & (if( OPER114 ){ qspi.mosi.extract(0)} else { qspi.mosi.extract(3)}) ) || //单线操作or4线
     (byteSel > 2.U   & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead)               //混合操作
   ){
     when( ~isPing_async ){
@@ -234,9 +245,12 @@ trait SyncSpiSync{ this: SyncSpiInterfaceBase =>
 
 }
 
-class SyncQSpiInterface extends SyncSpiInterfaceBase
+class SyncQSpiInterface(mode: Int) extends SyncSpiInterfaceBase
 with SyncSpiAsync
 with SyncSpiSync{
+
+  def OPER114 = if ( mode == 0 ) {true} else {false}
+  def OPER444 = if ( mode == 1 ) {true} else {false}
 }
 
 
diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 7c73053..7855c48 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -29,6 +29,12 @@ class RegAccessInterfaceIO extends Bundle{
 }
 
 abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
+  def SLOW    : Boolean
+  def FAST    : Boolean
+  def OPER444 : Boolean
+  def OPER114 : Boolean
+
+
   val io = IO(new RegAccessInterfaceIO)
 
   val sck     = Wire(Bool())
@@ -40,6 +46,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val shiftSCK  = ShiftRegisters(sck, 3, false.B, true.B)
   val shiftCSn  = ShiftRegisters(csn, 3, true.B, true.B)
   val shiftMOSI = Wire(Bool())
+  val shiftDat  = Wire(UInt(4.W))
 
 
   val isSckPosedge     = ~shiftSCK(2) &  shiftSCK(1)
@@ -91,18 +98,35 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
     spiLenTemp := 0.U
     spiLen     := 2.U
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 2.U){ //CS为低，且SCK上跳的第0byte
-    spiLenTemp := Cat( exRegi(2,0), shiftMOSI, 0.U(8.W) )
+    if( OPER444 ){
+      spiLenTemp := Cat(              shiftDat, 0.U(8.W) )
+    } else if( OPER114 ){
+      spiLenTemp := Cat( exRegi(2,0), shiftMOSI, 0.U(8.W) )
+    }
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 3.U) {//CS为低，且SCK上跳的第0byte
-    spiLenTemp := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
-    spiLen     := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
+    if( OPER444 ){
+      spiLenTemp := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
+      spiLen     := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
+    } else if( OPER114 ){
+      spiLenTemp := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
+      spiLen     := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
+    }
   }
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrr := 0.U
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
-    addrr := Cat( exRegi(6,0), shiftMOSI )
+    if( OPER444 ){
+      addrr := Cat( exRegi(3,0), shiftDat )
+    } else if( OPER114 ){
+      addrr := Cat( exRegi(6,0), shiftMOSI )
+    }
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
-    addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
+    if( OPER444 ){
+      addrr := Cat(addrr(7,0), exRegi(3,0), shiftDat)
+    } else if( OPER114 ){
+      addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
+    }
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){
       addrr := addrr + 1.U
@@ -112,9 +136,17 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrw := 0.U
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
-    addrw := Cat( exRegi(6,0), shiftMOSI )
+    if( OPER444 ){
+      addrw := Cat( exRegi(3,0), shiftDat )
+    } else if( OPER114 ){
+      addrw := Cat( exRegi(6,0), shiftMOSI )
+    }
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
-    addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI )
+    if( OPER444 ){
+      addrw := Cat(addrw(7,0), exRegi(3,0), shiftDat )
+    } else if( OPER114 ){
+      addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI )
+    }
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedgeNext(0) & byteSelNext >= 4.U & bitSelNext.andR ){
       addrw := addrw + 1.U
@@ -129,8 +161,15 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
 }
 
 class SSpiInterface extends SpiInterfaceBase{
+  def SLOW = true
+  def FAST = false
+  def OPER444 = false
+  def OPER114 = true
+
+
   val spi = IO(new SSPIInterfaceIO)
   shiftMOSI := ShiftRegister(spi.mosi, 2, false.B, true.B)
+  shiftDat := DontCare
 
   sck     := spi.sck
   csn     := spi.csn
@@ -168,10 +207,21 @@ class SSpiInterface extends SpiInterfaceBase{
 
 }
 
-class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
+class QSpiInterface(mode: Int) extends SpiInterfaceBase{
+
+  def SLOW_444 = 0
+  def SLOW_114 = 1
+  def FAST_444 = 2
+  def FAST_114 = 3
+
+  def SLOW = if ( mode == 0 || mode == 1 ) {true} else {false}
+  def FAST = if ( mode == 2 || mode == 3 ) {true} else {false}
+  def OPER444 = if ( mode == 0 || mode == 2 ) {true} else {false}
+  def OPER114 = if ( mode == 1 || mode == 3 ) {true} else {false}
+
   val qspi = IO(new QSPIInterfaceIO)
-  val shiftDat = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
-  shiftMOSI := shiftDat(1).extract(0)
+  shiftDat := ShiftRegister(qspi.mosi, 2, 0.U(4.W), true.B)
+  shiftMOSI := shiftDat.extract(0)
 
   sck       := qspi.sck
   csn       := qspi.csn
@@ -196,7 +246,7 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
 
   //输入看SCK上升沿
   when( isSckPosedge & ~shiftCSn(1) ){
-    when( byteSel <= 3.U ){
+    when( (if( OPER114 ) {byteSel <= 3.U} else {false.B}) ){
       when( bitSel === 0.U ){
         exRegi := Cat( 0.U, shiftMOSI )
       }.otherwise{
@@ -204,9 +254,9 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
       }
     } .otherwise{
       when( bitSel === 0.U ){
-        exRegi := Cat( 0.U, shiftDat(1) )
+        exRegi := Cat( 0.U, shiftDat )
       }.otherwise{
-        exRegi := Cat( exRegi(3,0), shiftDat(1) )
+        exRegi := Cat( exRegi(3,0), shiftDat )
       }
     }
   }
@@ -215,11 +265,11 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     exRego := 0.U //第一个byte 地址0
   } .elsewhen(
-    (if( edge ) {isSckPosedge} else {isSckNegedge})
+    (if( FAST ) {isSckPosedge} else {isSckNegedge})
     & ~shiftCSn(1)
   ){
-    when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
-      when( byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || ( if( edge ) { false.B } else { byteSel === 3.U } ) ){
+    when( (if( FAST ) { bitSel.andR } else { bitSel === 0.U }) ){
+      when( byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || ( if( FAST ) { false.B } else { byteSel === 3.U } ) ){
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
         exRego := io.datar