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修改索引号机制

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This commit is contained in:
Ruige Lee
2025-05-21 16:50:20 +08:00
parent 72e725a11f
commit 411f340eb0
3 changed files with 23 additions and 57 deletions
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18
src/main/scala/backBoard/shin/Interface.scala
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@@ -97,8 +97,8 @@ class SlaveRegisterBundle extends Bundle{
//链路寄存器组
val isDevOnLeftModify = Bool()
val indexOfLeftDev = UInt(14.W)
// val isDevOnLeftModify = Bool()
// val indexOfLeftDev = UInt(14.W)
val isDevOnRight = UInt(2.W)
val isDevOnRightModify = Bool()
val indexOfRightDev = UInt(14.W)
@@ -154,8 +154,8 @@ class InterfaceIO extends Bundle{
val localDevIndex = Input(UInt(16.W))
// val isDevOnLeft = Input(UInt(2.W))
val isDevOnLeftModify = Input(Bool())
val indexOfLeftDev = Input(UInt(14.W))
// val isDevOnLeftModify = Input(Bool())
// val indexOfLeftDev = Input(UInt(14.W))
val isDevOnRight = Input(UInt(2.W))
val isDevOnRightModify = Input(Bool())
@@ -245,11 +245,11 @@ abstract class InterfaceBase extends Module{
}) ++
Seq(
(addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, sReg.isDevOnLeftModify, 0.U(2.W) ),
(addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
(addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
(addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
(addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
(addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
// (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
// (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
) ++
Seq(
@@ -727,8 +727,8 @@ with InterfaceSystem
sReg.localDevIndex := io.localDevIndex
// sReg.isDevOnLeft := io.isDevOnLeft
sReg.isDevOnLeftModify := io.isDevOnLeftModify
sReg.indexOfLeftDev := io.indexOfLeftDev
// sReg.isDevOnLeftModify := io.isDevOnLeftModify
// sReg.indexOfLeftDev := io.indexOfLeftDev
sReg.isDevOnRight := io.isDevOnRight
sReg.isDevOnRightModify := io.isDevOnRightModify
sReg.indexOfRightDev := io.indexOfRightDev