From 411f340eb030efe5e2d9b7033d7fd74a77d18a90 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 21 May 2025 16:50:20 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E7=B4=A2=E5=BC=95=E5=8F=B7?= =?UTF-8?q?=E6=9C=BA=E5=88=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 18 +++--- src/main/scala/backBoard/shin/ShinTop.scala | 4 +- .../scala/backBoard/shin/SlaveParser.scala | 58 ++++--------------- 3 files changed, 23 insertions(+), 57 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 04b2282..5dd5b64 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -97,8 +97,8 @@ class SlaveRegisterBundle extends Bundle{ //链路寄存器组 - val isDevOnLeftModify = Bool() - val indexOfLeftDev = UInt(14.W) + // val isDevOnLeftModify = Bool() + // val indexOfLeftDev = UInt(14.W) val isDevOnRight = UInt(2.W) val isDevOnRightModify = Bool() val indexOfRightDev = UInt(14.W) @@ -154,8 +154,8 @@ class InterfaceIO extends Bundle{ val localDevIndex = Input(UInt(16.W)) // val isDevOnLeft = Input(UInt(2.W)) - val isDevOnLeftModify = Input(Bool()) - val indexOfLeftDev = Input(UInt(14.W)) + // val isDevOnLeftModify = Input(Bool()) + // val indexOfLeftDev = Input(UInt(14.W)) val isDevOnRight = Input(UInt(2.W)) val isDevOnRightModify = Input(Bool()) @@ -245,11 +245,11 @@ abstract class InterfaceBase extends Module{ }) ++ Seq( - (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, sReg.isDevOnLeftModify, 0.U(2.W) ), + (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ), (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0), (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8), - (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0), - (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8), + // (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0), + // (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8), ) ++ Seq( @@ -727,8 +727,8 @@ with InterfaceSystem sReg.localDevIndex := io.localDevIndex // sReg.isDevOnLeft := io.isDevOnLeft - sReg.isDevOnLeftModify := io.isDevOnLeftModify - sReg.indexOfLeftDev := io.indexOfLeftDev + // sReg.isDevOnLeftModify := io.isDevOnLeftModify + // sReg.indexOfLeftDev := io.indexOfLeftDev sReg.isDevOnRight := io.isDevOnRight sReg.isDevOnRightModify := io.isDevOnRightModify sReg.indexOfRightDev := io.indexOfRightDev diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 72bc295..328c5d8 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -333,8 +333,8 @@ trait ShinTopSlave{ this: ShinTopBase => //从站链路寄存器 // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft - interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify - interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev + // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify + // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev interface.io.isDevOnRight := slaveParser.io.isDevOnRight interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 7b4ce19..d91c29c 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -51,8 +51,8 @@ class SlaveParserIO extends Bundle{ //开放链路寄存器组给interface // val isDevOnLeft = Output(UInt(2.W)) - val isDevOnLeftModify = Output(Bool()) - val indexOfLeftDev = Output(UInt(14.W)) + // val isDevOnLeftModify = Output(Bool()) + // val indexOfLeftDev = Output(UInt(14.W)) val isDevOnRight = Output(UInt(2.W)) val isDevOnRightModify = Output(Bool()) val indexOfRightDev = Output(UInt(14.W)) @@ -98,53 +98,32 @@ abstract class SlaveParserBase extends Module{ val isLastDevice: Bool = RegInit(true.B) // val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft - val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify - val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev + // val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify + // val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U ) val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev - // val isDeviceModified: Bool = RegInit(true.B) - val localDevIndex = RegInit(0.U(14.W)); io.localDevIndex := localDevIndex //当前设备索引 - // dontTouch(localDevIndex) - // 认为只有下行到下行，上行到上行模式，探针是独立发起操作 - // val downSinkSel = Reg(Bool()) - // val upSinkSel = Reg(Bool()) - // val downFrameInfo = Reg(new FrameHeader) //下行大包头 - // val upFrameInfo = Reg(new FrameHeader) //上行大包头 - // val isDownSendBusy = downSendGen.io.frameReq.ready - // val isUpSendBusy = upSendGen.io.frameReq.ready //处理主报文 - // when( downSendGen.io.frameReq.fire ){ - - // } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包 - // downFrameInfo := downRecParser.io.frameReq.bits - // } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){//下行来了一个嗅探包 - // downFrameInfo := downRecParser.io.frameReq.bits - // } - - when( upSendGen.io.frameReq.fire ){ - - } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包 - - // upFrameInfo := upRecParser.io.frameReq.bits - } - downSendGen.io.frameReq.valid := downRecParser.io.frameReq.fire assert( ~(downSendGen.io.frameReq.valid & ~downSendGen.io.frameReq.ready) ) - downSendGen.io.frameReq.bits := downRecParser.io.frameReq.bits + { + downSendGen.io.frameReq.bits := downRecParser.io.frameReq.bits + //voerride + downSendGen.io.frameReq.bits.frameInfo := localDevIndex + } val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader) @@ -366,11 +345,7 @@ trait SlaveParserIndex{ this: SlaveParserBase => downRecParser.io.subMsgReq.bits.style === 0.U & downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址 localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U - isDevOnLeftModify := false.B - indexOfLeftDev := downRecParser.io.subMsgReq.bits.workCnt indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U) - - isDevOnRightModify := false.B when( isDownRecPing ){ downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U } .otherwise{ //pong @@ -712,21 +687,12 @@ trait SlaveParserProbe{ this: SlaveParserBase => } - - - - - when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包 - when( downRecParser.io.frameReq.bits.frameInfo =/= localDevIndex - 1.U ){ //索引不对 - isDevOnLeftModify := true.B - indexOfLeftDev := downRecParser.io.frameReq.bits.frameInfo - } - } - when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包 + indexOfRightDev := upRecParser.io.frameReq.bits.frameInfo when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对 isDevOnRightModify := true.B - indexOfRightDev := upRecParser.io.frameReq.bits.frameInfo + } .otherwise{ + isDevOnRightModify := false.B } }