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RuigeLee
2023-09-15 15:36:44 +08:00
parent b098ca963e
commit 40b558d3a2
1 changed files with 4 additions and 4 deletions
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8
src/main/verilog/backBoardMstTop.v
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@@ -12,9 +12,9 @@ module master_top(
output lvds_down_dout_p, output lvds_down_dout_p,
output lvds_down_dout_n, output lvds_down_dout_n,
input [12:0] io_FSMC_addr, input [9:0] io_FSMC_addr,
input [7:0] io_FSMC_dataIn, input [15:0] io_FSMC_dataIn,
output [7:0] io_FSMC_dataOut, output [15:0] io_FSMC_dataOut,
output io_FSMC_dataOEn, output io_FSMC_dataOEn,
input io_FSMC_cen, input io_FSMC_cen,
input io_FSMC_oen, input io_FSMC_oen,
@@ -41,7 +41,7 @@ wire reset_calib;
wire lock_o; wire lock_o;
wire reset_stop; wire reset_stop;
always@(posedge clk_10m) begin always@(posedge clk_10m_a) begin
rstn_d <= resetn; rstn_d <= resetn;
rst_n <= rstn_d; rst_n <= rstn_d;
end end