From 40b558d3a2830539323fe942711c329b368d71e2 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 15 Sep 2023 15:36:44 +0800 Subject: [PATCH] sync --- src/main/verilog/backBoardMstTop.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v index 50c7f6e..96d7910 100644 --- a/src/main/verilog/backBoardMstTop.v +++ b/src/main/verilog/backBoardMstTop.v @@ -12,9 +12,9 @@ module master_top( output lvds_down_dout_p, output lvds_down_dout_n, - input [12:0] io_FSMC_addr, - input [7:0] io_FSMC_dataIn, - output [7:0] io_FSMC_dataOut, + input [9:0] io_FSMC_addr, + input [15:0] io_FSMC_dataIn, + output [15:0] io_FSMC_dataOut, output io_FSMC_dataOEn, input io_FSMC_cen, input io_FSMC_oen, @@ -41,7 +41,7 @@ wire reset_calib; wire lock_o; wire reset_stop; -always@(posedge clk_10m) begin +always@(posedge clk_10m_a) begin rstn_d <= resetn; rst_n <= rstn_d; end