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准备编译

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This commit is contained in:
Ruige Lee
2025-04-24 16:18:33 +08:00
parent a555302c71
commit 4013e19eda
6 changed files with 258 additions and 156 deletions
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99
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -38,17 +38,13 @@ class SlaveParserIO extends Bundle{
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
// val sram_r = Flipped(new ShareSRAMIO)
// val sram_w = Flipped(new ShareSRAMIO)
val sram_w = Vec( 4, Flipped(new SRAM2kWRIO))
val sram_r = Vec( 4, Flipped(new SRAM2kRDIO))
// val dSMenq = Vec(4, Decoupled(UInt(8.W)))
// val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
val dSMenq = Output( Vec(4, Bool()) )
val uSMdeq = Output( Vec(4, Bool()) )
val sram_w = Vec( 4, Flipped(new SRAM2kWRIO) )
val sram_r = Vec( 4, Flipped(new SRAM2kRDIO) )
val dSMenq = Input( Vec(4, Bool()) )
val uSMdeq = Input( Vec(4, Bool()) )
val trigAddr = Input( Vec(8, UInt(15.W)) )
val timeStamp = Input(UInt(64.W))
}
@@ -407,29 +403,41 @@ trait SlaveParserRW{ this: SlaveParserBase =>
}
}
val isWrite := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
( isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & (downSubMsgInfo(0).devIndex === localDevIndex) & ( (downSubMsgInfo(0).operator === 1.U) | (downSubMsgInfo(0).operator === 3.U) )) |
( isDownRecPing & (downSubMsgInfo(1).devIndex === localDevIndex) & ( (downSubMsgInfo(1).operator === 1.U) | (downSubMsgInfo(1).operator === 3.U) ))
)
val isTermSM = Seq[Bool]
io.sram_w(0).enw := isWrite & isWRSM0
io.sram_w(0).addrw := addrw(10,0)
io.sram_w(0).dataw := downRecParser.io.data.bits
io.sram_w(0).enw := isWrite & isWRSM0
io.sram_w(0).addrw := addrw(10,0)
io.sram_w(0).dataw := downRecParser.io.data.bits
io.sram_w(1).enw := isWrite & isWRSM2
io.sram_w(1).addrw := addrw(10,0)
io.sram_w(1).dataw := downRecParser.io.data.bits
io.sram_w(1).enw := isWrite & isWRSM2
io.sram_w(1).addrw := addrw(10,0)
io.sram_w(1).dataw := downRecParser.io.data.bits
io.sram_w(2).enw := isWrite & isWRSM4
io.sram_w(2).addrw := addrw(10,0)
io.sram_w(2).dataw := downRecParser.io.data.bits
io.sram_w(3).enw := isWrite & isWRSM6
io.sram_w(3).addrw := addrw(10,0)
io.sram_w(3).dataw := downRecParser.io.data.bits
io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
io.uSMdeq(1) := isRead & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
io.dSMenq(2) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
io.uSMdeq(3) := isRead & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
io.dSMenq(4) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
io.uSMdeq(5) := isRead & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
io.dSMenq(6) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
io.uSMdeq(7) := isRead & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
io.sram_w(2).enw := isWrite & isWRSM4
io.sram_w(2).addrw := addrw(10,0)
io.sram_w(2).dataw := downRecParser.io.data.bits
io.sram_w(3).enw := isWrite & isWRSM6
io.sram_w(3).addrw := addrw(10,0)
io.sram_w(3).dataw := downRecParser.io.data.bits
//上行接收
@@ -458,7 +466,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
val addrr = Reg(UInt(15.W))
val readSMAddr := Mux1H(Seq(
val readSMAddr = Mux1H(Seq(
( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr,
))
@@ -474,7 +482,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
}
val upStreamData = Mux1H(Seq(
isRDRegister -> ,
isRDRegister -> 0.U,
isRDSM1 -> io.sram_r(0).datar,
isRDSM3 -> io.sram_r(1).datar,
isRDSM5 -> io.sram_r(2).datar,
@@ -516,7 +524,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
trait SlaveParserSync{ this: SlaveParserBase =>
val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
val upTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
@@ -546,7 +554,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
}
//下行接收
val isSync := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) |
( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U )
)
@@ -675,36 +683,3 @@ with SlaveParserProbe
}
class SlaveParser extends SlaveParserBase{
}