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准备编译

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This commit is contained in:
Ruige Lee
2025-04-24 16:18:33 +08:00
parent a555302c71
commit 4013e19eda
6 changed files with 258 additions and 156 deletions
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128
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -1,54 +1,108 @@
// package BACK
package BACK
// import chisel3._
// import chisel3.util._
import chisel3._
import chisel3.util._
// class ShinTopIO extends Bundle{
// val clk8x = Input(Bool())
// val modeSel = Input(Bool())\
class ShinTopIO extends Bundle{
// val clk8x = Input(Bool())
// val modeSel = Input(Bool())
// val dDatIn = Input(Bool())
// val dDatOut = Output(Bool())
// val uDatIn = Input(Bool())
// val uDatOut = Output(Bool())
// val dDatIn = Input(Bool())
// val dDatOut = Output(Bool())
// val uDatIn = Input(Bool())
// val uDatOut = Output(Bool())
// val qspi =
// val interrupt = Output(Bool())
// val ctrl = Input(UInt(4.W))
// }
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
// val qspi =
// val interrupt = Output(Bool())
// val ctrl = Input(UInt(4.W))
val timeStamp = Input(UInt(64.W))
val sram = MixedVec(
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
)
}
// class ShinTop extends Module{
// val io: ShinTopIO = IO(new ShinTopIO)
class ShinTop extends Module{
val io: ShinTopIO = IO(new ShinTopIO)
// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
// val slaveParser = Module(new SlaveParser )
// val masterParser = Module(new MasterParser)
// val sram = Module(new ShareSRAMDP)
// val interface = Module(new Interface)
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
// sram.io.addrA := Input(UInt(15.W))
// sram.io.datawA := Input( UInt(8.W) )
// sram.io.datarA := Output( UInt(8.W) )
// sram.io.enwA := Input(Bool())
// sram.io.enrA := Input(Bool())
// sram.io.clockA := Input(Bool())
val smUnit = Seq(
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
)
// sram.io.addrB := Input(UInt(15.W))
// sram.io.datawB := Input( UInt(8.W) )
// sram.io.datarB := Output( UInt(8.W) )
// sram.io.enwB := Input(Bool())
// sram.io.enrB := Input(Bool())
// sram.io.clockB := Input(Bool())
smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
smUnit(0).io.enq := slaveParser.io.dSMenq(0)
smUnit(2).io.enq := slaveParser.io.dSMenq(1)
smUnit(4).io.enq := slaveParser.io.dSMenq(2)
smUnit(6).io.enq := slaveParser.io.dSMenq(3)
smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
smUnit(0).io.sram <> io.sram(0)
smUnit(1).io.sram <> io.sram(1)
smUnit(2).io.sram <> io.sram(2)
smUnit(3).io.sram <> io.sram(3)
smUnit(4).io.sram <> io.sram(4)
smUnit(5).io.sram <> io.sram(5)
smUnit(6).io.sram <> io.sram(6)
smUnit(7).io.sram <> io.sram(7)
slaveParser.io.downIn <> io.downIn
slaveParser.io.downOut <> io.downOut
slaveParser.io.upIn <> io.upIn
slaveParser.io.upOut <> io.upOut
slaveParser.io.timeStamp := io.timeStamp
// }
}