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优化时序，提前打拍

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RuigeLee
2024-10-22 17:30:30 +08:00
parent 69dcac95ff
commit 3c965678c8
1 changed files with 4 additions and 5 deletions
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9
src/main/scala/backBoard/shin/ShinSlv.scala
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@@ -83,11 +83,10 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
val downRecvCnt = Reg(UInt(10.W)) val downRecvCnt = Reg(UInt(10.W))
val downLocalDataByte = Mux1H(Seq( val downLocalDataByte = RegEnable(
(downOldHead.operator === 0.U) -> OpInitByte.U, Mux1H(Seq(
(downOldHead.operator === 1.U) -> OpBoardCastByte.U, ( downOldHead.asUInt(3,0) === 0.U) -> OpInitByte.U, ( downOldHead.asUInt(3,0) === 1.U) -> OpBoardCastByte.U, ( downOldHead.asUInt(3,0) === 2.U) -> OpUniCastByte.U,
(downOldHead.operator === 2.U) -> OpUniCastByte.U, )), downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire & downRecvCnt === 3.U) //Timing Opt
))
val isDownStreamError = RegInit( false.B ) val isDownStreamError = RegInit( false.B )