diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala
index 3edecbe..d439ad5 100644
--- a/src/main/scala/backBoard/shin/ShinSlv.scala
+++ b/src/main/scala/backBoard/shin/ShinSlv.scala
@@ -83,11 +83,10 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
   val downRecvCnt = Reg(UInt(10.W))
 
 
-  val downLocalDataByte = Mux1H(Seq(
-    (downOldHead.operator === 0.U) -> OpInitByte.U,
-    (downOldHead.operator === 1.U) -> OpBoardCastByte.U,
-    (downOldHead.operator === 2.U) -> OpUniCastByte.U,
-  ))
+  val downLocalDataByte = RegEnable(
+    Mux1H(Seq(
+      ( downOldHead.asUInt(3,0) === 0.U) -> OpInitByte.U, ( downOldHead.asUInt(3,0) === 1.U) -> OpBoardCastByte.U, ( downOldHead.asUInt(3,0) === 2.U) -> OpUniCastByte.U,
+    )), downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire & downRecvCnt === 3.U) //Timing Opt
 
   val isDownStreamError = RegInit( false.B )