高云FPGA:从站增加0.5s看门狗

This commit is contained in:
Ruige Lee
2025-03-17 17:32:25 +08:00
parent a0799ae62f
commit 3c63a7accc

View File

@@ -28,7 +28,7 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass ) val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass )
val statusP = RegInit(false.B) val statusP = RegInit(false.B)
val statusRF = RegInit(false.B) val statusRF = RegInit(false.B)
val statusPR = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass ) val statusPR = RegInit(0.U(2.W))
val statusER = RegInit(false.B) val statusER = RegInit(false.B)
val statusLE = RegInit(false.B) val statusLE = RegInit(false.B)
val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass ) val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
@@ -111,6 +111,21 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
Mux( statusPR === "b01".U, flash1HZ, Mux( statusPR === "b01".U, flash1HZ,
Mux( statusPR === "b10".U, false.B, true.B Mux( statusPR === "b10".U, false.B, true.B
))) )))
val watchDogTarget = RegInit( 0.U( 19.W ) )
when( isCrcPass ){
watchDogTarget := flashCounter
}
when( isCrcPass ){
statusPR := Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) )
} .elsewhen( ((watchDogTarget === (flashCounter + 1.U)) | (watchDogTarget === 0.U & (flashCounter >= 500000.U))) & usTrigger ){
statusPR := 0.U
}
} }