From 3c63a7accc145e80c1c8a9b3850e3262796b565b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 17 Mar 2025 17:32:25 +0800 Subject: [PATCH] =?UTF-8?q?=E9=AB=98=E4=BA=91FPGA=EF=BC=9A=E4=BB=8E?= =?UTF-8?q?=E7=AB=99=E5=A2=9E=E5=8A=A00.5s=E7=9C=8B=E9=97=A8=E7=8B=97?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/LocalRegisters.scala | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index 3fd19b4..5200c8d 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -28,7 +28,7 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass ) val statusP = RegInit(false.B) val statusRF = RegInit(false.B) - val statusPR = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass ) + val statusPR = RegInit(0.U(2.W)) val statusER = RegInit(false.B) val statusLE = RegInit(false.B) val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass ) @@ -111,6 +111,21 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal => Mux( statusPR === "b01".U, flash1HZ, Mux( statusPR === "b10".U, false.B, true.B ))) + + + val watchDogTarget = RegInit( 0.U( 19.W ) ) + + when( isCrcPass ){ + watchDogTarget := flashCounter + } + + when( isCrcPass ){ + statusPR := Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ) + } .elsewhen( ((watchDogTarget === (flashCounter + 1.U)) | (watchDogTarget === 0.U & (flashCounter >= 500000.U))) & usTrigger ){ + statusPR := 0.U + } + + }