rx数据通道已经拆解
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RuigeLee
@@ -31,12 +31,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val tlSlv = new MacTileLinkSlaveIO
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val tlMst = new MacTileLinkMasterIO
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// Rx Status signals
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val InvalidSymbol = Input(Bool()) // Invalid symbol was received during reception in 100 Mbps mode
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val r_RxFlow = Input(Bool())
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val r_PassAll = Input(Bool())
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val ReceivedPauseFrm = Input(Bool())
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// Tx Status signals
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val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
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val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
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@@ -58,9 +52,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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// Interrupts
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val TxB_IRQ = Output(Bool())
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val TxE_IRQ = Output(Bool())
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val RxB_IRQ = Output(Bool())
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val RxE_IRQ = Output(Bool())
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val Busy_IRQ = Output(Bool())
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// val Busy_IRQ = Output(Bool())
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@@ -85,35 +78,29 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val RxDataLatched2_rxclk = Input(UInt(32.W))
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val WriteRxDataToFifoSync = Input(Bool())
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val RxAbortSync = Input(Bool())
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val LatchedRxLength_rxclk = Input(UInt(16.W))
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val RxStatusInLatched_rxclk = Input(UInt(9.W))
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val ShiftEndedSync = Input(Bool())
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val LatchedRxStartFrmSync = Input(Bool())
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val Busy_IRQ_sync = Input(Bool())
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val RxReady = Output(Bool())
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val RxStatusWriteLatched = Output(Bool()) //only for recording control frame in mac-control
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val RxStatusWriteLatchedSyncb = Input(Bool())
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val rxDeq = new RevBuff_Enq_Bundle
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}
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val io = IO(new MacTileLinkIO)
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val rx_fifo = Module(new MacFifo(dw = 32, dp = 16))
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val RxB_IRQ = RegInit(false.B); io.RxB_IRQ := RxB_IRQ
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val RxE_IRQ = RegInit(false.B); io.RxE_IRQ := RxE_IRQ
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@@ -122,11 +109,74 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B)
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val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
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val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B)
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val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B)
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val LatchedRxStartFrmSyncPluse = io.LatchedRxStartFrmSync & ~RegNext(io.LatchedRxStartFrmSync, false.B)
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val Busy_IRQ_syncPluse = io.Busy_IRQ_sync & ~RegNext(io.Busy_IRQ_sync)
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val RxReady = RegInit(false.B); io.RxReady := RxReady
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val rxDeqCtrlValid = RegInit(false.B)
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io.rxDeq.ctrl.valid := rxDeqCtrlValid
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io.rxDeq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
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io.rxDeq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
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io.rxDeq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse)
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when( io.rxDeq.ctrl.fire ){
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rxDeqCtrlValid := false.B
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} .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){
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rxDeqCtrlValid := true.B
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}
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// RxReady generation
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when(ShiftEndedSyncPluse | RxAbortPluse ){
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RxReady := false.B
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} .elsewhen( io.r_RxEn & (io.rxDeq.data.ready) ){
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RxReady := true.B
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}
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io.rxDeq.data.bits := io.RxDataLatched2_rxclk
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io.rxDeq.data.valid := WriteRxDataToFifoSyncPluse
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assert( (~io.rxDeq.data.valid & ~io.rxDeq.data.ready), "Assert Failed, rx overrun!" )
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val TxRetryPacket = RegInit(false.B)
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val TxRetryPacket_NotCleared = RegInit(false.B)
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@@ -138,136 +188,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val RxReady = RegInit(false.B); io.RxReady := RxReady
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val RxBDHardWire = RegInit(0.U(32.W))
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val isRxPingReady = false.B
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val isRxPongReady = false.B
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val ShiftEnded = RegInit(false.B)
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// RX shift ending signals
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val ShiftEndedSync3 = RegInit(false.B)
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val RxStatusWriteLatched = RegInit(false.B); io.RxStatusWriteLatched := RxStatusWriteLatched
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when(ShiftEnded){
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RxBDHardWire := Cat(io.LatchedRxLength_rxclk, 0.U(1.W), rxBuffDesc.irq, 0.U(1.W), 0.U(4.W), io.RxStatusInLatched_rxclk)
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}
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// RxReady generation
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when(ShiftEnded | RxAbortPluse | ~io.r_RxEn ){
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RxReady := false.B
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} .elsewhen( io.r_RxEn & (isRxPingReady | isRxPongReady) ){
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RxReady := true.B
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}
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rx_fifo.io.data_in := io.RxDataLatched2_rxclk
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rx_fifo.io.write := WriteRxDataToFifoSyncPluse & ~rx_fifo.io.full
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rx_fifo.io.read := io.tlMst.A.fire
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rx_fifo.io.clear := LatchedRxStartFrmSyncPluse
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when( ShiftEndedSyncPluse ){
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ShiftEndedSync3 := true.B
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} .elsewhen(ShiftEnded){
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ShiftEndedSync3 := false.B
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}
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// Generation of the end-of-frame signal
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when(ShiftEndedSync3 & io.tlMst.A.fire & rx_fifo.io.almost_empty & ~ShiftEnded){
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ShiftEnded := true.B
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} .elsewhen(ShiftEnded){
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ShiftEnded := false.B
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}
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assert( ~(rx_fifo.io.full & WriteRxDataToFifoSyncPluse), "Assert Failed, rx overrun!" )
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// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
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when(io.RxStatusWriteLatchedSyncb){
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RxStatusWriteLatched := false.B
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} .elsewhen(ShiftEnded){
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RxStatusWriteLatched := true.B
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}
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val RxIRQEn = RxBDHardWire.extract(14) //[14:13]
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val RxError = (io.RxStatusInLatched_rxclk(6,3).orR) | (io.RxStatusInLatched_rxclk(1,0).orR)
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// Rx Done Interrupt
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when(ShiftEnded & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
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RxB_IRQ := (~RxError)
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} .otherwise{
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RxB_IRQ := false.B
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}
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// Rx Error Interrupt
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when(ShiftEnded & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
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RxE_IRQ := RxError
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} .otherwise{
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RxE_IRQ := false.B
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}
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io.Busy_IRQ := Busy_IRQ_syncPluse
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val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
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val (_, _, isLastD, transDCnt) = edgeOut.count(io.tlMst.D)
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val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
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@@ -303,7 +224,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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def StateIdle = 0.U(3.W)
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def StateWB = 1.U(3.W)
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def StateTX = 2.U(3.W)
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def StateRX = 3.U(3.W)
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val stateNxt = RegInit( StateWB )
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val stateCur = RegNext( stateNxt, StateIdle )
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