From 38550d723b56e840a2e6df41dc3b2d5554f28145 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 12 Oct 2023 15:42:49 +0800 Subject: [PATCH] =?UTF-8?q?rx=E6=95=B0=E6=8D=AE=E9=80=9A=E9=81=93=E5=B7=B2?= =?UTF-8?q?=E7=BB=8F=E6=8B=86=E8=A7=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/RevBuff.scala | 55 ++++++ src/main/scala/mac/MAC.scala | 30 +--- src/main/scala/mac/MacTileLinkRx.scala | 12 -- src/main/scala/mac/MacTilelink.scala | 234 ++++++++----------------- 4 files changed, 141 insertions(+), 190 deletions(-) create mode 100644 src/main/scala/Switch/RevBuff.scala diff --git a/src/main/scala/Switch/RevBuff.scala b/src/main/scala/Switch/RevBuff.scala new file mode 100644 index 0000000..0ea5446 --- /dev/null +++ b/src/main/scala/Switch/RevBuff.scala @@ -0,0 +1,55 @@ +package MAC + +import chisel3._ +import chisel3.util._ + +class RevBuff_Enq_Ctrl_Bundle extends Bundle{ + val LatchedRxLength = UInt(16.W) + val RxStatusInLatched = UInt(9.W) + val isRxAbort = Bool() +} + +class RevBuff_Deq_Ctrl_Bundle extends Bundle{ + +} + +class RevBuff_Enq_Bundle extends Bundle{ + val data = Decoupled(UInt(32.W)) + val ctrl = Decoupled(new RevBuff_Enq_Ctrl_Bundle) +} + + +class RevBuff_Deq_Bundle extends Bundle{ + val data = Decoupled(UInt(32.W)) + val ctrl = Decoupled(new RevBuff_Deq_Ctrl_Bundle) +} + + +class RevBuffIO extends Bundle{ + val enq = Flipped(new RevBuff_Enq_Bundle) + val deq = new RevBuff_Deq_Bundle +} + + + + + +class RevBuff extends Module{ + val io: RevBuffIO = IO(new RevBuffIO) + + val isPing = RegInit(true.B) + val isPong = ~isPing + + val pipoBuff = for( i <- 0 until 2 ) yiled { Module(new Queue( UInt(32.W), 2048/4 )) } + val pipoInfo = for( i <- 0 until 2 ) yiled { Reg(Vec( 18, UInt(8.W))) } + + val recCnt = RegInit(0.U(5.W)) + + + + + + + +} + diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index 2ca2d7c..6c4511e 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -703,13 +703,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul - - wishbone.io.InvalidSymbol := InvalidSymbol - wishbone.io.ReceivedPacketGood := ReceivedPacketGood - wishbone.io.r_RxFlow := r_RxFlow - wishbone.io.r_PassAll := r_PassAll - wishbone.io.ReceivedPauseFrm := ReceivedPauseFrm - wishbone.io.RetryCntLatched := RetryCntLatched wishbone.io.RetryLimit := RetryLimit wishbone.io.LateCollLatched := LateCollLatched @@ -724,9 +717,9 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul wishbone.io.r_TxBDNum := r_TxBDNum TxB_IRQ := wishbone.io.TxB_IRQ TxE_IRQ := wishbone.io.TxE_IRQ - RxB_IRQ := wishbone.io.RxB_IRQ - RxE_IRQ := wishbone.io.RxE_IRQ - Busy_IRQ := wishbone.io.Busy_IRQ + RxB_IRQ := false.B + RxE_IRQ := false.B + @@ -879,12 +872,8 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B ) wishbone.io.ShiftEndedSync := ShiftEndedSync - - val LatchedRxStartFrmSync = ShiftRegister(macTileLinkRx.io.LatchedRxStartFrm, 2, false.B, true.B) - wishbone.io.LatchedRxStartFrmSync := LatchedRxStartFrmSync - - wishbone.io.RxStatusWriteLatchedSyncb := ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B) + @@ -894,18 +883,17 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul // Busy Interrupt - val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2) - wishbone.io.Busy_IRQ_sync := Busy_IRQ_sync - + val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2, false.B, true.B) + Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B) withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) { - RxStatusWriteLatchedSync := ShiftRegister(wishbone.io.RxStatusWriteLatched, 2, false.B, true.B) - macTileLinkRx.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B) + val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 2, false.B, true.B) + RxStatusWriteLatchedSync := ShiftEndedSyncb + macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B ) macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B ) macTileLinkRx.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B ) - macTileLinkRx.io.LatchedRxStartFrmSyncb := ShiftRegister( LatchedRxStartFrmSync, 2, false.B, true.B ) macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B ) } diff --git a/src/main/scala/mac/MacTileLinkRx.scala b/src/main/scala/mac/MacTileLinkRx.scala index 7f78087..52390e9 100644 --- a/src/main/scala/mac/MacTileLinkRx.scala +++ b/src/main/scala/mac/MacTileLinkRx.scala @@ -12,7 +12,6 @@ class MacTileLinkRxIO extends Bundle{ val LatchedRxLength = Output(UInt(16.W)) val RxStatusInLatched = Output( UInt(9.W) ) val ShiftEnded_rck = Output(Bool()) - val LatchedRxStartFrm = Output(Bool()) val RxLength = Input(UInt(16.W)) val LoadRxStatus = Input(Bool()) @@ -20,7 +19,6 @@ class MacTileLinkRxIO extends Bundle{ val ShiftEndedSyncb = Input(Bool()) val RxAbortSyncb = Input(Bool()) val WriteRxDataToFifoSyncb = Input(Bool()) - val LatchedRxStartFrmSyncb = Input(Bool()) val Busy_IRQ_rck = Output(Bool()) val Busy_IRQ_syncb = Input(Bool()) @@ -52,8 +50,6 @@ class MacTileLinkRx extends Module with RequireAsyncReset{ val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck val RxEnableWindow = RegInit(false.B) - val LatchedRxStartFrm = RegInit(false.B); io.LatchedRxStartFrm := LatchedRxStartFrm - val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck @@ -126,14 +122,6 @@ class MacTileLinkRx extends Module with RequireAsyncReset{ WriteRxDataToFifo := false.B } - - when(io.RxStartFrm & ~io.LatchedRxStartFrmSyncb){ - LatchedRxStartFrm := true.B - } .elsewhen(io.LatchedRxStartFrmSyncb){ - LatchedRxStartFrm := false.B - } - - // Generation of the end-of-frame signal when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){ ShiftEnded_rck := true.B diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index a1bcbb9..18cfda9 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -31,12 +31,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val tlSlv = new MacTileLinkSlaveIO val tlMst = new MacTileLinkMasterIO - // Rx Status signals - val InvalidSymbol = Input(Bool()) // Invalid symbol was received during reception in 100 Mbps mode - val r_RxFlow = Input(Bool()) - val r_PassAll = Input(Bool()) - val ReceivedPauseFrm = Input(Bool()) - // Tx Status signals val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made) @@ -58,9 +52,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod // Interrupts val TxB_IRQ = Output(Bool()) val TxE_IRQ = Output(Bool()) - val RxB_IRQ = Output(Bool()) - val RxE_IRQ = Output(Bool()) - val Busy_IRQ = Output(Bool()) + + // val Busy_IRQ = Output(Bool()) @@ -85,35 +78,29 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod + + val RxDataLatched2_rxclk = Input(UInt(32.W)) val WriteRxDataToFifoSync = Input(Bool()) + val RxAbortSync = Input(Bool()) + val LatchedRxLength_rxclk = Input(UInt(16.W)) val RxStatusInLatched_rxclk = Input(UInt(9.W)) + val ShiftEndedSync = Input(Bool()) - val LatchedRxStartFrmSync = Input(Bool()) - val Busy_IRQ_sync = Input(Bool()) val RxReady = Output(Bool()) - val RxStatusWriteLatched = Output(Bool()) //only for recording control frame in mac-control - val RxStatusWriteLatchedSyncb = Input(Bool()) + val rxDeq = new RevBuff_Enq_Bundle + + } val io = IO(new MacTileLinkIO) - val rx_fifo = Module(new MacFifo(dw = 32, dp = 16)) - - - - - val RxB_IRQ = RegInit(false.B); io.RxB_IRQ := RxB_IRQ - val RxE_IRQ = RegInit(false.B); io.RxE_IRQ := RxE_IRQ - - - @@ -122,11 +109,74 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B) - val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B) val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B) val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B) - val LatchedRxStartFrmSyncPluse = io.LatchedRxStartFrmSync & ~RegNext(io.LatchedRxStartFrmSync, false.B) - val Busy_IRQ_syncPluse = io.Busy_IRQ_sync & ~RegNext(io.Busy_IRQ_sync) + + val RxReady = RegInit(false.B); io.RxReady := RxReady + + + val rxDeqCtrlValid = RegInit(false.B) + io.rxDeq.ctrl.valid := rxDeqCtrlValid + io.rxDeq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse) + io.rxDeq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse) + io.rxDeq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse) + + when( io.rxDeq.ctrl.fire ){ + rxDeqCtrlValid := false.B + } .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){ + rxDeqCtrlValid := true.B + } + + + + // RxReady generation + when(ShiftEndedSyncPluse | RxAbortPluse ){ + RxReady := false.B + } .elsewhen( io.r_RxEn & (io.rxDeq.data.ready) ){ + RxReady := true.B + } + + + io.rxDeq.data.bits := io.RxDataLatched2_rxclk + io.rxDeq.data.valid := WriteRxDataToFifoSyncPluse + + assert( (~io.rxDeq.data.valid & ~io.rxDeq.data.ready), "Assert Failed, rx overrun!" ) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + val TxRetryPacket = RegInit(false.B) val TxRetryPacket_NotCleared = RegInit(false.B) @@ -138,136 +188,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val TxBDAddress = RegInit(0.U(7.W)) //[7:1] - val RxReady = RegInit(false.B); io.RxReady := RxReady - - val RxBDHardWire = RegInit(0.U(32.W)) - val isRxPingReady = false.B - val isRxPongReady = false.B - - - val ShiftEnded = RegInit(false.B) - - // RX shift ending signals - val ShiftEndedSync3 = RegInit(false.B) - val RxStatusWriteLatched = RegInit(false.B); io.RxStatusWriteLatched := RxStatusWriteLatched - - - when(ShiftEnded){ - RxBDHardWire := Cat(io.LatchedRxLength_rxclk, 0.U(1.W), rxBuffDesc.irq, 0.U(1.W), 0.U(4.W), io.RxStatusInLatched_rxclk) - } - - // RxReady generation - when(ShiftEnded | RxAbortPluse | ~io.r_RxEn ){ - RxReady := false.B - } .elsewhen( io.r_RxEn & (isRxPingReady | isRxPongReady) ){ - RxReady := true.B - } - - - - - rx_fifo.io.data_in := io.RxDataLatched2_rxclk - rx_fifo.io.write := WriteRxDataToFifoSyncPluse & ~rx_fifo.io.full - rx_fifo.io.read := io.tlMst.A.fire - rx_fifo.io.clear := LatchedRxStartFrmSyncPluse - - - - - - - - - - when( ShiftEndedSyncPluse ){ - ShiftEndedSync3 := true.B - } .elsewhen(ShiftEnded){ - ShiftEndedSync3 := false.B - } - - - // Generation of the end-of-frame signal - when(ShiftEndedSync3 & io.tlMst.A.fire & rx_fifo.io.almost_empty & ~ShiftEnded){ - ShiftEnded := true.B - } .elsewhen(ShiftEnded){ - ShiftEnded := false.B - } - - assert( ~(rx_fifo.io.full & WriteRxDataToFifoSyncPluse), "Assert Failed, rx overrun!" ) - - - - - - - - - - - // Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal - when(io.RxStatusWriteLatchedSyncb){ - RxStatusWriteLatched := false.B - } .elsewhen(ShiftEnded){ - RxStatusWriteLatched := true.B - } - - val RxIRQEn = RxBDHardWire.extract(14) //[14:13] - - - val RxError = (io.RxStatusInLatched_rxclk(6,3).orR) | (io.RxStatusInLatched_rxclk(1,0).orR) - - // Rx Done Interrupt - when(ShiftEnded & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){ - RxB_IRQ := (~RxError) - } .otherwise{ - RxB_IRQ := false.B - } - - // Rx Error Interrupt - when(ShiftEnded & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){ - RxE_IRQ := RxError - } .otherwise{ - RxE_IRQ := false.B - } - - - - io.Busy_IRQ := Busy_IRQ_syncPluse - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B) val (_, _, isLastD, transDCnt) = edgeOut.count(io.tlMst.D) val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) ) @@ -303,7 +224,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod def StateIdle = 0.U(3.W) def StateWB = 1.U(3.W) def StateTX = 2.U(3.W) - def StateRX = 3.U(3.W) val stateNxt = RegInit( StateWB ) val stateCur = RegNext( stateNxt, StateIdle )