latch事件寄存器编译通过

src/main/scala/backBoard/shin/Interface.scala

@@ -33,19 +33,6 @@ class CommonRegisterBundle extends Bundle{
   val intStatus = UInt(32.W)
   val intMode   = UInt(16.W)
 
-
-  // val upRecErrorCnt   = UInt(32.W)
-  // val downRecErrorCnt = UInt(32.W)
-  // val upForwardErrorCnt   = UInt(32.W)
-  // val downForwardErrorCnt = UInt(32.W)
-
-  // val qspiErrorCnt   = UInt(32.W)
-  // val forwardCnt     = UInt(32.W)
-  // val recByteCnt     = UInt(32.W)
-  // val forwardByteCnt = UInt(32.W)
-
-
-
   val wdtStatus = UInt(32.W)
   val wdtEnable = UInt(32.W)
   val wdtTarCnt = Vec( 17, UInt(32.W) )
@@ -61,48 +48,33 @@ class CommonRegisterBundle extends Bundle{
   val smUsedDepth = Vec(8, UInt(8.W))
   val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
-
+  val event = new Bundle{
+    val latchCtl = Vec(2, UInt(4.W))
+    val latchStatus = Vec(2, UInt(4.W))
+    val posedgeTimeStampLatch = Vec(2, UInt(64.W))
+    val negedgeTimeStampLatch = Vec(2, UInt(64.W))
+    val mcuSMTimeStampEnq  = UInt(64.W)
+    val mcuSMTimeStampDeq  = UInt(64.W)
+    val lvdsSMTimeStampEnq = UInt(64.W)
+    val lvdsSMTimeStampDeq = UInt(64.W)
+  }
 }
 
 class MasterRegisterBundle extends Bundle{
-
-
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
 
   val rplTimeStampTx = UInt(16.W)
-
-
 }
 
 
 class SlaveRegisterBundle extends Bundle{
-
-  // val RAMSize   = UInt(8.W)
-  // val MMUNum    = UInt(8.W)
-
-  // val nodeSeqAddr = UInt(16.W)
-  // val nodeSetAddr = UInt(16.W)
-
-
   val ebmmu = Vec(8, new EBMMU_Bundle)
 
-  // val intStatus = UInt(16.W)
-  // val mb = Vec(8, new Bundle{
-  //   val ctrl = UInt(8.W)
-  //   val status = UInt(8.W)
-  // })
-
-
-
-
-
   val localDevIndex = UInt(16.W)
 
   //链路寄存器组
 
-  // val isDevOnLeftModify = Bool()
-  // val indexOfLeftDev = UInt(14.W)
   val isDevOnRight = UInt(2.W)
   val isDevOnRightModify = Bool()
   val indexOfRightDev = UInt(14.W)
@@ -115,14 +87,8 @@ class SlaveRegisterBundle extends Bundle{
   val syncCfg = UInt(8.W)
   val syncWidth = Vec(4, UInt(16.W) )
 
-
-
   val syncOffset = Vec(4, UInt(32.W))
 
-
-
-
-
 }
 
 
@@ -134,10 +100,6 @@ class InterfaceIO extends Bundle{
 
   val lvds  = Flipped(new RegAccessInterfaceIO)
 
-
-
-  // val modeSel = Output(Bool())
-
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
@@ -147,6 +109,9 @@ class InterfaceIO extends Bundle{
   val dSMdeq = Output( Vec(4, Bool()) )
   val uSMenq = Output( Vec(4, Bool()) )
 
+  val lvdsSMEnq = Input(Vec(4, Bool()))
+  val lvdsSMDeq = Input(Vec(4, Bool()))
+
   val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
   val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
 
@@ -156,10 +121,6 @@ class InterfaceIO extends Bundle{
 
   val localDevIndex = Input(UInt(16.W))
 
-  // val isDevOnLeft = Input(UInt(2.W))
-  // val isDevOnLeftModify = Input(Bool())
-  // val indexOfLeftDev = Input(UInt(14.W))
-
   val isDevOnRight = Input(UInt(2.W))
   val isDevOnRightModify = Input(Bool())
   val indexOfRightDev = Input(UInt(14.W))
@@ -186,6 +147,8 @@ class InterfaceIO extends Bundle{
 
   val smUsedDepth = Input( Vec(8, UInt(8.W)) )
   val isSMReset = Output( Vec(8, Bool()) )
+
+  val latchPin = Input(Vec(2, Bool()))
 }
 
 
@@ -408,7 +371,38 @@ abstract class InterfaceBase extends Module{
       (for( i <- 0 until 17; j <- 0 until 4 ) yield {
         ( addr === ("h408".U(16.W) + (4*i+j).U) )  -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
       }) ++
+      Seq(
+        (addr === "h500".U )  -> cReg.event.latchCtl(0),
+        (addr === "h502".U )  -> cReg.event.latchCtl(1),
+        (addr === "h504".U )  -> cReg.event.latchStatus(0),
+        (addr === "h506".U )  -> cReg.event.latchStatus(1),
+      ) ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h508".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h510".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h518".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h520".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h528".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h530".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h538".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h540".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
+      } ++
       Seq()
+
     )
 
 
@@ -968,6 +962,77 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
 }
 
+
+trait InterfaceEvent{ this: InterfaceBase =>
+  val isPosedgeOnce = for( i <- 0 until 2 ) yield  RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
+  val isNegedgeOnce = for( i <- 0 until 2 ) yield  RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
+
+  val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
+  val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
+
+
+  val posedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
+  val negedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
+
+  val mcuSMTimeStampEnq  = RegInit(0.U(64.W))
+  val mcuSMTimeStampDeq  = RegInit(0.U(64.W))
+  val lvdsSMTimeStampEnq = RegInit(0.U(64.W))
+  val lvdsSMTimeStampDeq = RegInit(0.U(64.W))
+
+  for( i <- 0 until 2 ){
+    when( dataw.extract(0) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
+      isPosedgeLatch(i):= false.B
+      posedgeTimeStampLatch(i) := 0.U
+    } .elsewhen( ~RegNext(io.latchPin(i), false.B) & io.latchPin(i) ){
+      when( isPosedgeOnce(i) ){
+        isPosedgeLatch(i) := true.B
+      }
+      when(~isPosedgeLatch(i)){
+        posedgeTimeStampLatch(i) := cReg.timeStamp
+      }
+    }
+
+    when( dataw.extract(1) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
+      isNegedgeLatch(i) := false.B
+      negedgeTimeStampLatch(i) := 0.U
+    } .elsewhen( RegNext(io.latchPin(i), false.B) & ~io.latchPin(i) ){
+      when( isNegedgeOnce(i) ){
+        isNegedgeLatch(i) := true.B
+      }
+      when(~isNegedgeLatch(i)){
+        negedgeTimeStampLatch(i) := cReg.timeStamp
+      }
+    }
+
+    when( io.uSMenq.reduce(_|_) ){
+      mcuSMTimeStampEnq := cReg.timeStamp
+    }
+
+    when( io.dSMdeq.reduce(_|_) ){
+      mcuSMTimeStampDeq := cReg.timeStamp
+    }
+
+    when( io.lvdsSMEnq.reduce(_|_) ){
+      lvdsSMTimeStampEnq := cReg.timeStamp
+    }
+
+    when( io.lvdsSMDeq.reduce(_|_) ){
+      lvdsSMTimeStampDeq := cReg.timeStamp
+    }
+
+    cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)
+
+    cReg.event.latchStatus(i) := Cat( io.latchPin(i), isNegedgeLatch(i), isPosedgeLatch(i) )
+    cReg.event.posedgeTimeStampLatch(i) := posedgeTimeStampLatch(i)
+    cReg.event.negedgeTimeStampLatch(i) := negedgeTimeStampLatch(i)
+  }
+
+  cReg.event.mcuSMTimeStampEnq  := mcuSMTimeStampEnq
+  cReg.event.mcuSMTimeStampDeq  := mcuSMTimeStampDeq
+  cReg.event.lvdsSMTimeStampEnq := lvdsSMTimeStampEnq
+  cReg.event.lvdsSMTimeStampDeq := lvdsSMTimeStampDeq
+}
+
 class Interface extends InterfaceBase
 with InterfaceMCUop
 with InterfaceCheckSM
@@ -975,6 +1040,7 @@ with InterfaceLVDSop
 with InterfaceSync
 // with InterfaceWdt
 with InterfaceSystem
+with InterfaceEvent
 {
 
 

src/main/scala/backBoard/shin/ShinTop.scala

@@ -12,33 +12,12 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  // val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
-  // val downOut = Decoupled(new AXIS_Bundle(8))
-
-  // val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
-  // val upOut = Decoupled(new AXIS_Bundle(8))
-
-	// val qspi = 
-	// val interrupt = Output(Bool())
-	// val ctrl      = Input(UInt(4.W))
-
-
-
-
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
 
-
-  // val req = Flipped(Valid(new Bundle{
-  //   val txAddr    = UInt(15.W)
-  //   val rxAddr    = UInt(15.W)
-  //   val length  = UInt(12.W)
-  // }))
-
   val rsp = Valid(new Bundle{
     val isError = Bool()
-    // val length  = UInt(12.W)
   })
 
   val iSync = Output(Vec(4, Bool()))
@@ -48,6 +27,8 @@ class ShinTopIO extends Bundle{
   val ledTest = Output(UInt(8.W))
 
   val interrupt = Output(Bool())
+
+  val latchPin = Input(Vec(2, Bool()))
 }
 
 
@@ -58,11 +39,6 @@ class ShinTopIO extends Bundle{
 abstract class ShinTopBase extends Module{
   val io: ShinTopIO = IO(new ShinTopIO)
 
-  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
-	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
-
-
-
 	val slaveParser  = Module(new SlaveParser )
 	val masterParser = Module(new MasterParser)
 
@@ -73,6 +49,8 @@ abstract class ShinTopBase extends Module{
 
   val interface = Module(new Interface)
 
+  interface.io.latchPin  := io.latchPin
+
   io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
   
   io.isSoftReset := interface.io.isSoftReset
@@ -128,6 +106,19 @@ abstract class ShinTopBase extends Module{
     Module( new SMUnit(depth = 2) ),
   )
 
+  val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
+  val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
+
+
+  smUnit(0).io.enq := lvdsSMEnq(0)
+  smUnit(2).io.enq := lvdsSMEnq(1)
+  smUnit(4).io.enq := lvdsSMEnq(2)
+  smUnit(6).io.enq := lvdsSMEnq(3)
+
+  smUnit(1).io.deq := lvdsSMDeq(0)
+  smUnit(3).io.deq := lvdsSMDeq(1)
+  smUnit(5).io.deq := lvdsSMDeq(2)
+  smUnit(7).io.deq := lvdsSMDeq(3)
 
   smUnit(0).io.sram_r <> interface.io.sram_r(0)
   smUnit(2).io.sram_r <> interface.io.sram_r(1)
@@ -153,7 +144,6 @@ abstract class ShinTopBase extends Module{
   for( i <- 0 until 8 ){
     interface.io.smUsedDepth(i) := smUnit(i).io.cnt
     smUnit(i).reset := reset.asBool | interface.io.isSMReset(i)
-    
   }
 
 
@@ -210,17 +200,6 @@ abstract class ShinTopBase extends Module{
     slaveParser.io.sram_r(3).datar := 0.U
     masterParser.io.sram_r.datar := 0.U
 
-    smUnit(0).io.enq := false.B
-    smUnit(2).io.enq := false.B
-    smUnit(4).io.enq := false.B
-    smUnit(6).io.enq := false.B
-
-    smUnit(1).io.deq := false.B
-    smUnit(3).io.deq := false.B
-    smUnit(5).io.deq := false.B
-    smUnit(7).io.deq := false.B
-
-
     downCDRIn.io.axis.ready := false.B
     slaveParser.io.downIn.valid := false.B
     slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
@@ -265,7 +244,6 @@ abstract class ShinTopBase extends Module{
 }
 
 
-
 trait ShinTopMaster{ this: ShinTopBase =>
 
   when( interface.io.cReg.modeSel === true.B ){
@@ -277,30 +255,30 @@ trait ShinTopMaster{ this: ShinTopBase =>
 
     when( interface.io.txReq.bits.rxSM === 0.U ){
       smUnit(0).io.sram_w := masterParser.io.sram_w
-      smUnit(0).io.enq    := masterParser.io.rxEnq
+      lvdsSMEnq(0)    := masterParser.io.rxEnq
     } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
       smUnit(2).io.sram_w := masterParser.io.sram_w
-      smUnit(2).io.enq    := masterParser.io.rxEnq
+      lvdsSMEnq(1)    := masterParser.io.rxEnq
     } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
       smUnit(4).io.sram_w := masterParser.io.sram_w
-      smUnit(4).io.enq    := masterParser.io.rxEnq
+      lvdsSMEnq(2)    := masterParser.io.rxEnq
     } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
       smUnit(6).io.sram_w := masterParser.io.sram_w
-      smUnit(6).io.enq    := masterParser.io.rxEnq
+      lvdsSMEnq(3)    := masterParser.io.rxEnq
     }
 
     when( interface.io.txReq.bits.txSM === 0.U ){
       smUnit(1).io.sram_r <> masterParser.io.sram_r
-      smUnit(1).io.deq    := masterParser.io.txDeq
+      lvdsSMDeq(0)    := masterParser.io.txDeq
     } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
       smUnit(3).io.sram_r <> masterParser.io.sram_r
-      smUnit(3).io.deq    := masterParser.io.txDeq
+      lvdsSMDeq(1)    := masterParser.io.txDeq
     } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
       smUnit(5).io.sram_r <> masterParser.io.sram_r
-      smUnit(5).io.deq    := masterParser.io.txDeq
+      lvdsSMDeq(2)    := masterParser.io.txDeq
     } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
       smUnit(7).io.sram_r <> masterParser.io.sram_r
-      smUnit(7).io.deq    := masterParser.io.txDeq
+      lvdsSMDeq(3)    := masterParser.io.txDeq
     }
 
 
@@ -335,7 +313,6 @@ trait ShinTopSlave{ this: ShinTopBase =>
   slaveParser.io.cReg := interface.io.cReg
   slaveParser.io.sReg := interface.io.sReg
 
-
   when( interface.io.cReg.modeSel === false.B ){
     smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
     smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
@@ -347,15 +324,15 @@ trait ShinTopSlave{ this: ShinTopBase =>
     smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
     smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
 
-    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
+    lvdsSMEnq(0) := slaveParser.io.dSMenq(0)
-    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
+    lvdsSMEnq(1) := slaveParser.io.dSMenq(1)
-    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
+    lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
-    smUnit(6).io.enq := slaveParser.io.dSMenq(3)
+    lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
 
-    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
+    lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
-    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
+    lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
-    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
+    lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
-    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
+    lvdsSMDeq(3) := slaveParser.io.uSMdeq(3)
 
     interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
     interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime