1068 lines
36 KiB
Scala
1068 lines
36 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class EBMMU_Bundle extends Bundle{
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val lAddr = UInt(30.W)
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val pAddr = UInt(16.W)
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val length = UInt(16.W)
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val op = UInt(8.W)
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val isEnable = Bool()
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def EBMMU_OP_RD = op === 1.U
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def EBMMU_OP_WR = op === 2.U
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def EBMMU_OP_RW = op === 3.U
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}
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class CommonRegisterBundle extends Bundle{
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val mstOrSlv = UInt(2.W)
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def modeSel:Bool = mstOrSlv === "h1".U
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val hwVersion = UInt(8.W)
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val hwSerial = UInt(48.W)
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val busRate = UInt(8.W)
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val spiSel = UInt(2.W)
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val encryptKey = UInt(128.W)
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val isEncrypt = Bool()
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val intEnable = UInt(32.W)
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val intStatus = UInt(32.W)
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val intMode = UInt(16.W)
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val wdtStatus = UInt(32.W)
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val wdtEnable = UInt(32.W)
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val wdtTarCnt = Vec( 17, UInt(32.W) )
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val timeStamp = UInt(64.W)
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val mstDeltaTime = UInt(32.W)
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val syncPoint = UInt(64.W)
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val syncPeroid = UInt(32.W)
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val custom = Vec( 128, UInt(8.W) )
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val smUsedDepth = Vec(8, UInt(8.W))
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val smTrigLen = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
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val event = new Bundle{
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val latchCtl = Vec(2, UInt(4.W))
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val latchStatus = Vec(2, UInt(4.W))
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val posedgeTimeStampLatch = Vec(2, UInt(64.W))
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val negedgeTimeStampLatch = Vec(2, UInt(64.W))
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val mcuSMTimeStampEnq = UInt(64.W)
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val mcuSMTimeStampDeq = UInt(64.W)
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val lvdsSMTimeStampEnq = UInt(64.W)
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val lvdsSMTimeStampDeq = UInt(64.W)
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}
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}
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class MasterRegisterBundle extends Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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val rplTimeStampTx = UInt(16.W)
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}
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class SlaveRegisterBundle extends Bundle{
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val ebmmu = Vec(8, new EBMMU_Bundle)
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val localDevIndex = UInt(16.W)
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//链路寄存器组
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val isDevOnRight = UInt(2.W)
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val isDevOnRightModify = Bool()
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val indexOfRightDev = UInt(14.W)
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val slvDeltaTime = UInt(32.W) //从站时间戳差值
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val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
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val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
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val syncCfg = UInt(8.W)
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val syncWidth = Vec(4, UInt(16.W) )
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val syncOffset = Vec(4, UInt(32.W))
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}
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class InterfaceIO extends Bundle{
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val ospi = new SSPIInterfaceIO
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val oqspi = new QSPIInterfaceIO
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val iqspi = new QSPIInterfaceIO
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val lvds = Flipped(new RegAccessInterfaceIO)
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val txReq = Valid(new Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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}) //发送请求和SM代号
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val dSMdeq = Output( Vec(4, Bool()) )
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val uSMenq = Output( Vec(4, Bool()) )
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val lvdsSMEnq = Input(Vec(4, Bool()))
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val lvdsSMDeq = Input(Vec(4, Bool()))
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val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
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val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
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val cReg = Output(new CommonRegisterBundle)
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val mReg = Output(new MasterRegisterBundle)
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val sReg = Output(new SlaveRegisterBundle)
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val localDevIndex = Input(UInt(16.W))
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val isDevOnRight = Input(UInt(2.W))
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val isDevOnRightModify = Input(Bool())
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val indexOfRightDev = Input(UInt(14.W))
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val slvDeltaTime = Input(UInt(32.W)) //从站时间戳差值
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val mstDeltaTime = Input(UInt(32.W))
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val deltaFinal = Input(UInt(32.W))
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val sync = Output(Vec(4, Bool()))
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val initEncryptor = Valid(UInt(128.W))
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val isSoftReset = Output(Bool())
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val intMstTrig = Input(Vec(2, Bool()))
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val intHWTrig = Input(Vec(2, Bool()))
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val intHWClr = Output(Vec(2, Bool()))
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val intSlvTrig = Input(Vec(8, Bool()))
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val interrupt = Output(Bool())
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val wdtTrigger = Input(Vec(17, Bool()))
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val smUsedDepth = Input( Vec(8, UInt(8.W)) )
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val isSMReset = Output( Vec(8, Bool()) )
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val latchPin = Input(Vec(2, Bool()))
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}
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abstract class InterfaceBase extends Module{
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val io: InterfaceIO = IO(new InterfaceIO)
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val oSpi = Module(new SSpiInterface)
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val oQSpi = Module(new QSpiInterface)
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val iQSpi = Module(new QSpiInterface)
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io.ospi <> oSpi.spi
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io.oqspi <> oQSpi.qspi
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io.iqspi <> iQSpi.qspi
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val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
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val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
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val sReg = Wire(new SlaveRegisterBundle); io.sReg := sReg
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val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
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val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
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for( i <- 0 until 4 ) {
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sReg.syncWidth(i) := syncWidth(i)
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}
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val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
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val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
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val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
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for( i <- 0 until 4 ) {
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sReg.syncOffset(i) := syncOffset(i)
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}
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val isSysInit = cReg.mstOrSlv =/= 0.U
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val isMstMode = cReg.mstOrSlv === "h1".U
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val isSlvMode = cReg.mstOrSlv === "h2".U
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def AcquireReg(addr: UInt): UInt = {
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Mux1H(
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Seq(
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(addr === "h0".U) -> cReg.mstOrSlv,
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(addr === "h1".U) -> cReg.hwVersion,
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) ++
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((0 until 6).map{ i =>
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(addr === ("h2".U(16.W) + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
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}) ++
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Seq(
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(addr === "h8".U ) -> cReg.busRate( 7,0 ),
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(addr === "h9".U ) -> cReg.spiSel,
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(addr === "ha".U & isSlvMode) -> sReg.localDevIndex(7,0),
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(addr === "hb".U & isSlvMode) -> sReg.localDevIndex(15,8),
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(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
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//(addr === "h21".U & isMstMode) -> mReg.txLength,
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(addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
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(addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
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) ++
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((0 until 16).map{ i =>
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(addr === ("h50".U(16.W) + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
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}) ++
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Seq(
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(addr === "h60".U ) -> cReg.isEncrypt,
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(addr === "h70".U ) -> cReg.intEnable(7,0),
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(addr === "h71".U ) -> cReg.intEnable(15,8),
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(addr === "h72".U ) -> cReg.intEnable(23,16),
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(addr === "h73".U ) -> cReg.intEnable(31,24),
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(addr === "h74".U ) -> cReg.intStatus(7,0),
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(addr === "h75".U ) -> cReg.intStatus(15,8),
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(addr === "h76".U ) -> cReg.intStatus(23,16),
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(addr === "h77".U ) -> cReg.intStatus(31,24),
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(addr === "h7c".U ) -> cReg.intMode(7,0),
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(addr === "h7d".U ) -> cReg.intMode(15,8),
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(addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
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(addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
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(addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
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// (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
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// (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
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) ++
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Seq(
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//本地时钟
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(addr === "h100".U ) -> cReg.timeStamp(7,0),
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(addr === "h101".U ) -> cReg.timeStamp(15,8),
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(addr === "h102".U ) -> cReg.timeStamp(23,16),
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(addr === "h103".U ) -> cReg.timeStamp(31,24),
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(addr === "h104".U ) -> cReg.timeStamp(39,32),
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(addr === "h105".U ) -> cReg.timeStamp(47,40),
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(addr === "h106".U ) -> cReg.timeStamp(55,48),
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(addr === "h107".U ) -> cReg.timeStamp(63,56),
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//参考主站时钟
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(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
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(addr === "h109".U & isSlvMode) -> sReg.deltaFinal(15,8),
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(addr === "h10a".U & isSlvMode) -> sReg.deltaFinal(23,16),
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(addr === "h10b".U & isSlvMode) -> sReg.deltaFinal(31,24),
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// (addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32),
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// (addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40),
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// (addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48),
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// (addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56),
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//主站发送接收时间差
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(addr === "h110".U ) -> cReg.mstDeltaTime(7,0),
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(addr === "h111".U ) -> cReg.mstDeltaTime(15,8),
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(addr === "h112".U ) -> cReg.mstDeltaTime(23,16),
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(addr === "h113".U ) -> cReg.mstDeltaTime(31,24),
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//从站发送接收时间差
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(addr === "h114".U & isSlvMode) -> sReg.slvDeltaTime(7,0),
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(addr === "h115".U & isSlvMode) -> sReg.slvDeltaTime(15,8),
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(addr === "h116".U & isSlvMode) -> sReg.slvDeltaTime(23,16),
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(addr === "h117".U & isSlvMode) -> sReg.slvDeltaTime(31,24),
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//校准后的时钟
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(addr === "h118".U & isSlvMode) -> sReg.recoTimeStamp(7,0),
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(addr === "h119".U & isSlvMode) -> sReg.recoTimeStamp(15,8),
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(addr === "h11a".U & isSlvMode) -> sReg.recoTimeStamp(23,16),
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(addr === "h11b".U & isSlvMode) -> sReg.recoTimeStamp(31,24),
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(addr === "h11c".U & isSlvMode) -> sReg.recoTimeStamp(39,32),
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(addr === "h11d".U & isSlvMode) -> sReg.recoTimeStamp(47,40),
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(addr === "h11e".U & isSlvMode) -> sReg.recoTimeStamp(55,48),
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(addr === "h11f".U & isSlvMode) -> sReg.recoTimeStamp(63,56),
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(addr === "h120".U & isSlvMode) -> sReg.syncCfg,
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(addr === "h122".U & isSlvMode) -> sReg.syncWidth(0)(7,0),
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(addr === "h123".U & isSlvMode) -> sReg.syncWidth(0)(15,8),
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(addr === "h124".U & isSlvMode) -> sReg.syncWidth(1)(7,0),
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(addr === "h125".U & isSlvMode) -> sReg.syncWidth(1)(15,8),
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(addr === "h126".U & isSlvMode) -> sReg.syncWidth(2)(7,0),
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(addr === "h127".U & isSlvMode) -> sReg.syncWidth(2)(15,8),
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(addr === "h128".U & isSlvMode) -> sReg.syncWidth(3)(7,0),
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(addr === "h129".U & isSlvMode) -> sReg.syncWidth(3)(15,8),
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(addr === "h130".U ) -> cReg.syncPoint(7,0),
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(addr === "h131".U ) -> cReg.syncPoint(15,8),
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(addr === "h132".U ) -> cReg.syncPoint(23,16),
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(addr === "h133".U ) -> cReg.syncPoint(31,24),
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(addr === "h134".U ) -> cReg.syncPoint(39,32),
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(addr === "h135".U ) -> cReg.syncPoint(47,40),
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(addr === "h136".U ) -> cReg.syncPoint(55,48),
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(addr === "h137".U ) -> cReg.syncPoint(63,56),
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(addr === "h138".U ) -> cReg.syncPeroid(7,0),
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(addr === "h139".U ) -> cReg.syncPeroid(15,8),
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(addr === "h13a".U ) -> cReg.syncPeroid(23,16),
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(addr === "h13b".U ) -> cReg.syncPeroid(31,24),
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(addr === "h13c".U & isSlvMode) -> sReg.syncOffset(1)(7,0),
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(addr === "h13d".U & isSlvMode) -> sReg.syncOffset(1)(15,8),
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(addr === "h13e".U & isSlvMode) -> sReg.syncOffset(1)(23,16),
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(addr === "h13f".U & isSlvMode) -> sReg.syncOffset(1)(31,24),
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(addr === "h140".U & isSlvMode) -> sReg.syncOffset(2)(7,0),
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(addr === "h141".U & isSlvMode) -> sReg.syncOffset(2)(15,8),
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(addr === "h142".U & isSlvMode) -> sReg.syncOffset(2)(23,16),
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(addr === "h143".U & isSlvMode) -> sReg.syncOffset(2)(31,24),
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(addr === "h144".U & isSlvMode) -> sReg.syncOffset(3)(7,0),
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(addr === "h145".U & isSlvMode) -> sReg.syncOffset(3)(15,8),
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(addr === "h146".U & isSlvMode) -> sReg.syncOffset(3)(23,16),
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(addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24),
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) ++
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( 0 until 128 ).map{ i =>
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( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i)
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} ++
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( 0 until 8 ).map{ i => Seq(
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( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
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( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
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( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
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( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24),
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( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0),
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( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8),
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( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0),
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( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8),
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( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
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( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
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)}.reduce(_++_) ++
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( 0 until 8 ).map{ i =>
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( addr === ("h301".U(16.W) + (i*4).U) ) -> cReg.smUsedDepth(i)
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h303".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
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} ++
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( 0 until 4 ).map{ i =>
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( addr === ("h400".U(16.W) + i.U) ) -> cReg.wdtStatus( 8*i+7, 8*i+0 )
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} ++
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( 0 until 4 ).map{ i =>
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( addr === ("h404".U(16.W) + i.U) ) -> cReg.wdtEnable( 8*i+7, 8*i+0 )
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} ++
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(for( i <- 0 until 17; j <- 0 until 4 ) yield {
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( addr === ("h408".U(16.W) + (4*i+j).U) ) -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
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}) ++
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Seq(
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(addr === "h500".U ) -> cReg.event.latchCtl(0),
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(addr === "h502".U ) -> cReg.event.latchCtl(1),
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(addr === "h504".U ) -> cReg.event.latchStatus(0),
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(addr === "h506".U ) -> cReg.event.latchStatus(1),
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) ++
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( 0 until 8 ).map{ i =>
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( addr === ("h508".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h510".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h518".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h520".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
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} ++
|
||
( 0 until 8 ).map{ i =>
|
||
( addr === ("h528".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
|
||
} ++
|
||
( 0 until 8 ).map{ i =>
|
||
( addr === ("h530".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
|
||
} ++
|
||
( 0 until 8 ).map{ i =>
|
||
( addr === ("h538".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
|
||
} ++
|
||
( 0 until 8 ).map{ i =>
|
||
( addr === ("h540".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
|
||
} ++
|
||
Seq()
|
||
|
||
)
|
||
|
||
|
||
}
|
||
|
||
|
||
|
||
//spi信号
|
||
val addrr = Wire(UInt(16.W))
|
||
val addrw = Wire(UInt(16.W))
|
||
val dataw = Wire( UInt(8.W) )
|
||
val datar = Wire( UInt(8.W) )
|
||
val isEnW = Wire(Bool())
|
||
val isEnR = Wire(Bool())
|
||
|
||
|
||
}
|
||
|
||
trait InterfaceMCUop{ this: InterfaceBase =>
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
isEnW := Mux1H(Seq(
|
||
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
|
||
( cReg.spiSel === 1.U ) -> oSpi.io.isEnW,
|
||
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
|
||
))
|
||
|
||
addrr := Mux1H(Seq(
|
||
( cReg.spiSel === 0.U ) -> iQSpi.io.addrr,
|
||
( cReg.spiSel === 1.U ) -> oSpi.io.addrr,
|
||
( cReg.spiSel === 2.U ) -> oQSpi.io.addrr,
|
||
))
|
||
|
||
addrw := Mux1H(Seq(
|
||
( cReg.spiSel === 0.U ) -> iQSpi.io.addrw,
|
||
( cReg.spiSel === 1.U ) -> oSpi.io.addrw,
|
||
( cReg.spiSel === 2.U ) -> oQSpi.io.addrw,
|
||
))
|
||
|
||
dataw := Mux1H(Seq(
|
||
( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
|
||
( cReg.spiSel === 1.U ) -> oSpi.io.dataw,
|
||
( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
|
||
))
|
||
|
||
isEnR := Mux1H(Seq(
|
||
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
|
||
( cReg.spiSel === 1.U ) -> oSpi.io.isEnR,
|
||
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
|
||
))
|
||
|
||
datar := MuxCase( 0.U, Array(
|
||
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
|
||
((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
|
||
((addrr & "hF800".U) === "h1000".U) -> 0.U,
|
||
((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
|
||
((addrr & "hF800".U) === "h2000".U) -> 0.U,
|
||
((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar,
|
||
((addrr & "hF800".U) === "h3000".U) -> 0.U,
|
||
((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar,
|
||
((addrr & "hF800".U) === "h4000".U) -> 0.U,
|
||
))
|
||
|
||
iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
|
||
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
|
||
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
|
||
|
||
// when( isEnW ){
|
||
// printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw)
|
||
// }
|
||
// when( isEnR ){
|
||
// printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrr)
|
||
// }
|
||
|
||
|
||
|
||
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
|
||
cReg.hwVersion := RegEnable( dataw , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
|
||
|
||
cReg.hwSerial :=
|
||
Cat(
|
||
(0 until 6).map{ i =>
|
||
RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
|
||
}.reverse
|
||
)
|
||
|
||
cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
|
||
cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
|
||
|
||
cReg.encryptKey :=
|
||
Cat(
|
||
(0 until 16).map{ i =>
|
||
RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
|
||
}.reverse
|
||
)
|
||
|
||
cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )
|
||
|
||
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
|
||
mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
|
||
// mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
|
||
|
||
( 0 until 128 ).map{ i =>
|
||
cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
|
||
}
|
||
|
||
val rplTimeStampTx = RegInit(0.U(16.W))
|
||
|
||
mReg.rplTimeStampTx := rplTimeStampTx
|
||
|
||
when( io.intMstTrig(0) ){
|
||
rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W)
|
||
} .elsewhen( isEnW & addrw === "h25".U ){
|
||
rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) )
|
||
} .elsewhen( isEnW & addrw === "h24".U ){
|
||
rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
|
||
}
|
||
|
||
|
||
when( isEnW & isSlvMode ){
|
||
when( addrw === "h120".U ){
|
||
syncCfg := dataw
|
||
}
|
||
|
||
for( i <- 0 until 4 ){
|
||
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
|
||
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
|
||
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
|
||
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
|
||
}
|
||
}
|
||
|
||
when( addrw === "h130".U ){
|
||
syncPoint := Cat( syncPoint(63,8), dataw )
|
||
} .elsewhen( addrw === "h131".U ){
|
||
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
|
||
} .elsewhen( addrw === "h132".U ){
|
||
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
|
||
} .elsewhen( addrw === "h133".U ){
|
||
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
|
||
} .elsewhen( addrw === "h134".U ){
|
||
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
|
||
} .elsewhen( addrw === "h135".U ){
|
||
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
|
||
} .elsewhen( addrw === "h136".U ){
|
||
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
|
||
} .elsewhen( addrw === "h137".U ){
|
||
syncPoint := Cat( dataw, syncPoint(55,0) )
|
||
}
|
||
|
||
.elsewhen( addrw === "h138".U ){
|
||
syncPeroid := Cat( syncPeroid(31,8), dataw )
|
||
} .elsewhen( addrw === "h139".U ){
|
||
syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) )
|
||
} .elsewhen( addrw === "h13a".U ){
|
||
syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) )
|
||
} .elsewhen( addrw === "h13b".U ){
|
||
syncPeroid := Cat( dataw, syncPeroid(23,0) )
|
||
}
|
||
|
||
for( i <- 1 until 4 ){
|
||
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
|
||
} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
|
||
} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
|
||
} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
val wdtStatus = for( i <- 0 until 17 ) yield { RegInit(false.B) }
|
||
cReg.wdtStatus := Cat( wdtStatus.reverse )
|
||
|
||
for( i <- 0 until 8 ){
|
||
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
|
||
wdtStatus(i) := false.B
|
||
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
|
||
wdtStatus(i) := true.B
|
||
}
|
||
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
|
||
wdtStatus(8+i) := false.B
|
||
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
|
||
wdtStatus(8+i) := true.B
|
||
}
|
||
}
|
||
for( i <- 0 until 1 ){
|
||
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
|
||
wdtStatus(16+i) := false.B
|
||
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
|
||
wdtStatus(16+i) := true.B
|
||
}
|
||
}
|
||
|
||
cReg.wdtEnable :=
|
||
Cat(
|
||
RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h406".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
|
||
)
|
||
|
||
for( i <- 0 until 17 ){
|
||
cReg.wdtTarCnt(i) :=
|
||
Cat(
|
||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
|
||
)
|
||
}
|
||
|
||
}
|
||
|
||
trait InterfaceCheckSM{ this: InterfaceBase =>
|
||
val isEnW: Bool
|
||
val addrw: UInt
|
||
val dataw: UInt
|
||
val isEnR: Bool
|
||
|
||
|
||
val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
|
||
val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
|
||
|
||
|
||
for( i <- 0 until 8 ){
|
||
|
||
io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))
|
||
|
||
cReg.smUsedDepth(i) := io.smUsedDepth(i)
|
||
cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
|
||
|
||
when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
|
||
smTrigLen_H(i) := dataw
|
||
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
|
||
smTrigLen_H(i) := io.lvds.dataw
|
||
}
|
||
|
||
when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
|
||
smTrigLen_L(i) := dataw
|
||
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
|
||
smTrigLen_L(i) := io.lvds.dataw
|
||
}
|
||
|
||
}
|
||
|
||
|
||
io.sram_r(0).addrr := addrr
|
||
io.sram_r(1).addrr := addrr
|
||
io.sram_r(2).addrr := addrr
|
||
io.sram_r(3).addrr := addrr
|
||
|
||
io.sram_r(0).enr := isEnR & (( addrr & "hF800".U ) === "h0800".U)
|
||
io.sram_r(1).enr := isEnR & (( addrr & "hF800".U ) === "h1800".U)
|
||
io.sram_r(2).enr := isEnR & (( addrr & "hF800".U ) === "h2800".U)
|
||
io.sram_r(3).enr := isEnR & (( addrr & "hF800".U ) === "h3800".U)
|
||
|
||
io.sram_w(0).addrw := addrw
|
||
io.sram_w(1).addrw := addrw
|
||
io.sram_w(2).addrw := addrw
|
||
io.sram_w(3).addrw := addrw
|
||
|
||
io.sram_w(0).dataw := dataw
|
||
io.sram_w(1).dataw := dataw
|
||
io.sram_w(2).dataw := dataw
|
||
io.sram_w(3).dataw := dataw
|
||
|
||
io.sram_w(0).enw := isEnW & (( addrw & "hF800".U ) === "h1000".U)
|
||
io.sram_w(1).enw := isEnW & (( addrw & "hF800".U ) === "h2000".U)
|
||
io.sram_w(2).enw := isEnW & (( addrw & "hF800".U ) === "h3000".U)
|
||
io.sram_w(3).enw := isEnW & (( addrw & "hF800".U ) === "h4000".U)
|
||
|
||
io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U + 1.U)
|
||
io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h1800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U + 1.U)
|
||
io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h2800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U + 1.U)
|
||
io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h3800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U + 1.U)
|
||
|
||
io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U)
|
||
io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U)
|
||
io.uSMenq(2) := isEnW & (( addrw & "hF800".U ) === "h3000".U) & (addrw(10,0) === cReg.smTrigLen(5) - 1.U)
|
||
io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U)
|
||
}
|
||
|
||
trait InterfaceLVDSop{ this: InterfaceBase =>
|
||
|
||
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
|
||
|
||
when( io.lvds.isEnW & isSlvMode ){
|
||
|
||
when( io.lvds.addrw === "h120".U ){
|
||
syncCfg := io.lvds.dataw
|
||
}
|
||
|
||
for( i <- 0 until 4 ){
|
||
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
|
||
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
|
||
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
|
||
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
|
||
}
|
||
}
|
||
|
||
.elsewhen( io.lvds.addrw === "h130".U ){
|
||
syncPoint := Cat( syncPoint(63,8), io.lvds.dataw )
|
||
} .elsewhen( io.lvds.addrw === "h131".U ){
|
||
syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) )
|
||
} .elsewhen( io.lvds.addrw === "h132".U ){
|
||
syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) )
|
||
} .elsewhen( io.lvds.addrw === "h133".U ){
|
||
syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) )
|
||
} .elsewhen( io.lvds.addrw === "h134".U ){
|
||
syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) )
|
||
} .elsewhen( io.lvds.addrw === "h135".U ){
|
||
syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) )
|
||
} .elsewhen( io.lvds.addrw === "h136".U ){
|
||
syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) )
|
||
} .elsewhen( io.lvds.addrw === "h137".U ){
|
||
syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) )
|
||
}
|
||
|
||
.elsewhen( io.lvds.addrw === "h138".U ){
|
||
syncPeroid := Cat( syncPeroid(31,8), io.lvds.dataw )
|
||
} .elsewhen( io.lvds.addrw === "h139".U ){
|
||
syncPeroid := Cat( syncPeroid(31,16), io.lvds.dataw, syncPeroid(7,0) )
|
||
} .elsewhen( io.lvds.addrw === "h13a".U ){
|
||
syncPeroid := Cat( syncPeroid(31,24), io.lvds.dataw, syncPeroid(15,0) )
|
||
} .elsewhen( io.lvds.addrw === "h13b".U ){
|
||
syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) )
|
||
}
|
||
|
||
for( i <- 1 until 4 ){
|
||
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
|
||
} .elsewhen( io.lvds.addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) )
|
||
} .elsewhen( io.lvds.addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) )
|
||
} .elsewhen( io.lvds.addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
|
||
syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) )
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
( 0 until 8 ).map{ i =>
|
||
sReg.ebmmu(i).lAddr := Cat(
|
||
RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
|
||
)
|
||
|
||
sReg.ebmmu(i).pAddr := Cat(
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
|
||
)
|
||
|
||
sReg.ebmmu(i).length := Cat(
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
|
||
)
|
||
|
||
sReg.ebmmu(i).op :=
|
||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
|
||
|
||
sReg.ebmmu(i).isEnable :=
|
||
RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
|
||
}
|
||
|
||
}
|
||
|
||
trait InterfaceSync{ this: InterfaceBase =>
|
||
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
|
||
|
||
cReg.mstDeltaTime := io.mstDeltaTime
|
||
|
||
|
||
// sReg.mstTimeStamp := io.mstTimeStamp
|
||
sReg.deltaFinal := io.deltaFinal
|
||
sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
|
||
sReg.slvDeltaTime := io.slvDeltaTime
|
||
|
||
val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
|
||
val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
|
||
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
|
||
|
||
|
||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||
syncSign(0) := true.B
|
||
syncPoint := syncPoint + cReg.syncPeroid
|
||
} .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
|
||
syncSign(0) := false.B
|
||
} .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||
syncSign(0) := false.B
|
||
}
|
||
|
||
for( i <- 1 until 4 ) {
|
||
|
||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||
syncOffsetCnt(i) := 0.U
|
||
} .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
|
||
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
|
||
} .elsewhen( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||
syncOffsetCnt(i) := "hFFFFFFFF".U(32.W)
|
||
}
|
||
|
||
when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||
syncSign(i) := true.B
|
||
} .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
|
||
syncSign(i) := false.B
|
||
} .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
|
||
syncSign(i) := false.B
|
||
}
|
||
|
||
}
|
||
|
||
for( i <- 0 until 4 ){
|
||
when( ~sReg.syncCfg(4+i) ){
|
||
when( syncSign(i) ){
|
||
syncResetCnt(i) := syncResetCnt(i) + 1.U
|
||
} .otherwise{
|
||
syncResetCnt(i) := 0.U
|
||
}
|
||
}
|
||
|
||
}
|
||
|
||
|
||
|
||
|
||
io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
|
||
io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
|
||
io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
|
||
io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode
|
||
|
||
}
|
||
|
||
// trait InterfaceWdt{ this: InterfaceBase =>
|
||
|
||
// }
|
||
|
||
trait InterfaceSystem{ this: InterfaceBase =>
|
||
io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
|
||
|
||
cReg.intEnable :=
|
||
Cat(
|
||
1.U(1.W), //复位中断，时钟为1
|
||
RegEnable( dataw(6,0), 0.U, isEnW & addrw === "h73".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),
|
||
)
|
||
|
||
val intStatus = for( i <- 0 until 32 ) yield {
|
||
if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
|
||
}
|
||
cReg.intStatus := Cat( intStatus.reverse )
|
||
|
||
cReg.intMode :=
|
||
Cat(
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h7d".U ),
|
||
RegEnable( dataw, 0.U, isEnW & addrw === "h7c".U ),
|
||
)
|
||
|
||
val isLevelInt = cReg.intMode.extract(15) === false.B
|
||
val isPulseInt = cReg.intMode.extract(15) === true.B
|
||
val intPulseWidth = cReg.intMode(14,0)
|
||
|
||
//主站发送完成
|
||
when( io.intMstTrig(0) ){
|
||
intStatus(0) := true.B
|
||
}
|
||
|
||
//主站接收完成
|
||
when( io.intMstTrig(1) ){
|
||
intStatus(1) := true.B
|
||
}
|
||
|
||
//主站发送周期到了
|
||
|
||
|
||
//看门狗溢出
|
||
when( io.wdtTrigger.reduce(_|_) ){
|
||
intStatus(4) := true.B
|
||
}
|
||
|
||
|
||
|
||
|
||
//从站SM请求
|
||
for( i <- 0 until 8 ){
|
||
when( io.intSlvTrig(i) ){
|
||
intStatus(8+i) := true.B
|
||
}
|
||
}
|
||
|
||
//下行接收硬件错误
|
||
when( io.intHWTrig(0) ){
|
||
intStatus(29) := true.B
|
||
}
|
||
|
||
when( io.intHWTrig(1) ){
|
||
intStatus(30) := true.B
|
||
}
|
||
//上行接收硬件错误
|
||
|
||
//写清中断
|
||
for( i <- 0 until 8 ){
|
||
when( dataw.extract(i) & isEnW & addrw === "h78".U ){
|
||
intStatus(i) := false.B
|
||
}
|
||
when( dataw.extract(i) & isEnW & addrw === "h79".U ){
|
||
intStatus(i+8) := false.B
|
||
}
|
||
when( dataw.extract(i) & isEnW & addrw === "h7a".U ){
|
||
intStatus(i+16) := false.B
|
||
}
|
||
when( dataw.extract(i) & isEnW & addrw === "h7b".U ){
|
||
intStatus(i+24) := false.B
|
||
}
|
||
}
|
||
|
||
io.intHWClr(0) := dataw.extract(5) & isEnW & addrw === "h7b".U
|
||
io.intHWClr(1) := dataw.extract(6) & isEnW & addrw === "h7b".U
|
||
|
||
val intPulse = RegInit(false.B)
|
||
val intPulseResetCnt = RegInit(0.U(15.W))
|
||
|
||
val trigIntPulse =
|
||
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
|
||
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
|
||
false.B | //主站发送周期到了
|
||
io.wdtTrigger.reduce(_|_) | //主站接收看门狗溢出
|
||
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
|
||
io.intHWTrig(0) | io.intHWTrig(1)//下行接收硬件错误
|
||
|
||
when( intPulseResetCnt === intPulseWidth ){
|
||
intPulse := false.B
|
||
} .elsewhen( trigIntPulse ){
|
||
intPulse := true.B
|
||
}
|
||
|
||
when( trigIntPulse ){
|
||
intPulseResetCnt := 0.U
|
||
} .elsewhen( (intPulseResetCnt < intPulseWidth) & (intPulse === true.B) ){
|
||
intPulseResetCnt := intPulseResetCnt + 1.U
|
||
}
|
||
|
||
io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
|
||
|
||
|
||
}
|
||
|
||
|
||
trait InterfaceEvent{ this: InterfaceBase =>
|
||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||
|
||
val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||
val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||
|
||
|
||
val posedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
|
||
val negedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
|
||
|
||
val mcuSMTimeStampEnq = RegInit(0.U(64.W))
|
||
val mcuSMTimeStampDeq = RegInit(0.U(64.W))
|
||
val lvdsSMTimeStampEnq = RegInit(0.U(64.W))
|
||
val lvdsSMTimeStampDeq = RegInit(0.U(64.W))
|
||
|
||
for( i <- 0 until 2 ){
|
||
when( dataw.extract(0) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
|
||
isPosedgeLatch(i):= false.B
|
||
posedgeTimeStampLatch(i) := 0.U
|
||
} .elsewhen( ~RegNext(io.latchPin(i), false.B) & io.latchPin(i) ){
|
||
when( isPosedgeOnce(i) ){
|
||
isPosedgeLatch(i) := true.B
|
||
}
|
||
when(~isPosedgeLatch(i)){
|
||
posedgeTimeStampLatch(i) := cReg.timeStamp
|
||
}
|
||
}
|
||
|
||
when( dataw.extract(1) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
|
||
isNegedgeLatch(i) := false.B
|
||
negedgeTimeStampLatch(i) := 0.U
|
||
} .elsewhen( RegNext(io.latchPin(i), false.B) & ~io.latchPin(i) ){
|
||
when( isNegedgeOnce(i) ){
|
||
isNegedgeLatch(i) := true.B
|
||
}
|
||
when(~isNegedgeLatch(i)){
|
||
negedgeTimeStampLatch(i) := cReg.timeStamp
|
||
}
|
||
}
|
||
|
||
when( io.uSMenq.reduce(_|_) ){
|
||
mcuSMTimeStampEnq := cReg.timeStamp
|
||
}
|
||
|
||
when( io.dSMdeq.reduce(_|_) ){
|
||
mcuSMTimeStampDeq := cReg.timeStamp
|
||
}
|
||
|
||
when( io.lvdsSMEnq.reduce(_|_) ){
|
||
lvdsSMTimeStampEnq := cReg.timeStamp
|
||
}
|
||
|
||
when( io.lvdsSMDeq.reduce(_|_) ){
|
||
lvdsSMTimeStampDeq := cReg.timeStamp
|
||
}
|
||
|
||
cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)
|
||
|
||
cReg.event.latchStatus(i) := Cat( io.latchPin(i), isNegedgeLatch(i), isPosedgeLatch(i) )
|
||
cReg.event.posedgeTimeStampLatch(i) := posedgeTimeStampLatch(i)
|
||
cReg.event.negedgeTimeStampLatch(i) := negedgeTimeStampLatch(i)
|
||
}
|
||
|
||
cReg.event.mcuSMTimeStampEnq := mcuSMTimeStampEnq
|
||
cReg.event.mcuSMTimeStampDeq := mcuSMTimeStampDeq
|
||
cReg.event.lvdsSMTimeStampEnq := lvdsSMTimeStampEnq
|
||
cReg.event.lvdsSMTimeStampDeq := lvdsSMTimeStampDeq
|
||
}
|
||
|
||
class Interface extends InterfaceBase
|
||
with InterfaceMCUop
|
||
with InterfaceCheckSM
|
||
with InterfaceLVDSop
|
||
with InterfaceSync
|
||
// with InterfaceWdt
|
||
with InterfaceSystem
|
||
with InterfaceEvent
|
||
{
|
||
|
||
|
||
io.txReq.bits.txSM := mReg.txSM
|
||
io.txReq.bits.rxSM := mReg.rxSM
|
||
// io.txReq.bits.txLength := //mReg.txLength
|
||
io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U
|
||
|
||
|
||
|
||
|
||
sReg.localDevIndex := io.localDevIndex
|
||
|
||
// sReg.isDevOnLeft := io.isDevOnLeft
|
||
// sReg.isDevOnLeftModify := io.isDevOnLeftModify
|
||
// sReg.indexOfLeftDev := io.indexOfLeftDev
|
||
sReg.isDevOnRight := io.isDevOnRight
|
||
sReg.isDevOnRightModify := io.isDevOnRightModify
|
||
sReg.indexOfRightDev := io.indexOfRightDev
|
||
|
||
io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
|
||
io.initEncryptor.bits := cReg.encryptKey
|
||
|
||
|
||
} |