latch事件寄存器编译通过
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Ruige Lee
@@ -33,19 +33,6 @@ class CommonRegisterBundle extends Bundle{
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val intStatus = UInt(32.W)
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val intMode = UInt(16.W)
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// val upRecErrorCnt = UInt(32.W)
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// val downRecErrorCnt = UInt(32.W)
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// val upForwardErrorCnt = UInt(32.W)
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// val downForwardErrorCnt = UInt(32.W)
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// val qspiErrorCnt = UInt(32.W)
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// val forwardCnt = UInt(32.W)
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// val recByteCnt = UInt(32.W)
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// val forwardByteCnt = UInt(32.W)
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val wdtStatus = UInt(32.W)
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val wdtEnable = UInt(32.W)
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val wdtTarCnt = Vec( 17, UInt(32.W) )
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@@ -61,48 +48,33 @@ class CommonRegisterBundle extends Bundle{
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val smUsedDepth = Vec(8, UInt(8.W))
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val smTrigLen = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
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val event = new Bundle{
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val latchCtl = Vec(2, UInt(4.W))
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val latchStatus = Vec(2, UInt(4.W))
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val posedgeTimeStampLatch = Vec(2, UInt(64.W))
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val negedgeTimeStampLatch = Vec(2, UInt(64.W))
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val mcuSMTimeStampEnq = UInt(64.W)
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val mcuSMTimeStampDeq = UInt(64.W)
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val lvdsSMTimeStampEnq = UInt(64.W)
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val lvdsSMTimeStampDeq = UInt(64.W)
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}
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}
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class MasterRegisterBundle extends Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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val rplTimeStampTx = UInt(16.W)
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}
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class SlaveRegisterBundle extends Bundle{
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// val RAMSize = UInt(8.W)
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// val MMUNum = UInt(8.W)
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// val nodeSeqAddr = UInt(16.W)
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// val nodeSetAddr = UInt(16.W)
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val ebmmu = Vec(8, new EBMMU_Bundle)
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// val intStatus = UInt(16.W)
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// val mb = Vec(8, new Bundle{
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// val ctrl = UInt(8.W)
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// val status = UInt(8.W)
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// })
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val localDevIndex = UInt(16.W)
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//链路寄存器组
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// val isDevOnLeftModify = Bool()
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// val indexOfLeftDev = UInt(14.W)
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val isDevOnRight = UInt(2.W)
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val isDevOnRightModify = Bool()
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val indexOfRightDev = UInt(14.W)
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@@ -115,14 +87,8 @@ class SlaveRegisterBundle extends Bundle{
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val syncCfg = UInt(8.W)
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val syncWidth = Vec(4, UInt(16.W) )
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val syncOffset = Vec(4, UInt(32.W))
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}
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@@ -134,10 +100,6 @@ class InterfaceIO extends Bundle{
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val lvds = Flipped(new RegAccessInterfaceIO)
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// val modeSel = Output(Bool())
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val txReq = Valid(new Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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@@ -147,6 +109,9 @@ class InterfaceIO extends Bundle{
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val dSMdeq = Output( Vec(4, Bool()) )
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val uSMenq = Output( Vec(4, Bool()) )
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val lvdsSMEnq = Input(Vec(4, Bool()))
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val lvdsSMDeq = Input(Vec(4, Bool()))
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val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
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val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
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@@ -156,10 +121,6 @@ class InterfaceIO extends Bundle{
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val localDevIndex = Input(UInt(16.W))
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// val isDevOnLeft = Input(UInt(2.W))
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// val isDevOnLeftModify = Input(Bool())
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// val indexOfLeftDev = Input(UInt(14.W))
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val isDevOnRight = Input(UInt(2.W))
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val isDevOnRightModify = Input(Bool())
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val indexOfRightDev = Input(UInt(14.W))
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@@ -186,6 +147,8 @@ class InterfaceIO extends Bundle{
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val smUsedDepth = Input( Vec(8, UInt(8.W)) )
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val isSMReset = Output( Vec(8, Bool()) )
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val latchPin = Input(Vec(2, Bool()))
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}
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@@ -408,7 +371,38 @@ abstract class InterfaceBase extends Module{
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(for( i <- 0 until 17; j <- 0 until 4 ) yield {
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( addr === ("h408".U(16.W) + (4*i+j).U) ) -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
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}) ++
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Seq(
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(addr === "h500".U ) -> cReg.event.latchCtl(0),
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(addr === "h502".U ) -> cReg.event.latchCtl(1),
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(addr === "h504".U ) -> cReg.event.latchStatus(0),
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(addr === "h506".U ) -> cReg.event.latchStatus(1),
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) ++
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( 0 until 8 ).map{ i =>
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( addr === ("h508".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h510".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h518".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h520".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h528".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h530".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h538".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
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} ++
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( 0 until 8 ).map{ i =>
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( addr === ("h540".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
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} ++
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Seq()
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)
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@@ -968,6 +962,77 @@ trait InterfaceSystem{ this: InterfaceBase =>
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}
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trait InterfaceEvent{ this: InterfaceBase =>
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val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
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val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
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val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
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val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
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val posedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
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val negedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
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val mcuSMTimeStampEnq = RegInit(0.U(64.W))
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val mcuSMTimeStampDeq = RegInit(0.U(64.W))
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val lvdsSMTimeStampEnq = RegInit(0.U(64.W))
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val lvdsSMTimeStampDeq = RegInit(0.U(64.W))
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for( i <- 0 until 2 ){
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when( dataw.extract(0) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
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isPosedgeLatch(i):= false.B
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posedgeTimeStampLatch(i) := 0.U
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} .elsewhen( ~RegNext(io.latchPin(i), false.B) & io.latchPin(i) ){
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when( isPosedgeOnce(i) ){
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isPosedgeLatch(i) := true.B
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}
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when(~isPosedgeLatch(i)){
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posedgeTimeStampLatch(i) := cReg.timeStamp
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}
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}
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when( dataw.extract(1) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
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isNegedgeLatch(i) := false.B
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negedgeTimeStampLatch(i) := 0.U
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} .elsewhen( RegNext(io.latchPin(i), false.B) & ~io.latchPin(i) ){
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when( isNegedgeOnce(i) ){
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isNegedgeLatch(i) := true.B
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}
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when(~isNegedgeLatch(i)){
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negedgeTimeStampLatch(i) := cReg.timeStamp
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}
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}
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when( io.uSMenq.reduce(_|_) ){
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mcuSMTimeStampEnq := cReg.timeStamp
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}
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when( io.dSMdeq.reduce(_|_) ){
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mcuSMTimeStampDeq := cReg.timeStamp
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}
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when( io.lvdsSMEnq.reduce(_|_) ){
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lvdsSMTimeStampEnq := cReg.timeStamp
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}
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when( io.lvdsSMDeq.reduce(_|_) ){
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lvdsSMTimeStampDeq := cReg.timeStamp
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}
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cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)
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cReg.event.latchStatus(i) := Cat( io.latchPin(i), isNegedgeLatch(i), isPosedgeLatch(i) )
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cReg.event.posedgeTimeStampLatch(i) := posedgeTimeStampLatch(i)
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cReg.event.negedgeTimeStampLatch(i) := negedgeTimeStampLatch(i)
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}
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cReg.event.mcuSMTimeStampEnq := mcuSMTimeStampEnq
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cReg.event.mcuSMTimeStampDeq := mcuSMTimeStampDeq
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cReg.event.lvdsSMTimeStampEnq := lvdsSMTimeStampEnq
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cReg.event.lvdsSMTimeStampDeq := lvdsSMTimeStampDeq
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}
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class Interface extends InterfaceBase
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with InterfaceMCUop
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with InterfaceCheckSM
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@@ -975,6 +1040,7 @@ with InterfaceLVDSop
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with InterfaceSync
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// with InterfaceWdt
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with InterfaceSystem
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with InterfaceEvent
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{
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