修正Makefile下在linux下编译问题,增加了对gcc版本的判断,添加-rv32izicsr的开关
This commit is contained in:
41
Makefile
41
Makefile
@@ -1,3 +1,11 @@
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TARGET=riscv64-unknown-elf
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RVCC=$(TARGET)-gcc
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RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
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MARCH=-march=rv32i -mabi=ilp32
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CFLAGS=-O2
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ifeq "$(RVCCVERSION)" "12.2.0"
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MARCH=-march=rv32izicsr -mabi=ilp32
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endif
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.PHONY: compile tb wave
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.PHONY: compile tb wave
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@@ -25,7 +33,6 @@ back:
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cp ./src/main/verilog/defineParam.v ./generated/back/
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cp ./src/main/verilog/defineParam.v ./generated/back/
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ef:
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ef:
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sbt "test:runMain test.testModule"
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sbt "test:runMain test.testModule"
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@@ -61,64 +68,64 @@ sw:
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rm ./tb/sw/build/* -f
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rm ./tb/sw/build/* -f
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mkdir -p ./tb/sw/build/
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mkdir -p ./tb/sw/build/
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/ -I ./tb/sw/src \
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-c ./tb/sw/src/mstStartup.S \
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-c ./tb/sw/src/mstStartup.S \
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-o ./tb/sw/build/mstStartup.o
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-o ./tb/sw/build/mstStartup.o
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riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
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$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/mstMain.c \
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-c ./tb/sw/src/MstMain.c \
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-o ./tb/sw/build/mstMain.o
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-o ./tb/sw/build/mstMain.o
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# riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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# $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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# -I ./tb/sw/ -I ./tb/sw/src \
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# -I ./tb/sw/ -I ./tb/sw/src \
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# -c ./tb/sw/src/mstMain.S \
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# -c ./tb/sw/src/mstMain.S \
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# -o ./tb/sw/build/mstMain.o
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# -o ./tb/sw/build/mstMain.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/mstStartup.o \
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./tb/sw/build/mstStartup.o \
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./tb/sw/build/mstMain.o \
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./tb/sw/build/mstMain.o \
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-o ./tb/sw/build/mstTest.elf
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-o ./tb/sw/build/mstTest.elf
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riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
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$(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
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riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
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$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
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riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog
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$(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
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riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
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$(RVCC) -O3 -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/slvMain.c \
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-c ./tb/sw/src/SlvMain.c \
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-o ./tb/sw/build/slvMain.o
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-o ./tb/sw/build/slvMain.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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$(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/ -I ./tb/sw/src \
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-c ./tb/sw/src/slvStartup.S \
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-c ./tb/sw/src/slvStartup.S \
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-o ./tb/sw/build/slvStartup.o
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-o ./tb/sw/build/slvStartup.o
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# riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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# $(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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# -I ./tb/sw/ -I ./tb/sw/src \
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# -I ./tb/sw/ -I ./tb/sw/src \
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# -c ./tb/sw/src/slvMain.S \
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# -c ./tb/sw/src/slvMain.S \
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# -o ./tb/sw/build/slvMain.o
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# -o ./tb/sw/build/slvMain.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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$(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/slvStartup.o \
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./tb/sw/build/slvStartup.o \
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./tb/sw/build/slvMain.o \
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./tb/sw/build/slvMain.o \
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-o ./tb/sw/build/slvTest.elf
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-o ./tb/sw/build/slvTest.elf
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riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin
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$(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin
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riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
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$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
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riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog
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$(TARGET)-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
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python3 ./tb/sw/bin_to_hex.py
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python3 ./tb/sw/bin_to_hex.py
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