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remove error

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RuigeLee
2023-11-02 15:25:26 +08:00
parent 9d08c298de
commit 3774d56391
4 changed files with 0 additions and 79 deletions
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1
src/main/scala/Switch/mac/MacStatus.scala
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@@ -8,7 +8,6 @@ class MacStatusIO extends Bundle{
val MRxClk = Input(Bool())
val RxCrcError = Input(Bool())
val MRxErr = Input(Bool())
val MRxDV = Input(Bool())
val RxStateSFD = Input(Bool())
val RxStateData = Input(UInt(2.W))

2
src/main/scala/Switch/mac/MacTx.scala
View File

@@ -22,7 +22,6 @@ class MacTxIO extends Bundle{
val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)
val MTxEn = Output(Bool()) // Transmit enable (to PHY)
val MTxErr = Output(Bool()) // Transmit error (to PHY)
val TxDone = Output(Bool()) // Transmit packet done (to RISC)
val TxAbort = Output(Bool()) // Transmit packet abort (to RISC)
val TxUsedData = Output(Bool()) // Transmit packet used data (to RISC)
@@ -281,7 +280,6 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
val TxAbort = RegInit(false.B); io.TxAbort := ~io.TxStartFrm & TxAbort
val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
io.MTxErr := false.B
val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit