diff --git a/src/main/scala/Switch/MAC.scala b/src/main/scala/Switch/MAC.scala
index 47aba9c..5fc4171 100644
--- a/src/main/scala/Switch/MAC.scala
+++ b/src/main/scala/Switch/MAC.scala
@@ -15,13 +15,11 @@ class MII extends Bundle with MDIO{
   val mtx_clk_pad_i = Input(Bool())
   val mtxd_pad_o    = Output(UInt(4.W))
   val mtxen_pad_o   = Output(Bool())
-  val mtxerr_pad_o  = Output(Bool())
 
   // Rx
   val mrx_clk_pad_i = Input(Bool())
   val mrxd_pad_i    = Input(UInt(4.W))
   val mrxdv_pad_i   = Input(Bool())
-  val mrxerr_pad_i  = Input(Bool())
 
   // Common Tx and Rx
   val mcoll_pad_i = Input(Bool())
@@ -112,7 +110,6 @@ abstract class Mac(implicit p: Parameters) extends SwitchNode{
   val r_TxEn                     = Wire(Bool())
   val r_RxEn                     = Wire(Bool())
   val MRxDV_Lb                   = Wire(Bool())
-  val MRxErr_Lb                  = Wire(Bool())
   val MRxD_Lb                    = Wire(UInt(4.W))
   val Transmitting               = Wire(Bool())
   val DribbleNibble              = Wire(Bool())
@@ -232,9 +229,6 @@ abstract class Mac(implicit p: Parameters) extends SwitchNode{
   // Muxed MII receive data valid
   MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync)
 
-  // Muxed MII Receive Error
-  MRxErr_Lb := Mux(r_LoopBck, io.mii.mtxerr_pad_o, io.mii.mrxerr_pad_i & RxEnSync)
-
   // Muxed MII Receive Data
   MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
 
@@ -256,7 +250,6 @@ abstract class Mac(implicit p: Parameters) extends SwitchNode{
 
   io.mii.mtxd_pad_o    := txethmac.io.MTxD
   io.mii.mtxen_pad_o   := txethmac.io.MTxEn
-  io.mii.mtxerr_pad_o := txethmac.io.MTxErr
   TxDone := txethmac.io.TxDone
   TxAbort := txethmac.io.TxAbort
   TxUsedData := txethmac.io.TxUsedData
@@ -354,7 +347,6 @@ abstract class Mac(implicit p: Parameters) extends SwitchNode{
   macstatus.io.asyncReset          := io.asyncReset
   macstatus.io.MRxClk              := io.mii.mrx_clk_pad_i
   macstatus.io.RxCrcError          := RxCrcError
-  macstatus.io.MRxErr              := MRxErr_Lb
   macstatus.io.MRxDV               := MRxDV_Lb
   macstatus.io.RxStateSFD          := RxStateSFD
   macstatus.io.RxStateData         := RxStateData
diff --git a/src/main/scala/Switch/TxBuff.scala.bk b/src/main/scala/Switch/TxBuff.scala.bk
deleted file mode 100644
index d018398..0000000
--- a/src/main/scala/Switch/TxBuff.scala.bk
+++ /dev/null
@@ -1,68 +0,0 @@
-package Switch
-
-import chisel3._
-import chisel3.util._
-
-import MAC._
-
-
-
-
-class TxBuffIO extends Bundle{
-  val enq = Flipped(Decoupled(new Mac_Stream_Bundle))
-  val deq = Decoupled(new Mac_Stream_Bundle)
-}
-
-
-abstract class TxBuffBase(val threshold: Int = 8) extends Module{
-  val io: TxBuffIO = IO(new TxBuffIO)
-
-  val buff = Module(new Queue( new Mac_Stream_Bundle, 2048 ))
-  val enqCnt = Reg(UInt(16.W))
-
-}
-
-
-trait TxBuffEnq{ this: TxBuffBase =>
-    io.enq <> buff.io.enq
-
-
-    when( io.enq.fire ){
-      when( io.enq.bits.isStart ) {
-        enqCnt := 0.U
-      } .elsewhen( io.enq.bits.isLast ){
-
-      } .elsewhen( enqCnt === threshold.U ){
-        enqCnt := enqCnt
-      } .otherwise{
-        enqCnt := enqCnt + 1.U        
-      }
-    } 
-
-}
-
-trait TxBuffDeq{ this: TxBuffBase =>
-
-  val isReach = RegInit(false.B)
-
-  when( io.enq.fire ){
-    when( io.enq.bits.isStart ) {
-      isReach := false.B
-    } .elsewhen(
-        io.enq.bits.isLast ||
-        (if( threshold != 0 ) {enqCnt === threshold.U} else {false.B})
-      ){
-      isReach := true.B
-    }
-  }
-
-    
-    enqCnt === threshold.U
-
-  io.deq.bits := buff.io.deq.bits
-  io.deq.valid := buff.io.deq.valid & isReach
-  buff.io.deq.ready := io.deq.ready & isReach
-}
-
-
-
diff --git a/src/main/scala/Switch/mac/MacStatus.scala b/src/main/scala/Switch/mac/MacStatus.scala
index 6c6626d..e955ab1 100644
--- a/src/main/scala/Switch/mac/MacStatus.scala
+++ b/src/main/scala/Switch/mac/MacStatus.scala
@@ -8,7 +8,6 @@ class MacStatusIO extends Bundle{
 
   val MRxClk              = Input(Bool())
   val RxCrcError          = Input(Bool())
-  val MRxErr              = Input(Bool())
   val MRxDV               = Input(Bool())
   val RxStateSFD          = Input(Bool())
   val RxStateData         = Input(UInt(2.W))
diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala
index e86712e..67fc942 100644
--- a/src/main/scala/Switch/mac/MacTx.scala
+++ b/src/main/scala/Switch/mac/MacTx.scala
@@ -22,7 +22,6 @@ class MacTxIO extends Bundle{
 
   val MTxD               = Output(UInt(4.W))     // Transmit nibble (to PHY)
   val MTxEn              = Output(Bool())     // Transmit enable (to PHY)
-  val MTxErr             = Output(Bool())     // Transmit error (to PHY)
   val TxDone             = Output(Bool())     // Transmit packet done (to RISC)
   val TxAbort            = Output(Bool())     // Transmit packet abort (to RISC)
   val TxUsedData         = Output(Bool())     // Transmit packet used data (to RISC)
@@ -281,7 +280,6 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
   val TxAbort = RegInit(false.B); io.TxAbort := ~io.TxStartFrm & TxAbort
 
   val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
-  io.MTxErr := false.B
 
   val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit