mst test pass

2023-08-01 14:44:05 +08:00
parent 24800cce9d
commit 35e6fcdb52
5 changed files with 254 additions and 7 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
      ChiselGeneratorAnnotation(() => {
-    new BackBoardMst
+    new BackPlaneMstTest
  })
    ))