diff --git a/Makefile b/Makefile index e894771..63039fe 100644 --- a/Makefile +++ b/Makefile @@ -81,16 +81,16 @@ VSimBack: --timescale "1 ns / 1 ps" \ -y ${PWD}/tb/ \ -y ${PWD}/generated/ \ - --top-module BackBoardSlvTest \ + --top-module BackPlaneMstTest \ --trace-fst \ - --cc ./generated/BackBoardSlvTest.v \ + --cc ./generated/BackPlaneMstTest.v \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_DELAY=0 \ --exe --build \ - ${PWD}/tb/sim_backSlv.cpp \ + ${PWD}/tb/sim_backMst.cpp \ -Mdir ./tb/build/ \ -j 30 diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala index 93b7ac0..b71369c 100644 --- a/src/main/scala/backBoard/SpiSlv.scala +++ b/src/main/scala/backBoard/SpiSlv.scala @@ -29,11 +29,11 @@ class SpiSlv extends Module with RequireAsyncReset{ io.CDRIn.ready := io.CS io.interrupt := false.B - io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 ) + io.MISO := RegNext(centReg.asUInt.extract( 6+8+32+2+16-1 )) when( ~io.CS ){ - centReg := Cat(centReg.asUInt << 1, io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle) + centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle) } .otherwise{ when( io.CDROut.fire ){ @@ -59,7 +59,7 @@ class SpiSlv extends Module with RequireAsyncReset{ when( io.CDROut.fire ){ CDROutValid := false.B - } .elsewhen( centReg.op === OPMSTT & ~CDROutValid ){ + } .elsewhen( io.CS & centReg.op === OPMSTT & ~CDROutValid ){ CDROutValid := true.B diff --git a/src/test/scala/gcd/BackPlaneMstTest.scala b/src/test/scala/gcd/BackPlaneMstTest.scala new file mode 100644 index 0000000..2858dc2 --- /dev/null +++ b/src/test/scala/gcd/BackPlaneMstTest.scala @@ -0,0 +1,72 @@ +package BACK + +import chisel3._ +import chisel3.util._ + +class BackPlaneMstTestIO extends Bundle{ + + val SCK = Input(Bool()) + val interrupt = Output(Bool()) + val clk4 = Input( Bool() ) + val reset = Input(Bool()) + + val downStreamRespdat = Output(Bool()) + + val req = Flipped(Decoupled(new CDRData)) + val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle)) + +} + +class BackPlaneMstTest extends RawModule{ + val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO) + + withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){ + val dut = Module(new BackBoardMst) + + io.downStreamRespdat := dut.io.downStreamRespdat + + // dut.io.CS := io.CS + // io.MISO := dut.io.MISO + // dut.io.MOSI := io.MOSI + dut.io.SCK := ~io.SCK + + dut.io.clk4 := io.clk4 + io.interrupt := dut.io.interrupt + + dut.io.reset := io.reset + + io.req.ready := true.B + val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat + val reqInfo = RegInit(0.U((new CDRData).getWidth.W)) + + when( io.req.fire ){ + reqInfo := io.req.bits.asUInt + reqDat := true.B + } .otherwise{ + reqDat := reqInfo.extract( 6+8+32+16-1 ) + reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) + } + + io.spi.ready := true.B + val cnt = RegInit(0.U(7.W)) + val spiInfo = Reg( new CDR_Master_Interface_Bundle ) + val MOSI = RegInit(false.B); dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 ) + val cs = RegInit(true.B); dut.io.CS := cs + + when( io.spi.fire ){ + cs := false.B + cnt := 0.U + spiInfo := io.spi.bits + } .elsewhen( cnt =/= 63.U ){ + cnt := cnt + 1.U + spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle) + } .elsewhen( cnt === 63.U ){ + cs := true.B + } + + } + + + +} + diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 61637df..338dad7 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._ object testModule extends App { (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { - new BackBoardMst + new BackPlaneMstTest }) )) diff --git a/tb/sim_backMst.cpp b/tb/sim_backMst.cpp new file mode 100644 index 0000000..f39d35b --- /dev/null +++ b/tb/sim_backMst.cpp @@ -0,0 +1,175 @@ +/* + Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +#include +#include "VBackPlaneMstTest.h" +#include +#include +#include + +#include + + + +#if VM_TRACE +#include "verilated_fst_c.h" +#endif + + +char* img; +VBackPlaneMstTest *top; +#if VM_TRACE +VerilatedFstC* tfp; +#endif +vluint64_t main_time = 0; + +double sc_time_stamp () { + return main_time; +} + + + +static void sim_exit(){ +#if VM_TRACE + tfp->close(); +#endif + + top->final(); + + delete top; +} + + + + + + +int main(int argc, char **argv, char **env) { + + + top = new VBackPlaneMstTest(); + +#if VM_TRACE + tfp = new VerilatedFstC; + Verilated::traceEverOn(true); + top->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("./tb/build/wave.fst"); +#endif + + + + + + + + + + + + + + + + + top->io_reset = 1; + top->io_SCK = 0; + top->io_clk4 = 0; + + while(!Verilated::gotFinish()) { + + Verilated::timeInc(1); + + if ( main_time != 1000 ){ + } else { + top->io_reset = 0; + } + + if ( main_time % 400 == 100 ) { + top->io_SCK = 1; + } else if ( main_time % 400 == 300 ) { + top->io_SCK = 0; + } + + if ( main_time % 100 == 10 ) { + top->io_clk4 = 1; + } else if ( main_time % 100 == 60 ) { + top->io_clk4 = 0; + } + + + if( main_time == 50000 ){ + top->io_spi_valid = 1; + top->io_spi_bits_address = 0x11 << 1 | 0x00; + top->io_spi_bits_register = 0x0; + top->io_spi_bits_data = 0xaa; + top->io_spi_bits_op = 0x01; + top->io_spi_bits_hash = 0x0; + + } else if( main_time == 50400 ){ + top->io_spi_valid = 0; + } + + if( main_time == 150000 ){ + top->io_req_valid = 1; + top->io_req_bits_address = 0x11 << 1 | 0x00; + top->io_req_bits_register = 0x0; + top->io_req_bits_data = 0xaa; + } else if( main_time == 150400 ){ + top->io_req_valid = 0; + } + + if( main_time == 250000 ){ + top->io_spi_valid = 1; + top->io_spi_bits_address = 0x11 << 1 | 0x01; + top->io_spi_bits_register = 0x0; + top->io_spi_bits_data = 0x55; + top->io_spi_bits_op = 0x00; + top->io_spi_bits_hash = 0x0; + + } else if( main_time == 250400 ){ + top->io_spi_valid = 0; + } + + + + top->eval(); +#if VM_TRACE + tfp->dump(Verilated::time()); + +#endif + + + main_time ++; + + if( main_time > 450000 ){ + break; + } + } + + sim_exit(); + return -1; + + +} + + + + + + + +