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mst test pass

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This commit is contained in:
RuigeLee
2023-08-01 14:44:05 +08:00
parent 24800cce9d
commit 35e6fcdb52
5 changed files with 254 additions and 7 deletions
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6
src/main/scala/backBoard/SpiSlv.scala
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@@ -29,11 +29,11 @@ class SpiSlv extends Module with RequireAsyncReset{
io.CDRIn.ready := io.CS
io.interrupt := false.B
io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
io.MISO := RegNext(centReg.asUInt.extract( 6+8+32+2+16-1 ))
when( ~io.CS ){
centReg := Cat(centReg.asUInt << 1, io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
} .otherwise{
when( io.CDROut.fire ){
@@ -59,7 +59,7 @@ class SpiSlv extends Module with RequireAsyncReset{
when( io.CDROut.fire ){
CDROutValid := false.B
} .elsewhen( centReg.op === OPMSTT & ~CDROutValid ){
} .elsewhen( io.CS & centReg.op === OPMSTT & ~CDROutValid ){
CDROutValid := true.B