mst test pass

src/main/scala/backBoard/SpiSlv.scala

@@ -29,11 +29,11 @@ class SpiSlv extends Module with RequireAsyncReset{
 
   io.CDRIn.ready := io.CS
   io.interrupt   := false.B
-  io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
+  io.MISO := RegNext(centReg.asUInt.extract( 6+8+32+2+16-1 ))
 
   when( ~io.CS ){
     
-    centReg := Cat(centReg.asUInt << 1, io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
+    centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
   } .otherwise{
 
     when( io.CDROut.fire ){
@@ -59,7 +59,7 @@ class SpiSlv extends Module with RequireAsyncReset{
 
   when( io.CDROut.fire ){
     CDROutValid := false.B
-  } .elsewhen( centReg.op === OPMSTT & ~CDROutValid ){
+  } .elsewhen( io.CS & centReg.op === OPMSTT & ~CDROutValid ){
     CDROutValid := true.B
 
 

src/test/scala/gcd/BackPlaneMstTest.scala

@@ -0,0 +1,72 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class BackPlaneMstTestIO extends Bundle{
+
+  val SCK  = Input(Bool())
+  val interrupt = Output(Bool())
+  val clk4            = Input( Bool() )
+  val reset = Input(Bool())
+
+  val downStreamRespdat = Output(Bool())
+
+  val req = Flipped(Decoupled(new CDRData))
+  val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
+
+}
+
+class BackPlaneMstTest extends RawModule{
+  val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO)
+
+  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
+    val dut = Module(new BackBoardMst)
+
+    io.downStreamRespdat := dut.io.downStreamRespdat
+
+    // dut.io.CS   := io.CS
+    // io.MISO     := dut.io.MISO
+    // dut.io.MOSI := io.MOSI
+    dut.io.SCK  := ~io.SCK
+
+    dut.io.clk4 := io.clk4
+    io.interrupt := dut.io.interrupt
+
+    dut.io.reset := io.reset
+
+    io.req.ready := true.B
+    val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
+    val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
+
+    when( io.req.fire ){
+      reqInfo := io.req.bits.asUInt
+      reqDat := true.B
+    } .otherwise{
+      reqDat := reqInfo.extract( 6+8+32+16-1 )
+      reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+    }
+
+    io.spi.ready := true.B
+    val cnt = RegInit(0.U(7.W))
+    val spiInfo = Reg( new CDR_Master_Interface_Bundle )
+    val MOSI = RegInit(false.B); dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
+    val cs   = RegInit(true.B);  dut.io.CS   := cs
+
+    when( io.spi.fire ){
+      cs := false.B
+      cnt := 0.U
+      spiInfo := io.spi.bits
+    } .elsewhen( cnt =/= 63.U ){
+      cnt := cnt + 1.U
+      spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
+    } .elsewhen( cnt === 63.U ){
+      cs := true.B
+    }
+
+  }
+
+
+
+}
+

src/test/scala/gcd/test.scala

@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    new BackBoardMst
+    new BackPlaneMstTest
   })
     ))