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加入CDR的滤波，并修改测试led

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This commit is contained in:
Ruige Lee
2025-07-28 14:31:45 +08:00
parent 20f45581e6
commit 302893c3e7
2 changed files with 17 additions and 7 deletions
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22
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -26,9 +26,17 @@ abstract class CDRInBase extends Module{
} }
trait CDRInOverSample{ this: CDRInBase => trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
val flitReg = for( i <- 0 until sampleRate ) yield {
withClockAndReset(io.overCLK.asClock, reset.asBool){
RegNext(
(sampleReg(i) & sampleReg(i+1)) |
(sampleReg(i) & sampleReg(i+2)) |
(sampleReg(i+1) & sampleReg(i+2)), false.B
)
}
}
// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) } // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
// val arbSel = Reg(UInt( log2Ceil(sampleRate).W )) // val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
@@ -51,9 +59,11 @@ trait CDRInOverSample{ this: CDRInBase =>
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
when( sampleReg(0) ^ sampleReg(1) ){ withClockAndReset(io.overCLK.asClock, reset.asBool){
arbLock := arbCnt when( flitReg(0) ^ flitReg(1) ){
arbLock := arbCnt
}
} }
val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
@@ -83,7 +93,7 @@ trait CDRInOverSample{ this: CDRInBase =>
(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate) ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
}) })
) )
)} )}

2
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -73,7 +73,7 @@ abstract class ShinTopBase extends Module{
val interface = Module(new Interface) val interface = Module(new Interface)
io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U ) io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
io.isSoftReset := interface.io.isSoftReset io.isSoftReset := interface.io.isSoftReset
io.interrupt := interface.io.interrupt io.interrupt := interface.io.interrupt