From 302893c3e761cad245358b61c8bfd5c6d63904ac Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 28 Jul 2025 14:31:45 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8A=A0=E5=85=A5CDR=E7=9A=84=E6=BB=A4?=
 =?UTF-8?q?=E6=B3=A2=EF=BC=8C=E5=B9=B6=E4=BF=AE=E6=94=B9=E6=B5=8B=E8=AF=95?=
 =?UTF-8?q?led?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 22 +++++++++++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index fae6248..ddceefc 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -26,9 +26,17 @@ abstract class CDRInBase extends Module{
 }
 
 trait CDRInOverSample{ this: CDRInBase =>
-  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
-
+  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
 
+  val flitReg = for( i <- 0 until sampleRate ) yield {
+    withClockAndReset(io.overCLK.asClock, reset.asBool){
+      RegNext(
+        (sampleReg(i) & sampleReg(i+1)) |
+        (sampleReg(i) & sampleReg(i+2)) |
+        (sampleReg(i+1) & sampleReg(i+2)), false.B
+      )
+    }
+  }
 
   // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
   // val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
@@ -51,9 +59,11 @@ trait CDRInOverSample{ this: CDRInBase =>
 
   val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
   arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
-  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
-  when( sampleReg(0) ^ sampleReg(1) ){
-    arbLock := arbCnt
+  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
+  withClockAndReset(io.overCLK.asClock, reset.asBool){
+    when( flitReg(0) ^ flitReg(1) ){
+      arbLock := arbCnt
+    }
   }
 
   val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
@@ -83,7 +93,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 
       (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
         //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
-        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate)
+        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
       })
     )
   )}
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 4274e3a..f7646eb 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -73,7 +73,7 @@ abstract class ShinTopBase extends Module{
 
   val interface = Module(new Interface)
 
-  io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
+  io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
   
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt