加入CDR的滤波，并修改测试led

2025-07-28 14:31:45 +08:00
parent 20f45581e6
commit 302893c3e7
2 changed files with 17 additions and 7 deletions
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -73,7 +73,7 @@ abstract class ShinTopBase extends Module{

  val interface = Module(new Interface)

-  io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
+  io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
  
  io.isSoftReset := interface.io.isSoftReset
  io.interrupt   := interface.io.interrupt