remove istilelink parameter

2023-07-11 17:45:32 +08:00
parent 44048ea7d9
commit 2d720b7c8d
4 changed files with 9 additions and 10 deletions
--- a/src/test/scala/gcd/Mac_test_top.scala
+++ b/src/test/scala/gcd/Mac_test_top.scala
@@ -27,7 +27,7 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{

 	tlRAM := mac.tlClientNode

-  if( !isTileLink ){} else {
+

 		val tlClientIONode = 
 			TLClientNode(Seq(TLMasterPortParameters.v1(
@@ -42,7 +42,6 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
    val tlSlv = InModuleBody {
      tlClientIONode.makeIOs()
    }
-  }

 	lazy val module = new LazyModuleImp(this) {
 		val io = IO(new MacIO with MDIO)