diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala
index 9fa3d0b..48e7edd 100644
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/mac/MAC.scala
@@ -40,7 +40,7 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
 
 
-class MacIO(implicit p: Parameters) extends MacBundle with MDIO{
+class MacIO extends Bundle with MDIO{
 
   // Tx
   val mtx_clk_pad_i = Input(Bool())
diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala
index df05b59..5dc447b 100644
--- a/src/main/scala/mac/MacTilelink.scala
+++ b/src/main/scala/mac/MacTilelink.scala
@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 
 
 
-abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut)(implicit p: Parameters) extends MacModule{
+abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module{
 
   class MacTileLinkSlaveIO extends Bundle{
     val A = Flipped(Decoupled(new TLBundleA(edgeIn.bundle)))
@@ -26,7 +26,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut)(implicit p:
     val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
   }
 
-  class MacTileLinkIO(implicit p: Parameters) extends MacBundle{
+  class MacTileLinkIO extends Bundle{
 
     val tlSlv = new MacTileLinkSlaveIO
     val tlMst = new MacTileLinkMasterIO
@@ -1465,7 +1465,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
   }
 }
 
-class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut)(implicit p: Parameters) extends MacTileLinkBase(edgeIn, edgeOut) with MacTileLinkTXClk with MacTileLinkRXClk
+class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends MacTileLinkBase(edgeIn, edgeOut) with MacTileLinkTXClk with MacTileLinkRXClk
 
 
 
diff --git a/src/main/scala/mac/Parameters.scala b/src/main/scala/mac/Parameters.scala
index d5795e6..c21ab29 100644
--- a/src/main/scala/mac/Parameters.scala
+++ b/src/main/scala/mac/Parameters.scala
@@ -6,15 +6,15 @@ import freechips.rocketchip.diplomacy._
 
 import org.chipsalliance.cde.config._
 
-abstract class MacModule(implicit val p: Parameters) extends Module with HasMacParameters { def io: Record }
-abstract class MacBundle(implicit val p: Parameters) extends Bundle with HasMacParameters
+// abstract class MacModule(implicit val p: Parameters) extends Module with HasMacParameters { def io: Record }
+// abstract class MacBundle(implicit val p: Parameters) extends Bundle with HasMacParameters
 
 
 case object MacParamsKey extends Field[MacSetting]
 
 
 case class MacSetting(
-  isTileLink: Boolean = true
+  // isTileLink: Boolean = true
 ){
 
 }
@@ -24,7 +24,7 @@ trait HasMacParameters {
 
   val macSetting = p(MacParamsKey)
 
-  def isTileLink = macSetting.isTileLink
+  // def isTileLink = macSetting.isTileLink
 }
 
 class MacCfg extends Config((_, _, _) => {
diff --git a/src/test/scala/gcd/Mac_test_top.scala b/src/test/scala/gcd/Mac_test_top.scala
index 49dc9bf..aec2aec 100644
--- a/src/test/scala/gcd/Mac_test_top.scala
+++ b/src/test/scala/gcd/Mac_test_top.scala
@@ -27,7 +27,7 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
 	tlRAM := mac.tlClientNode
 
-  if( !isTileLink ){} else {
+
 
 		val tlClientIONode = 
 			TLClientNode(Seq(TLMasterPortParameters.v1(
@@ -42,7 +42,6 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
     val tlSlv = InModuleBody {
       tlClientIONode.makeIOs()
     }
-  }
 
 	lazy val module = new LazyModuleImp(this) {
 		val io = IO(new MacIO with MDIO)