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增加一个锁定可以暂时解决发送失败问题

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This commit is contained in:
Ruige Lee
2025-08-18 16:20:50 +08:00
parent 11bbf14226
commit 2afd3f722a
2 changed files with 70 additions and 70 deletions
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108
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -17,6 +17,12 @@ abstract class CDRInBase extends Module{
val io: CDRInIO = IO(new CDRInIO)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
val STATE_PAYLOAD = 2.U
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val syncSerDat = Wire(Bool())
}
@@ -65,92 +71,91 @@ trait CDRInOverSample{ this: CDRInBase =>
}
trait CDRInMultiSample{ this: CDRInBase =>
val testIO = IO(Output(UInt(3.W)))
val testIO = IO(Output(UInt(10.W)))
val clkNum: Int = 16
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(16, Bool())))
val multiCLK = IO(Input(Vec(8, Bool())))
val sampleReg = Wire(Vec(16, Bool()))
val sampleReg = Wire(Vec(8, Bool()))
for( i <- 0 until 16 ) {
for( i <- 0 until 8 ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
}
val sampleReg_sync = Wire(Vec(23,Bool()))
val sampleReg_sync = Wire(Vec(16,Bool()))
for( i <- 0 until 7 ){
sampleReg_sync(i) := RegNext(sampleReg_sync(i+15))
for( i <- 0 until 8 ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
}
for( i <- 7 until 23 ){
sampleReg_sync(i) := RegNext(sampleReg(i-7))
for( i <- 8 until 16 ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i-8), 1)
}
/*
val flitReg =
for( i <- 1 until 22 ) yield {
(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
}
// val flitReg =
// for( i <- 1 until 22 ) yield {
// (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
// (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
// (sampleReg_sync(i+0) & sampleReg_sync(i+1))
// }
// val asyncSerDat = PopCount(flitReg) >= 11.U
val asyncSerDat = PopCount(flitReg) >= 11.U
*/
val flitReg =
for( i <- 6 until 22 ) yield {
for( i <- 1 until 15 ) yield {
(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
}
val arbLock = Reg(UInt( 16.W ))
val arbLock = Reg(UInt( 8.W ))
val isLock = RegInit(false.B)
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
when( ~isLock ){
when( flitReg(0) ^ flitReg(1) ){
arbLock := "b1".U(16.W) << 7
} .elsewhen( flitReg(1) ^ flitReg(2) ){
arbLock := "b1".U(16.W) << 8
} .elsewhen( flitReg(2) ^ flitReg(3) ){
arbLock := "b1".U(16.W) << 9
} .elsewhen( flitReg(3) ^ flitReg(4) ){
arbLock := "b1".U(16.W) << 10
} .elsewhen( flitReg(4) ^ flitReg(5) ){
arbLock := "b1".U(16.W) << 11
} .elsewhen( flitReg(5) ^ flitReg(6) ){
arbLock := "b1".U(16.W) << 12
} .elsewhen( flitReg(6) ^ flitReg(7) ){
arbLock := "b1".U(16.W) << 13
} .elsewhen( flitReg(7) ^ flitReg(8) ){
arbLock := "b1".U(16.W) << 14
} .elsewhen( flitReg(8) ^ flitReg(9) ){
arbLock := "b1".U(16.W) << 15
} .elsewhen( flitReg(9) ^ flitReg(10) ){
arbLock := "b1".U(16.W) << 0
} .elsewhen( flitReg(10) ^ flitReg(11) ){
isLock := true.B
} .elsewhen( flitReg(1) ^ flitReg(2) ){
arbLock := "b1".U(16.W) << 1
} .elsewhen( flitReg(11) ^ flitReg(12) ){
isLock := true.B
} .elsewhen( flitReg(2) ^ flitReg(3) ){
arbLock := "b1".U(16.W) << 2
} .elsewhen( flitReg(12) ^ flitReg(13) ){
isLock := true.B
} .elsewhen( flitReg(3) ^ flitReg(4) ){
arbLock := "b1".U(16.W) << 3
} .elsewhen( flitReg(13) ^ flitReg(14) ){
isLock := true.B
} .elsewhen( flitReg(4) ^ flitReg(5) ){
arbLock := "b1".U(16.W) << 4
} .elsewhen( flitReg(14) ^ flitReg(15) ){
isLock := true.B
} .elsewhen( flitReg(5) ^ flitReg(6) ){
arbLock := "b1".U(16.W) << 5
} .elsewhen( flitReg(15) ^ flitReg(0) ){
isLock := true.B
} .elsewhen( flitReg(6) ^ flitReg(7) ){
arbLock := "b1".U(16.W) << 6
isLock := true.B
} .elsewhen( flitReg(7) ^ flitReg(8) ){
arbLock := "b1".U(16.W) << 7
isLock := true.B
}
} .elsewhen( stateNext === STATE_IDLE & stateCurr === STATE_PAYLOAD ){
isLock := false.B
}
val asyncSerDat =
Mux1H(
(for { i <- 0 until clkNum } yield {
(arbLock === (1.U << i)) -> flitReg(i)
(for { i <- 0 until 8 } yield {
(arbLock === (1.U << i)) -> flitReg(i+4)
})
)
@@ -160,7 +165,7 @@ val arbLock = Reg(UInt( 16.W ))
syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
testIO := Cat( syncSerDat, asyncSerDat, io.serDat )
testIO := Cat( syncSerDat, Cat(flitReg), io.serDat )
}
@@ -172,12 +177,7 @@ trait CDRInAxis{ this: CDRInBase =>
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
val STATE_PAYLOAD = 2.U
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val byteCnt = RegInit(0.U((12+1).W))

4
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val multiCLK = Input(Vec(16, Bool()))
val multiCLK = Input(Vec(8, Bool()))
val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO
@@ -77,7 +77,7 @@ abstract class ShinTopBase extends Module{
io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
io.testIO := Cat(
upCDROut.io.serDat, upCDRIn.testIO, downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
)
io.isSoftReset := interface.io.isSoftReset