259 lines
7.1 KiB
Scala
259 lines
7.1 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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//work in 100MHZ
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class CDRInIO extends Bundle{
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val axis = Decoupled(new AXIS_Bundle(8))
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val serDat = Input(Bool())
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}
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abstract class CDRInBase extends Module{
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val io: CDRInIO = IO(new CDRInIO)
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val STATE_IDLE = 0.U
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val STATE_HEADER = 1.U
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val STATE_PAYLOAD = 2.U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, STATE_IDLE )
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val syncSerDat = Wire(Bool())
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}
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trait CDRInOverSample{ this: CDRInBase =>
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val overCLK = IO(Input(Bool()))
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val sampleRate: Int = 4
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require(sampleRate >= 4)
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val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
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val flitReg = for( i <- 0 until sampleRate ) yield {
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withClockAndReset(overCLK.asClock, reset.asBool){
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RegNext(
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(sampleReg(i) & sampleReg(i+1)) |
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(sampleReg(i) & sampleReg(i+2)) |
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(sampleReg(i+1) & sampleReg(i+2)), false.B
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)
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}
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}
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val arbCnt = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
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val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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withClockAndReset(overCLK.asClock, reset.asBool){
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when( flitReg(0) ^ flitReg(1) ){
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arbLock := arbCnt
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}
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}
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val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
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Mux1H(
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(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
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//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
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((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
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})
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)
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)}
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syncSerDat := ShiftRegister( asyncSerDat, 2 )
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}
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trait CDRInMultiSample{ this: CDRInBase =>
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val testIO = IO(Output(UInt(10.W)))
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val clkNum: Int = 16
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//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
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val multiCLK = IO(Input(Vec(8, Bool())))
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val sampleReg = Wire(Vec(8, Bool()))
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for( i <- 0 until 8 ) {
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sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
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}
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val sampleReg_sync = Wire(Vec(16,Bool()))
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for( i <- 0 until 8 ){
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sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
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}
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for( i <- 8 until 16 ){
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sampleReg_sync(i) := ShiftRegister(sampleReg(i-8), 1)
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}
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/*
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val flitReg =
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for( i <- 1 until 22 ) yield {
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(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
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(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
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(sampleReg_sync(i+0) & sampleReg_sync(i+1))
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}
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val asyncSerDat = PopCount(flitReg) >= 11.U
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*/
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val flitReg =
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for( i <- 1 until 15 ) yield {
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(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
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(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
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(sampleReg_sync(i+0) & sampleReg_sync(i+1))
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}
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val arbLock = Reg(UInt( 8.W ))
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val isLock = RegInit(false.B)
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//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
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when( ~isLock ){
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when( flitReg(0) ^ flitReg(1) ){
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arbLock := "b1".U(16.W) << 0
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isLock := true.B
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} .elsewhen( flitReg(1) ^ flitReg(2) ){
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arbLock := "b1".U(16.W) << 1
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isLock := true.B
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} .elsewhen( flitReg(2) ^ flitReg(3) ){
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arbLock := "b1".U(16.W) << 2
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isLock := true.B
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} .elsewhen( flitReg(3) ^ flitReg(4) ){
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arbLock := "b1".U(16.W) << 3
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isLock := true.B
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} .elsewhen( flitReg(4) ^ flitReg(5) ){
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arbLock := "b1".U(16.W) << 4
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isLock := true.B
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} .elsewhen( flitReg(5) ^ flitReg(6) ){
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arbLock := "b1".U(16.W) << 5
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isLock := true.B
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} .elsewhen( flitReg(6) ^ flitReg(7) ){
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arbLock := "b1".U(16.W) << 6
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isLock := true.B
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} .elsewhen( flitReg(7) ^ flitReg(8) ){
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arbLock := "b1".U(16.W) << 7
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isLock := true.B
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}
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} .elsewhen( stateNext === STATE_IDLE & stateCurr === STATE_PAYLOAD ){
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isLock := false.B
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}
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val asyncSerDat =
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Mux1H(
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(for { i <- 0 until 8 } yield {
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(arbLock === (1.U << i)) -> flitReg(i+4)
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})
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)
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syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
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testIO := Cat( syncSerDat, Cat(flitReg), io.serDat )
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}
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trait CDRInAxis{ this: CDRInBase =>
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def HeaderByte: Int = 4
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val ETH_PRE = "b1100010001".U(10.W)
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val ETH_SFD = "b0110100111".U(10.W)
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = RegInit(0.U((12+1).W))
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val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
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val shiftData = Dualb4b5Decoder(checkSFD(9,0))
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val payloadLen = RegInit(0.U(12.W))
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when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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payloadLen := Cat( shiftData, 0.U(4.W) )
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} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
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}
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stateNext :=
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Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
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(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
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(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
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)) //crc
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
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bitCnt := 0.U
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} .otherwise{
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when( bitCnt === 9.U ){
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bitCnt := 0.U
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} .otherwise{
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bitCnt := bitCnt + 1.U
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}
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}
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
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byteCnt := 0.U
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} .elsewhen( bitCnt === 9.U ){
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when( stateCurr === STATE_HEADER ){
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byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
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assert( byteCnt <= (HeaderByte-1).U )
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
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assert( byteCnt <= ( payloadLen+ (4-1).U ) )
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}
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}
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val axis_valid = RegInit(false.B)
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val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
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val axis_tuser = false.B
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val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )
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io.axis.valid := axis_valid
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io.axis.bits.tdata := axis_tdata
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io.axis.bits.tuser := axis_tuser
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io.axis.bits.tlast := axis_tlast
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when( io.axis.fire ){
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axis_valid := false.B
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} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
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axis_valid := true.B
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}
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}
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class CDRIn extends CDRInBase
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with CDRInAxis
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with CDRInOverSample
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class MPCDRIn extends CDRInBase
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with CDRInAxis
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with CDRInMultiSample
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