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pwm默认触发中断，暂时删除pwm例化，软件中断号用宏定义

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This commit is contained in:
Ruige Lee
2025-01-27 22:25:39 +08:00
parent 0d20af8297
commit 28e1f20abb
4 changed files with 428 additions and 29 deletions
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36
tb/sw/src/MstMain.c
View File

@@ -10,6 +10,12 @@ volatile uint32_t *plic_priority_4 = (uint32_t*)( 0xc000000U + 0X000004 * 4);
volatile uint32_t *plic_priority_5 = (uint32_t*)( 0xc000000U + 0X000004 * 5);
volatile uint32_t *plic_priority_6 = (uint32_t*)( 0xc000000U + 0X000004 * 6);
volatile uint32_t *plic_priority_TxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_TXEND);
volatile uint32_t *plic_priority_RxError = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXERROR);
volatile uint32_t *plic_priority_RxStart = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXSTART);
volatile uint32_t *plic_priority_RxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXEND);
volatile uint32_t *plic_priority_18 = (uint32_t*)( 0xc000000U + 0X000004 * 18);
volatile uint32_t *plic_priority_19 = (uint32_t*)( 0xc000000U + 0X000004 * 19);
volatile uint32_t *plic_priority_20 = (uint32_t*)( 0xc000000U + 0X000004 * 20);
@@ -35,13 +41,13 @@ void plic_handle(){
uint32_t claim = *plic_claim;
if( claim == 18 ){
if( claim == CDR_INT_TXEND ){
flag_intTxEnd = 1;
} else if( claim == 19 ){
} else if( claim == CDR_INT_RXERROR ){
flag_intRxError = 1;
} else if( claim == 20 ){
} else if( claim == CDR_INT_RXSTART ){
flag_intRxStart = 1;
} else if( claim == 21 ){
} else if( claim == CDR_INT_RXEND ){
flag_intRxEnd = 1;
}
@@ -82,20 +88,20 @@ void main()
uint32_t led = 0;
*plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21;
*plic_priority_18 = 1;
*plic_priority_19 = 1;
*plic_priority_20 = 1;
*plic_priority_21 = 1;
*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
*plic_priority_TxEnd = 1;
*plic_priority_RxError = 1;
*plic_priority_RxStart = 1;
*plic_priority_RxEnd = 1;
*plic_threshold_0 = 0;
{//再写一次实现延迟，等从机的复位完成
*plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21;
*plic_priority_18 = 1;
*plic_priority_19 = 1;
*plic_priority_20 = 1;
*plic_priority_21 = 1;
*plic_threshold_0 = 0;
*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
*plic_priority_TxEnd = 1;
*plic_priority_RxError = 1;
*plic_priority_RxStart = 1;
*plic_priority_RxEnd = 1;
*plic_threshold_0 = 0;
}

26
tb/sw/src/SlvMain.c
View File

@@ -5,11 +5,19 @@
// #include "timer.h"
#include "tl2cdr.h"
volatile uint32_t *plic_priority_3 = (uint32_t*)( 0xc000000U + 0X000004 * 3);
volatile uint32_t *plic_priority_4 = (uint32_t*)( 0xc000000U + 0X000004 * 4);
volatile uint32_t *plic_priority_5 = (uint32_t*)( 0xc000000U + 0X000004 * 5);
volatile uint32_t *plic_priority_6 = (uint32_t*)( 0xc000000U + 0X000004 * 6);
volatile uint32_t *plic_priority_TxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_TXEND);
volatile uint32_t *plic_priority_RxError = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXERROR);
volatile uint32_t *plic_priority_RxStart = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXSTART);
volatile uint32_t *plic_priority_RxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXEND);
volatile uint32_t *plic_priority_18 = (uint32_t*)( 0xc000000U + 0X000004 * 18);
volatile uint32_t *plic_priority_19 = (uint32_t*)( 0xc000000U + 0X000004 * 19);
volatile uint32_t *plic_priority_20 = (uint32_t*)( 0xc000000U + 0X000004 * 20);
@@ -35,13 +43,13 @@ void plic_handle(){
uint32_t claim = *plic_claim;
if( claim == 18 ){
if( claim == CDR_INT_TXEND ){
flag_intTxEnd = 1;
} else if( claim == 19 ){
} else if( claim == CDR_INT_RXERROR ){
flag_intRxError = 1;
} else if( claim == 20 ){
} else if( claim == CDR_INT_RXSTART ){
flag_intRxStart = 1;
} else if( claim == 21 ){
} else if( claim == CDR_INT_RXEND ){
flag_intRxEnd = 1;
}
@@ -79,11 +87,11 @@ void main()
register uint32_t isLast;
register uint32_t flag;
*plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21;
*plic_priority_18 = 1;
*plic_priority_19 = 1;
*plic_priority_20 = 1;
*plic_priority_21 = 1;
*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
*plic_priority_TxEnd = 1;
*plic_priority_RxError = 1;
*plic_priority_RxStart = 1;
*plic_priority_RxEnd = 1;
*plic_threshold_0 = 0;

6
tb/sw/tl2cdr/tl2cdr.h
View File

@@ -26,6 +26,12 @@
#define CDR_ReadTxCrc 0x24
#define CDR_ReadRxCrc 0x28
#define CDR_INT_TXEND 14
#define CDR_INT_RXERROR 15
#define CDR_INT_RXSTART 16
#define CDR_INT_RXEND 17
extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
extern volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write