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RuigeLee
2025-09-11 14:30:08 +08:00
parent 61d4f6fcf8
commit 26367fd63c
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243
tb/ShinBack_tb.v
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`timescale 1 ns / 1 ps
module ShinBack_tb();
reg clock = 0;
reg overClk = 0;
reg reset = 1;
reg [15:0] io_FSMC_ADIn;
wire [15:0] io_FSMC_ADOut;
wire io_FSMC_ADOEn;
reg io_FSMC_csn = 1;
reg io_FSMC_rdn = 1;
reg io_FSMC_wrn = 1;
reg io_FSMC_advn;
reg io_testIO = 0;
wire [3:0] downStreamDat;
wire [3:0] upStreamDat;
ShinMst s_shinMst(
.clock(clock),
.reset(reset),
.io_FSMC_ADIn(io_FSMC_ADIn),
.io_FSMC_ADOut(io_FSMC_ADOut),
.io_FSMC_ADOEn(io_FSMC_ADOEn),
.io_FSMC_csn(io_FSMC_csn),
.io_FSMC_rdn(io_FSMC_rdn),
.io_FSMC_wrn(io_FSMC_wrn),
.io_FSMC_advn(io_FSMC_advn),
.io_interrupt(),
.io_testIO(io_testIO),
.io_serOut(downStreamDat[0]),
.io_serIn(upStreamDat[0]),
.io_overCLK(overClk)
);
ShinSlvBase s_ShinSlv0(
.clock(clock),
.reset(reset),
.io_isOnline(),
.io_isLast(1'b0),
.io_DCIn(1'b0),
.io_downSer_out(downStreamDat[1]),
.io_downSer_in(downStreamDat[0]),
.io_upSer_out(upStreamDat[0]),
.io_upSer_in(upStreamDat[1]),
.io_overCLK(overClk),
.led()
);
ShinSlvBase s_ShinSlv1(
.clock(clock),
.reset(reset),
.io_isOnline(),
.io_isLast(1'b0),
.io_DCIn(1'b0),
.io_downSer_out(downStreamDat[2]),
.io_downSer_in(downStreamDat[1]),
.io_upSer_out(upStreamDat[1]),
.io_upSer_in(upStreamDat[2]),
.io_overCLK(overClk),
.led()
);
ShinSlvBase s_ShinSlv2(
.clock(clock),
.reset(reset),
.io_isOnline(),
.io_isLast(1'b0),
.io_DCIn(1'b0),
.io_downSer_out(downStreamDat[3]),
.io_downSer_in(downStreamDat[2]),
.io_upSer_out(upStreamDat[2]),
.io_upSer_in(upStreamDat[3]),
.io_overCLK(overClk),
.led()
);
ShinSlvBase s_ShinSlv3(
.clock(clock),
.reset(reset),
.io_isOnline(),
.io_isLast(1'b1),
.io_DCIn(1'b0),
.io_downSer_out(),
.io_downSer_in(downStreamDat[3]),
.io_upSer_out(upStreamDat[3]),
.io_upSer_in(1'b0),
.io_overCLK(overClk),
.led()
);
initial begin
forever #80 clock = ~clock;
end
initial begin
#10
forever #20 overClk = ~overClk;
end
initial begin
# 100 reset = 1;
# 100 reset = 0;
end
initial begin
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 1;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 1;
io_testIO = 0;
#5005
// @0 <- 512 length | operator
#500
io_FSMC_ADIn = 16'd0 | (1 << 11);
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 0;
#500
io_FSMC_ADIn = (16'd512 << 4) | 16'd0;
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 0;
io_FSMC_advn = 1;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 1;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 1;
// @1 <- 0 param0
#500
io_FSMC_ADIn = 16'd1 | (1 << 11);
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 0;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 0;
io_FSMC_advn = 1;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 1;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 1;
// @2 <- 0 param1
#500
io_FSMC_ADIn = 16'd2 | (1 << 11);
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 0;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 0;
io_FSMC_advn = 1;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 1;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 1;
// @3 <- 0 param2
#500
io_FSMC_ADIn = 16'd3 | (1 << 11);
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 0;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 0;
io_FSMC_rdn = 1;
io_FSMC_wrn = 0;
io_FSMC_advn = 1;
#500
io_FSMC_ADIn = 16'd0;
io_FSMC_csn = 1;
io_FSMC_rdn = 1;
io_FSMC_wrn = 1;
io_FSMC_advn = 1;
#800
io_testIO = 1;
#160
io_testIO = 0;
end
initial begin
# 10000000
$finish;
end
initial begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinBack_tb);//tb模块名称
end
endmodule

191
tb/backSys_tb.v
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@@ -1,191 +0,0 @@
`timescale 1 ns / 1 ps
module backSys_TB (
);
reg clock;
reg reset;
reg overCLK;
wire [3:0] io_uDat;
wire [3:0] io_dDat;
wire [3:0] isLast;
BackSys s_Mst(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[0]),
.io_uDatOut(),
.io_dDatIn(1'b0),
.io_dDatOut(io_dDat[0]),
.io_out(),
.io_in(32'b0),
.io_isOnline(),
.io_isLast(isLast[0]),
.io_DCIn(1'b0)
);
BackSys s_Slv0(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[1]),
.io_uDatOut(io_uDat[0]),
.io_dDatIn(io_dDat[0]),
.io_dDatOut(io_dDat[1]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[0]),
.io_isLast(isLast[1]),
.io_DCIn(1'b0)
);
BackSys s_Slv1(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[2]),
.io_uDatOut(io_uDat[1]),
.io_dDatIn(io_dDat[1]),
.io_dDatOut(io_dDat[2]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[1]),
.io_isLast(isLast[2]),
.io_DCIn(1'b0)
);
BackSys s_Slv2(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[3]),
.io_uDatOut(io_uDat[2]),
.io_dDatIn(io_dDat[2]),
.io_dDatOut(io_dDat[3]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[2]),
.io_isLast(isLast[3]),
.io_DCIn(1'b0)
);
BackSys s_Slv3(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(1'b0),
.io_uDatOut(io_uDat[3]),
.io_dDatIn(io_dDat[3]),
.io_dDatOut(),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[3]),
.io_isLast(1'b1),
.io_DCIn(1'b0)
);
initial begin
clock = 0;
reset = 1;
overCLK = 0;
#200
reset <= 0;
# 5000000
$display("Time Out !!!");
$stop;
end
initial begin
forever begin #40 clock <= ~clock; end
end
initial begin
forever begin #10 overCLK <= ~overCLK; end
end
`define SRAM s_Mst.sram.mem.mem_ext.ram
localparam DP = 2**14;
integer i;
reg [7:0] mem [0:200000];
initial begin
$readmemh("./tb/sw/build/mstTest.verilog", mem);
for ( i = 0; i < DP; i = i + 1 ) begin
`SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
end
end
`define SLV0_SRAM s_Slv0.sram.mem.mem_ext.ram
`define SLV1_SRAM s_Slv1.sram.mem.mem_ext.ram
`define SLV2_SRAM s_Slv2.sram.mem.mem_ext.ram
`define SLV3_SRAM s_Slv3.sram.mem.mem_ext.ram
localparam DPS = 2**14;
reg [7:0] mem1 [0:200000];
initial begin
$readmemh("./tb/sw/build/slvTest.verilog", mem);
for ( i = 0; i < DP; i = i + 1 ) begin
`SLV0_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV0_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV0_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV0_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV1_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV1_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV1_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV1_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV2_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV2_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV2_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV2_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV3_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV3_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV3_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV3_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
end
end
initial
begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, backSys_TB);//tb模块名称
end
endmodule

148
tb/cdrInOut_tb.v
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@@ -1,148 +0,0 @@
`timescale 1 ns / 1 ps
module CDRInOut_tb();
reg clock = 0;
reg reset = 1;
reg overCLK = 0;
wire serDat;
wire tx_axis_ready;
reg tx_axis_valid = 0;
reg [7:0] tx_axis_bits_tdata;
reg tx_axis_bits_tlast;
reg tx_axis_bits_tuser;
reg rx_axis_ready = 1;
wire rx_axis_valid;
wire [7:0] rx_axis_bits_tdata;
wire rx_axis_bits_tlast;
wire rx_axis_bits_tuser;
CDRIn s_CDRIn(
.clock(clock),
.reset(reset),
.io_axis_ready(rx_axis_ready),
.io_axis_valid(rx_axis_valid),
.io_axis_bits_tdata(rx_axis_bits_tdata),
.io_axis_bits_tlast(rx_axis_bits_tlast),
.io_axis_bits_tuser(rx_axis_bits_tuser),
.io_serDat(serDat),
.io_overCLK(overCLK)
);
CDROut s_CDROut(
.clock(clock),
.reset(reset),
.io_axis_ready(tx_axis_ready),
.io_axis_valid(tx_axis_valid),
.io_axis_bits_tdata(tx_axis_bits_tdata),
.io_axis_bits_tlast(tx_axis_bits_tlast),
.io_axis_bits_tuser(tx_axis_bits_tuser),
.io_serDat(serDat)
);
initial begin
forever #80 clock = ~clock;
end
initial begin
#10
forever #20 overCLK = ~overCLK;
end
initial begin
# 100 reset = 1;
# 100 reset = 0;
end
// reg [7:0] cnt = 0;
reg [31:0] rtc_cnt=0;
always @(posedge clock) begin
if( rtc_cnt > 200 ) begin
rtc_cnt <= #2 0;
end else begin
rtc_cnt <= #2 rtc_cnt + 1;
end
end
reg [7:0] cnt;
always @(posedge clock) begin
if( rtc_cnt == 0 ) begin
cnt <= #2 0;
end else begin
if( cnt == 8'd0 ) begin
tx_axis_valid <= #2 1'b1;
tx_axis_bits_tdata <= #2 0;
tx_axis_bits_tlast <= #2 1'b0;
tx_axis_bits_tuser <= #2 1'b0;
cnt <= #2 cnt + 8'd1;
end else begin
if( tx_axis_valid & tx_axis_ready ) begin
if ( tx_axis_bits_tlast ) begin
tx_axis_valid <= #2 1'b0;
tx_axis_bits_tlast <= #2 1'b0;
end else begin
tx_axis_bits_tdata <= #2 cnt;
tx_axis_bits_tuser <= #2 1'b0;
if( cnt == 8'd1 ) begin
tx_axis_bits_tdata <= #2 8'h1;
end
if( cnt == 8'd4 ) begin
tx_axis_bits_tlast <= #2 8'h1;
end else begin
cnt <= #2 cnt + 8'd1;
end
end
end
end
end
end
initial begin
# 100000
$finish;
end
initial begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, CDRInOut_tb);//tb模块名称
end
endmodule

113
tb/cdrOut_tb.v
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`timescale 1 ns / 1 ps
module CDROut_tb();
reg clock = 0;
reg reset = 1;
wire serDat;
wire axis_ready;
reg axis_valid = 0;
reg [7:0] axis_bits_tdata;
reg axis_bits_tlast;
reg axis_bits_tuser;
CDROut s_CDROut(
.clock(clock),
.reset(reset),
.io_axis_ready(axis_ready),
.io_axis_valid(axis_valid),
.io_axis_bits_tdata(axis_bits_tdata),
.io_axis_bits_tlast(axis_bits_tlast),
.io_axis_bits_tuser(axis_bits_tuser),
.io_serDat(serDat)
);
initial begin
forever #20 clock = ~clock;
end
initial begin
# 100 reset = 1;
# 100 reset = 0;
end
reg [7:0] cnt = 0;
// always @(posedge clock) begin
// if( cnt == 8'd0 ) begin
// #2 axis_valid <= 1'b1;
// #2 axis_bits_tdata <= cnt;
// #2 axis_bits_tlast <= 1'b0;
// #2 axis_bits_tuser <= 1'b0;
// #2 cnt <= cnt + 8'd1;
// end else begin
// if( axis_valid & axis_ready ) begin
// axis_valid <= 1'b0;
// end else if( ~axis_valid ) begin
// #2 axis_valid <= 1'b1;
// if ( cnt == 8'd255 ) begin
// #2 axis_bits_tlast <= 1'b1;
// end else begin
// #2 axis_bits_tlast <= 1'b0;
// #2 cnt <= cnt + 8'd1;
// end
// end
// end
// end
always @(posedge clock) begin
if( cnt == 8'd0 ) begin
#2 axis_valid <= 1'b1;
#2 axis_bits_tdata <= cnt;
#2 axis_bits_tlast <= 1'b0;
#2 axis_bits_tuser <= 1'b0;
#2 cnt <= cnt + 8'd1;
end else begin
if( axis_valid & axis_ready ) begin
if ( axis_bits_tlast ) begin
#2 axis_valid <= 1'b0;
#2 axis_bits_tlast <= 1'b0;
end else begin
#2 axis_bits_tdata <= cnt;
#2 axis_bits_tuser <= 1'b0;
if( cnt == 8'd31 ) begin
#2 axis_bits_tlast <= 1'b1;
end else begin
#2 cnt <= cnt + 8'd1;
end
end
end
end
end
initial begin
# 100000
$finish;
end
initial begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, CDROut_tb);//tb模块名称
end
endmodule

244
tb/sim_backChain.cpp
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@@ -1,244 +0,0 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <verilated.h>
#include "VBackPlaneChainTest.h"
#include <memory>
#include <iostream>
#include <getopt.h>
#include <sstream>
#if VM_TRACE
#include "verilated_fst_c.h"
#endif
char* img;
VBackPlaneChainTest *top;
#if VM_TRACE
VerilatedFstC* tfp;
#endif
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;
}
static void sim_exit(){
#if VM_TRACE
tfp->close();
#endif
top->final();
delete top;
}
int main(int argc, char **argv, char **env) {
top = new VBackPlaneChainTest();
#if VM_TRACE
tfp = new VerilatedFstC;
Verilated::traceEverOn(true);
top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("./tb/build/wave.fst");
#endif
top->reset = 1;
top->clock = 0;
top->io_clk400_0 = 0;
top->io_clk400_1 = 0;
top->io_clk400_2 = 0;
top->io_clk400_3 = 0;
top->io_clk400_4 = 0;
top->io_clk400_5 = 0;
while(!Verilated::gotFinish()) {
Verilated::timeInc(1);
if ( main_time != 1000 ){
} else {
top->reset = 0;
}
if ( main_time % 400 == 100 ) {
top->clock = 1;
} else if ( main_time % 400 == 300 ) {
top->clock = 0;
}
if ( main_time % 100 == 10 ) {
top->io_clk400_0 = 1;
} else if ( main_time % 100 == 60 ) {
top->io_clk400_0 = 0;
}
if ( main_time % 100 == 20 ) {
top->io_clk400_1 = 1;
} else if ( main_time % 100 == 70 ) {
top->io_clk400_1 = 0;
}
if ( main_time % 100 == 40 ) {
top->io_clk400_2 = 1;
} else if ( main_time % 100 == 90 ) {
top->io_clk400_2 = 0;
}
if ( main_time % 100 == 5 ) {
top->io_clk400_3 = 1;
} else if ( main_time % 100 == 55 ) {
top->io_clk400_3 = 0;
}
if ( main_time % 100 == 0 ) {
top->io_clk400_4 = 1;
} else if ( main_time % 100 == 50 ) {
top->io_clk400_4 = 0;
}
if ( main_time % 100 == 30 ) {
top->io_clk400_5 = 1;
} else if ( main_time % 100 == 80 ) {
top->io_clk400_5 = 0;
}
if( main_time == 50000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x00 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0xa5;
top->io_spi_bits_op = 0x01;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 50100 ){
top->io_spi_valid = 0;
}
if( main_time == 250000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x01 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 250100 ){
top->io_spi_valid = 0;
}
if( main_time == 450000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x02 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 450100 ){
top->io_spi_valid = 0;
}
if( main_time == 650000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x03 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 650100 ){
top->io_spi_valid = 0;
}
if( main_time == 850000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x04 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 850100 ){
top->io_spi_valid = 0;
}
if( main_time == 1050000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x05 << 1 | 0x01;
top->io_spi_bits_register = 0x1;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 1050100 ){
top->io_spi_valid = 0;
}
top->eval();
#if VM_TRACE
tfp->dump(Verilated::time());
#endif
main_time ++;
if( main_time > 3050000 ){
break;
}
}
sim_exit();
return -1;
}

175
tb/sim_backMst.cpp
View File

@@ -1,175 +0,0 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <verilated.h>
#include "VBackPlaneMstTest.h"
#include <memory>
#include <iostream>
#include <getopt.h>
#include <sstream>
#if VM_TRACE
#include "verilated_fst_c.h"
#endif
char* img;
VBackPlaneMstTest *top;
#if VM_TRACE
VerilatedFstC* tfp;
#endif
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;
}
static void sim_exit(){
#if VM_TRACE
tfp->close();
#endif
top->final();
delete top;
}
int main(int argc, char **argv, char **env) {
top = new VBackPlaneMstTest();
#if VM_TRACE
tfp = new VerilatedFstC;
Verilated::traceEverOn(true);
top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("./tb/build/wave.fst");
#endif
top->io_reset = 1;
// top->io_SCK = 0;
top->io_clk4 = 0;
while(!Verilated::gotFinish()) {
Verilated::timeInc(1);
if ( main_time != 1000 ){
} else {
top->io_reset = 0;
}
// if ( main_time % 400 == 100 ) {
// top->io_SCK = 1;
// } else if ( main_time % 400 == 300 ) {
// top->io_SCK = 0;
// }
if ( main_time % 100 == 10 ) {
top->io_clk4 = 1;
} else if ( main_time % 100 == 60 ) {
top->io_clk4 = 0;
}
if( main_time == 50000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x11 << 1 | 0x00;
top->io_spi_bits_register = 0x0;
top->io_spi_bits_data = 0xaa;
top->io_spi_bits_op = 0x01;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 50100 ){
top->io_spi_valid = 0;
}
if( main_time == 150000 ){
top->io_req_valid = 1;
top->io_req_bits_address = 0x11 << 1 | 0x00;
top->io_req_bits_register = 0x0;
top->io_req_bits_data = 0xaa;
} else if( main_time == 150400 ){
top->io_req_valid = 0;
}
if( main_time == 250000 ){
top->io_spi_valid = 1;
top->io_spi_bits_address = 0x11 << 1 | 0x01;
top->io_spi_bits_register = 0x0;
top->io_spi_bits_data = 0x55;
top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0;
} else if( main_time == 250100 ){
top->io_spi_valid = 0;
}
top->eval();
#if VM_TRACE
tfp->dump(Verilated::time());
#endif
main_time ++;
if( main_time > 450000 ){
break;
}
}
sim_exit();
return -1;
}

147
tb/sim_backSlv.cpp
View File

@@ -1,147 +0,0 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <verilated.h>
#include "VBackBoardSlvTest.h"
#include <memory>
#include <iostream>
#include <getopt.h>
#include <sstream>
#if VM_TRACE
#include "verilated_fst_c.h"
#endif
char* img;
VBackBoardSlvTest *top;
#if VM_TRACE
VerilatedFstC* tfp;
#endif
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;
}
static void sim_exit(){
#if VM_TRACE
tfp->close();
#endif
top->final();
delete top;
}
int main(int argc, char **argv, char **env) {
top = new VBackBoardSlvTest();
#if VM_TRACE
tfp = new VerilatedFstC;
Verilated::traceEverOn(true);
top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("./tb/build/wave.fst");
#endif
top->reset = 1;
top->clock = 0;
top->io_clk4 = 0;
while(!Verilated::gotFinish()) {
Verilated::timeInc(1);
if ( main_time != 1000 ){
} else {
top->reset = 0;
}
if ( main_time % 400 == 100 ) {
top->clock = 1;
} else if ( main_time % 400 == 300 ) {
top->clock = 0;
}
if ( main_time % 100 == 10 ) {
top->io_clk4 = 1;
} else if ( main_time % 100 == 60 ) {
top->io_clk4 = 0;
}
if( main_time == 50000 ){
top->io_req_valid = 1;
top->io_req_bits_address = 0x11 << 1 | 0x00;
top->io_req_bits_register = 0x0;
top->io_req_bits_data = 0xaa;
} else if( main_time == 50400 ){
top->io_req_valid = 0;
}
if( main_time == 150000 ){
top->io_rsp_valid = 1;
top->io_rsp_bits_address = 0x11 << 1 | 0x00;
top->io_rsp_bits_register = 0x0;
top->io_rsp_bits_data = 0xaa;
} else if( main_time == 150400 ){
top->io_rsp_valid = 0;
}
top->eval();
#if VM_TRACE
tfp->dump(Verilated::time());
#endif
main_time ++;
if( main_time > 250000 ){
break;
}
}
sim_exit();
return -1;
}

946
tb/verilator/SimTop.v
View File

@@ -1,946 +0,0 @@
module SimTop (
// output success,
// output fail,
input clock, //100MHz
input reset,
input clk800,
output [7:0] gpio_o,
input [7:0] gpio_i
);
wire [3:0] uDatSer;
wire [3:0] dDatSer;
wire [3:0] dmactive;
ExampleRocketSystem s_rocket_mst(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[0]),
.debug_dmactiveAck(dmactive[0]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.gpio_0_pins_0_i_ival(gpio_i[0]), //输入
.gpio_0_pins_0_i_po(1'b0), //
.gpio_0_pins_0_o_oval(gpio_o[0]), //输出
.gpio_0_pins_0_o_oe(), //输出使能
.gpio_0_pins_0_o_ie(), //输入使能
.gpio_0_pins_0_o_pue(), //上拉使能
.gpio_0_pins_0_o_ds(), //驱动强度
.gpio_0_pins_0_o_ps(), //驱动速率？
.gpio_0_pins_0_o_ds1(), //驱动强度？
.gpio_0_pins_0_o_poe(), //Nandtree enable
.gpio_0_pins_1_i_ival(gpio_i[1]),
.gpio_0_pins_1_i_po(1'b0),
.gpio_0_pins_1_o_oval(gpio_o[1]),
.gpio_0_pins_1_o_oe(),
.gpio_0_pins_1_o_ie(),
.gpio_0_pins_1_o_pue(),
.gpio_0_pins_1_o_ds(),
.gpio_0_pins_1_o_ps(),
.gpio_0_pins_1_o_ds1(),
.gpio_0_pins_1_o_poe(),
.gpio_0_pins_2_i_ival(gpio_i[2]),
.gpio_0_pins_2_i_po(1'b0),
.gpio_0_pins_2_o_oval(gpio_o[2]),
.gpio_0_pins_2_o_oe(),
.gpio_0_pins_2_o_ie(),
.gpio_0_pins_2_o_pue(),
.gpio_0_pins_2_o_ds(),
.gpio_0_pins_2_o_ps(),
.gpio_0_pins_2_o_ds1(),
.gpio_0_pins_2_o_poe(),
.gpio_0_pins_3_i_ival(gpio_i[3]),
.gpio_0_pins_3_i_po(1'b0),
.gpio_0_pins_3_o_oval(gpio_o[3]),
.gpio_0_pins_3_o_oe(),
.gpio_0_pins_3_o_ie(),
.gpio_0_pins_3_o_pue(),
.gpio_0_pins_3_o_ds(),
.gpio_0_pins_3_o_ps(),
.gpio_0_pins_3_o_ds1(),
.gpio_0_pins_3_o_poe(),
.gpio_0_pins_4_i_ival(gpio_i[4]),
.gpio_0_pins_4_i_po(1'b0),
.gpio_0_pins_4_o_oval(gpio_o[4]),
.gpio_0_pins_4_o_oe(),
.gpio_0_pins_4_o_ie(),
.gpio_0_pins_4_o_pue(),
.gpio_0_pins_4_o_ds(),
.gpio_0_pins_4_o_ps(),
.gpio_0_pins_4_o_ds1(),
.gpio_0_pins_4_o_poe(),
.gpio_0_pins_5_i_ival(gpio_i[5]),
.gpio_0_pins_5_i_po(1'b0),
.gpio_0_pins_5_o_oval(gpio_o[5]),
.gpio_0_pins_5_o_oe(),
.gpio_0_pins_5_o_ie(),
.gpio_0_pins_5_o_pue(),
.gpio_0_pins_5_o_ds(),
.gpio_0_pins_5_o_ps(),
.gpio_0_pins_5_o_ds1(),
.gpio_0_pins_5_o_poe(),
.gpio_0_pins_6_i_ival(gpio_i[6]),
.gpio_0_pins_6_i_po(1'b0),
.gpio_0_pins_6_o_oval(gpio_o[6]),
.gpio_0_pins_6_o_oe(),
.gpio_0_pins_6_o_ie(),
.gpio_0_pins_6_o_pue(),
.gpio_0_pins_6_o_ds(),
.gpio_0_pins_6_o_ps(),
.gpio_0_pins_6_o_ds1(),
.gpio_0_pins_6_o_poe(),
.gpio_0_pins_7_i_ival(gpio_i[7]),
.gpio_0_pins_7_i_po(1'b0),
.gpio_0_pins_7_o_oval(gpio_o[7]),
.gpio_0_pins_7_o_oe(),
.gpio_0_pins_7_o_ie(),
.gpio_0_pins_7_o_pue(),
.gpio_0_pins_7_o_ds(),
.gpio_0_pins_7_o_ps(),
.gpio_0_pins_7_o_ds1(),
.gpio_0_pins_7_o_poe(),
.uart_0_txd(),
.uart_0_rxd(1'b0),
// .pwm_0_gpio_0(),
// .pwm_0_gpio_1(),
// .pwm_0_gpio_2(),
// .pwm_0_gpio_3(),
.spi_0_sck(),
.spi_0_dq_0_i(1'b0),
.spi_0_dq_0_o(),
.spi_0_dq_0_ie(),
.spi_0_dq_0_oe(),
.spi_0_dq_1_i(1'b0),
.spi_0_dq_1_o(),
.spi_0_dq_1_ie(),
.spi_0_dq_1_oe(),
.spi_0_dq_2_i(1'b0),
.spi_0_dq_2_o(),
.spi_0_dq_2_ie(),
.spi_0_dq_2_oe(),
.spi_0_dq_3_i(1'b0),
.spi_0_dq_3_o(),
.spi_0_dq_3_ie(),
.spi_0_dq_3_oe(),
.spi_0_cs_0(),
.spi_0_cs_1(),
.spi_0_cs_2(),
.spi_0_cs_3(),
.i2c_0_scl_in(1'b0),
.i2c_0_scl_out(),
.i2c_0_scl_oe(),
.i2c_0_sda_in(1'b0),
.i2c_0_sda_out(),
.i2c_0_sda_oe(),
.interrupts(2'b0),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(1'b0),
.cdrInIO_uDatIn(uDatSer[0]),
.cdrInIO_isLast(1'b0),
.cdrOutIO_dDatOut(dDatSer[0]),
.cdrOutIO_uDatOut(),
.cdrOutIO_isOnline(),
.fsmcio_ADIn(16'b0),
.fsmcio_ADOut(),
.fsmcio_ADOEn(),
.fsmcio_csn(1'b1),
.fsmcio_rdn(1'b1),
.fsmcio_wrn(1'b1),
.fsmcio_advn(1'b1)
);
ExampleRocketSystem s_rocket_slv0(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[1]),
.debug_dmactiveAck(dmactive[1]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.gpio_0_pins_0_i_ival(gpio_i[0]), //输入
.gpio_0_pins_0_i_po(1'b0), //
.gpio_0_pins_0_o_oval(gpio_o[0]), //输出
.gpio_0_pins_0_o_oe(), //输出使能
.gpio_0_pins_0_o_ie(), //输入使能
.gpio_0_pins_0_o_pue(), //上拉使能
.gpio_0_pins_0_o_ds(), //驱动强度
.gpio_0_pins_0_o_ps(), //驱动速率？
.gpio_0_pins_0_o_ds1(), //驱动强度？
.gpio_0_pins_0_o_poe(), //Nandtree enable
.gpio_0_pins_1_i_ival(gpio_i[1]),
.gpio_0_pins_1_i_po(1'b0),
.gpio_0_pins_1_o_oval(gpio_o[1]),
.gpio_0_pins_1_o_oe(),
.gpio_0_pins_1_o_ie(),
.gpio_0_pins_1_o_pue(),
.gpio_0_pins_1_o_ds(),
.gpio_0_pins_1_o_ps(),
.gpio_0_pins_1_o_ds1(),
.gpio_0_pins_1_o_poe(),
.gpio_0_pins_2_i_ival(gpio_i[2]),
.gpio_0_pins_2_i_po(1'b0),
.gpio_0_pins_2_o_oval(gpio_o[2]),
.gpio_0_pins_2_o_oe(),
.gpio_0_pins_2_o_ie(),
.gpio_0_pins_2_o_pue(),
.gpio_0_pins_2_o_ds(),
.gpio_0_pins_2_o_ps(),
.gpio_0_pins_2_o_ds1(),
.gpio_0_pins_2_o_poe(),
.gpio_0_pins_3_i_ival(gpio_i[3]),
.gpio_0_pins_3_i_po(1'b0),
.gpio_0_pins_3_o_oval(gpio_o[3]),
.gpio_0_pins_3_o_oe(),
.gpio_0_pins_3_o_ie(),
.gpio_0_pins_3_o_pue(),
.gpio_0_pins_3_o_ds(),
.gpio_0_pins_3_o_ps(),
.gpio_0_pins_3_o_ds1(),
.gpio_0_pins_3_o_poe(),
.gpio_0_pins_4_i_ival(gpio_i[4]),
.gpio_0_pins_4_i_po(1'b0),
.gpio_0_pins_4_o_oval(gpio_o[4]),
.gpio_0_pins_4_o_oe(),
.gpio_0_pins_4_o_ie(),
.gpio_0_pins_4_o_pue(),
.gpio_0_pins_4_o_ds(),
.gpio_0_pins_4_o_ps(),
.gpio_0_pins_4_o_ds1(),
.gpio_0_pins_4_o_poe(),
.gpio_0_pins_5_i_ival(gpio_i[5]),
.gpio_0_pins_5_i_po(1'b0),
.gpio_0_pins_5_o_oval(gpio_o[5]),
.gpio_0_pins_5_o_oe(),
.gpio_0_pins_5_o_ie(),
.gpio_0_pins_5_o_pue(),
.gpio_0_pins_5_o_ds(),
.gpio_0_pins_5_o_ps(),
.gpio_0_pins_5_o_ds1(),
.gpio_0_pins_5_o_poe(),
.gpio_0_pins_6_i_ival(gpio_i[6]),
.gpio_0_pins_6_i_po(1'b0),
.gpio_0_pins_6_o_oval(gpio_o[6]),
.gpio_0_pins_6_o_oe(),
.gpio_0_pins_6_o_ie(),
.gpio_0_pins_6_o_pue(),
.gpio_0_pins_6_o_ds(),
.gpio_0_pins_6_o_ps(),
.gpio_0_pins_6_o_ds1(),
.gpio_0_pins_6_o_poe(),
.gpio_0_pins_7_i_ival(gpio_i[7]),
.gpio_0_pins_7_i_po(1'b0),
.gpio_0_pins_7_o_oval(gpio_o[7]),
.gpio_0_pins_7_o_oe(),
.gpio_0_pins_7_o_ie(),
.gpio_0_pins_7_o_pue(),
.gpio_0_pins_7_o_ds(),
.gpio_0_pins_7_o_ps(),
.gpio_0_pins_7_o_ds1(),
.gpio_0_pins_7_o_poe(),
.uart_0_txd(),
.uart_0_rxd(1'b0),
// .pwm_0_gpio_0(),
// .pwm_0_gpio_1(),
// .pwm_0_gpio_2(),
// .pwm_0_gpio_3(),
.spi_0_sck(),
.spi_0_dq_0_i(1'b0),
.spi_0_dq_0_o(),
.spi_0_dq_0_ie(),
.spi_0_dq_0_oe(),
.spi_0_dq_1_i(1'b0),
.spi_0_dq_1_o(),
.spi_0_dq_1_ie(),
.spi_0_dq_1_oe(),
.spi_0_dq_2_i(1'b0),
.spi_0_dq_2_o(),
.spi_0_dq_2_ie(),
.spi_0_dq_2_oe(),
.spi_0_dq_3_i(1'b0),
.spi_0_dq_3_o(),
.spi_0_dq_3_ie(),
.spi_0_dq_3_oe(),
.spi_0_cs_0(),
.spi_0_cs_1(),
.spi_0_cs_2(),
.spi_0_cs_3(),
.i2c_0_scl_in(1'b0),
.i2c_0_scl_out(),
.i2c_0_scl_oe(),
.i2c_0_sda_in(1'b0),
.i2c_0_sda_out(),
.i2c_0_sda_oe(),
.interrupts(2'b0),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[0]),
.cdrInIO_uDatIn(uDatSer[1]),
.cdrInIO_isLast(1'b0),
.cdrOutIO_dDatOut(dDatSer[1]),
.cdrOutIO_uDatOut(uDatSer[0]),
.cdrOutIO_isOnline(),
.fsmcio_ADIn(16'b0),
.fsmcio_ADOut(),
.fsmcio_ADOEn(),
.fsmcio_csn(1'b1),
.fsmcio_rdn(1'b1),
.fsmcio_wrn(1'b1),
.fsmcio_advn(1'b1)
);
ExampleRocketSystem s_rocket_slv1(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[2]),
.debug_dmactiveAck(dmactive[2]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.gpio_0_pins_0_i_ival(gpio_i[0]), //输入
.gpio_0_pins_0_i_po(1'b0), //
.gpio_0_pins_0_o_oval(gpio_o[0]), //输出
.gpio_0_pins_0_o_oe(), //输出使能
.gpio_0_pins_0_o_ie(), //输入使能
.gpio_0_pins_0_o_pue(), //上拉使能
.gpio_0_pins_0_o_ds(), //驱动强度
.gpio_0_pins_0_o_ps(), //驱动速率？
.gpio_0_pins_0_o_ds1(), //驱动强度？
.gpio_0_pins_0_o_poe(), //Nandtree enable
.gpio_0_pins_1_i_ival(gpio_i[1]),
.gpio_0_pins_1_i_po(1'b0),
.gpio_0_pins_1_o_oval(gpio_o[1]),
.gpio_0_pins_1_o_oe(),
.gpio_0_pins_1_o_ie(),
.gpio_0_pins_1_o_pue(),
.gpio_0_pins_1_o_ds(),
.gpio_0_pins_1_o_ps(),
.gpio_0_pins_1_o_ds1(),
.gpio_0_pins_1_o_poe(),
.gpio_0_pins_2_i_ival(gpio_i[2]),
.gpio_0_pins_2_i_po(1'b0),
.gpio_0_pins_2_o_oval(gpio_o[2]),
.gpio_0_pins_2_o_oe(),
.gpio_0_pins_2_o_ie(),
.gpio_0_pins_2_o_pue(),
.gpio_0_pins_2_o_ds(),
.gpio_0_pins_2_o_ps(),
.gpio_0_pins_2_o_ds1(),
.gpio_0_pins_2_o_poe(),
.gpio_0_pins_3_i_ival(gpio_i[3]),
.gpio_0_pins_3_i_po(1'b0),
.gpio_0_pins_3_o_oval(gpio_o[3]),
.gpio_0_pins_3_o_oe(),
.gpio_0_pins_3_o_ie(),
.gpio_0_pins_3_o_pue(),
.gpio_0_pins_3_o_ds(),
.gpio_0_pins_3_o_ps(),
.gpio_0_pins_3_o_ds1(),
.gpio_0_pins_3_o_poe(),
.gpio_0_pins_4_i_ival(gpio_i[4]),
.gpio_0_pins_4_i_po(1'b0),
.gpio_0_pins_4_o_oval(gpio_o[4]),
.gpio_0_pins_4_o_oe(),
.gpio_0_pins_4_o_ie(),
.gpio_0_pins_4_o_pue(),
.gpio_0_pins_4_o_ds(),
.gpio_0_pins_4_o_ps(),
.gpio_0_pins_4_o_ds1(),
.gpio_0_pins_4_o_poe(),
.gpio_0_pins_5_i_ival(gpio_i[5]),
.gpio_0_pins_5_i_po(1'b0),
.gpio_0_pins_5_o_oval(gpio_o[5]),
.gpio_0_pins_5_o_oe(),
.gpio_0_pins_5_o_ie(),
.gpio_0_pins_5_o_pue(),
.gpio_0_pins_5_o_ds(),
.gpio_0_pins_5_o_ps(),
.gpio_0_pins_5_o_ds1(),
.gpio_0_pins_5_o_poe(),
.gpio_0_pins_6_i_ival(gpio_i[6]),
.gpio_0_pins_6_i_po(1'b0),
.gpio_0_pins_6_o_oval(gpio_o[6]),
.gpio_0_pins_6_o_oe(),
.gpio_0_pins_6_o_ie(),
.gpio_0_pins_6_o_pue(),
.gpio_0_pins_6_o_ds(),
.gpio_0_pins_6_o_ps(),
.gpio_0_pins_6_o_ds1(),
.gpio_0_pins_6_o_poe(),
.gpio_0_pins_7_i_ival(gpio_i[7]),
.gpio_0_pins_7_i_po(1'b0),
.gpio_0_pins_7_o_oval(gpio_o[7]),
.gpio_0_pins_7_o_oe(),
.gpio_0_pins_7_o_ie(),
.gpio_0_pins_7_o_pue(),
.gpio_0_pins_7_o_ds(),
.gpio_0_pins_7_o_ps(),
.gpio_0_pins_7_o_ds1(),
.gpio_0_pins_7_o_poe(),
.uart_0_txd(),
.uart_0_rxd(1'b0),
// .pwm_0_gpio_0(),
// .pwm_0_gpio_1(),
// .pwm_0_gpio_2(),
// .pwm_0_gpio_3(),
.spi_0_sck(),
.spi_0_dq_0_i(1'b0),
.spi_0_dq_0_o(),
.spi_0_dq_0_ie(),
.spi_0_dq_0_oe(),
.spi_0_dq_1_i(1'b0),
.spi_0_dq_1_o(),
.spi_0_dq_1_ie(),
.spi_0_dq_1_oe(),
.spi_0_dq_2_i(1'b0),
.spi_0_dq_2_o(),
.spi_0_dq_2_ie(),
.spi_0_dq_2_oe(),
.spi_0_dq_3_i(1'b0),
.spi_0_dq_3_o(),
.spi_0_dq_3_ie(),
.spi_0_dq_3_oe(),
.spi_0_cs_0(),
.spi_0_cs_1(),
.spi_0_cs_2(),
.spi_0_cs_3(),
.i2c_0_scl_in(1'b0),
.i2c_0_scl_out(),
.i2c_0_scl_oe(),
.i2c_0_sda_in(1'b0),
.i2c_0_sda_out(),
.i2c_0_sda_oe(),
.interrupts(2'b0),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[1]),
.cdrInIO_uDatIn(uDatSer[2]),
.cdrInIO_isLast(1'b0),
.cdrOutIO_dDatOut(dDatSer[2]),
.cdrOutIO_uDatOut(uDatSer[1]),
.cdrOutIO_isOnline(),
.fsmcio_ADIn(16'b0),
.fsmcio_ADOut(),
.fsmcio_ADOEn(),
.fsmcio_csn(1'b1),
.fsmcio_rdn(1'b1),
.fsmcio_wrn(1'b1),
.fsmcio_advn(1'b1)
);
ExampleRocketSystem s_rocket_slv2(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[3]),
.debug_dmactiveAck(dmactive[3]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.gpio_0_pins_0_i_ival(gpio_i[0]), //输入
.gpio_0_pins_0_i_po(1'b0), //
.gpio_0_pins_0_o_oval(gpio_o[0]), //输出
.gpio_0_pins_0_o_oe(), //输出使能
.gpio_0_pins_0_o_ie(), //输入使能
.gpio_0_pins_0_o_pue(), //上拉使能
.gpio_0_pins_0_o_ds(), //驱动强度
.gpio_0_pins_0_o_ps(), //驱动速率？
.gpio_0_pins_0_o_ds1(), //驱动强度？
.gpio_0_pins_0_o_poe(), //Nandtree enable
.gpio_0_pins_1_i_ival(gpio_i[1]),
.gpio_0_pins_1_i_po(1'b0),
.gpio_0_pins_1_o_oval(gpio_o[1]),
.gpio_0_pins_1_o_oe(),
.gpio_0_pins_1_o_ie(),
.gpio_0_pins_1_o_pue(),
.gpio_0_pins_1_o_ds(),
.gpio_0_pins_1_o_ps(),
.gpio_0_pins_1_o_ds1(),
.gpio_0_pins_1_o_poe(),
.gpio_0_pins_2_i_ival(gpio_i[2]),
.gpio_0_pins_2_i_po(1'b0),
.gpio_0_pins_2_o_oval(gpio_o[2]),
.gpio_0_pins_2_o_oe(),
.gpio_0_pins_2_o_ie(),
.gpio_0_pins_2_o_pue(),
.gpio_0_pins_2_o_ds(),
.gpio_0_pins_2_o_ps(),
.gpio_0_pins_2_o_ds1(),
.gpio_0_pins_2_o_poe(),
.gpio_0_pins_3_i_ival(gpio_i[3]),
.gpio_0_pins_3_i_po(1'b0),
.gpio_0_pins_3_o_oval(gpio_o[3]),
.gpio_0_pins_3_o_oe(),
.gpio_0_pins_3_o_ie(),
.gpio_0_pins_3_o_pue(),
.gpio_0_pins_3_o_ds(),
.gpio_0_pins_3_o_ps(),
.gpio_0_pins_3_o_ds1(),
.gpio_0_pins_3_o_poe(),
.gpio_0_pins_4_i_ival(gpio_i[4]),
.gpio_0_pins_4_i_po(1'b0),
.gpio_0_pins_4_o_oval(gpio_o[4]),
.gpio_0_pins_4_o_oe(),
.gpio_0_pins_4_o_ie(),
.gpio_0_pins_4_o_pue(),
.gpio_0_pins_4_o_ds(),
.gpio_0_pins_4_o_ps(),
.gpio_0_pins_4_o_ds1(),
.gpio_0_pins_4_o_poe(),
.gpio_0_pins_5_i_ival(gpio_i[5]),
.gpio_0_pins_5_i_po(1'b0),
.gpio_0_pins_5_o_oval(gpio_o[5]),
.gpio_0_pins_5_o_oe(),
.gpio_0_pins_5_o_ie(),
.gpio_0_pins_5_o_pue(),
.gpio_0_pins_5_o_ds(),
.gpio_0_pins_5_o_ps(),
.gpio_0_pins_5_o_ds1(),
.gpio_0_pins_5_o_poe(),
.gpio_0_pins_6_i_ival(gpio_i[6]),
.gpio_0_pins_6_i_po(1'b0),
.gpio_0_pins_6_o_oval(gpio_o[6]),
.gpio_0_pins_6_o_oe(),
.gpio_0_pins_6_o_ie(),
.gpio_0_pins_6_o_pue(),
.gpio_0_pins_6_o_ds(),
.gpio_0_pins_6_o_ps(),
.gpio_0_pins_6_o_ds1(),
.gpio_0_pins_6_o_poe(),
.gpio_0_pins_7_i_ival(gpio_i[7]),
.gpio_0_pins_7_i_po(1'b0),
.gpio_0_pins_7_o_oval(gpio_o[7]),
.gpio_0_pins_7_o_oe(),
.gpio_0_pins_7_o_ie(),
.gpio_0_pins_7_o_pue(),
.gpio_0_pins_7_o_ds(),
.gpio_0_pins_7_o_ps(),
.gpio_0_pins_7_o_ds1(),
.gpio_0_pins_7_o_poe(),
.uart_0_txd(),
.uart_0_rxd(1'b0),
// .pwm_0_gpio_0(),
// .pwm_0_gpio_1(),
// .pwm_0_gpio_2(),
// .pwm_0_gpio_3(),
.spi_0_sck(),
.spi_0_dq_0_i(1'b0),
.spi_0_dq_0_o(),
.spi_0_dq_0_ie(),
.spi_0_dq_0_oe(),
.spi_0_dq_1_i(1'b0),
.spi_0_dq_1_o(),
.spi_0_dq_1_ie(),
.spi_0_dq_1_oe(),
.spi_0_dq_2_i(1'b0),
.spi_0_dq_2_o(),
.spi_0_dq_2_ie(),
.spi_0_dq_2_oe(),
.spi_0_dq_3_i(1'b0),
.spi_0_dq_3_o(),
.spi_0_dq_3_ie(),
.spi_0_dq_3_oe(),
.spi_0_cs_0(),
.spi_0_cs_1(),
.spi_0_cs_2(),
.spi_0_cs_3(),
.i2c_0_scl_in(1'b0),
.i2c_0_scl_out(),
.i2c_0_scl_oe(),
.i2c_0_sda_in(1'b0),
.i2c_0_sda_out(),
.i2c_0_sda_oe(),
.interrupts(2'b0),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[2]),
.cdrInIO_uDatIn(),
.cdrInIO_isLast(1'b1),
.cdrOutIO_dDatOut(),
.cdrOutIO_uDatOut(uDatSer[2]),
.cdrOutIO_isOnline(),
.fsmcio_ADIn(16'b0),
.fsmcio_ADOut(),
.fsmcio_ADOEn(),
.fsmcio_csn(1'b1),
.fsmcio_rdn(1'b1),
.fsmcio_wrn(1'b1),
.fsmcio_advn(1'b1)
);
// wire debugger_success;
// debuger i_debuger(
// .success(debugger_success),
// .DEBUGER_AWID (mmio_axi4_0_aw_bits_id),
// .DEBUGER_BID (mmio_axi4_0_b_bits_id),
// .DEBUGER_ARID (mmio_axi4_0_ar_bits_id),
// .DEBUGER_RID (mmio_axi4_0_r_bits_id),
// .DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
// .DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
// .DEBUGER_AWREADY(mmio_axi4_0_aw_ready),
// .DEBUGER_WDATA (mmio_axi4_0_w_bits_data),
// .DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
// .DEBUGER_WVALID(mmio_axi4_0_w_valid),
// .DEBUGER_WREADY(mmio_axi4_0_w_ready),
// .DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
// .DEBUGER_BVALID(mmio_axi4_0_b_valid),
// .DEBUGER_BREADY(mmio_axi4_0_b_ready),
// .DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
// .DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
// .DEBUGER_ARREADY(mmio_axi4_0_ar_ready),
// .DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
// .DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
// .DEBUGER_RVALID(mmio_axi4_0_r_valid),
// .DEBUGER_RREADY(mmio_axi4_0_r_ready),
// .CLK(CLK),
// .RSTn(RSTn)
// );
// reg [1023:0] firmware_file;
// initial begin
// if ($value$plusargs("%s", firmware_file)) begin
// $display("%s", firmware_file);
// $readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
// end
// end
// assign success = debugger_success;
initial begin
#1000
s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 0;
s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 1;
s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 2;
s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 3;
end
string testName;
`define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram
reg [7:0] mem0 [0:200000];
reg [7:0] mem1 [0:200000];
reg [7:0] mem2 [0:200000];
reg [7:0] mem3 [0:200000];
localparam DP = 8192;
integer i;
initial begin
#20
$readmemh("./tb/sw/build/mstTest.verilog", mem0);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin
`MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]};
end
else begin
`MEM0[i] = 32'h0;
end
// $display("MEM0[%d] = %h", i, `MEM0[i]);
end
$readmemh("./tb/sw/build/slvTest.verilog", mem1);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
`MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
end
else begin
`MEM1[i] = 32'h0;
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem2);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
`MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
end
else begin
`MEM2[i] = 32'h0;
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem3);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
`MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
end
else begin
`MEM3[i] = 32'h0;
end
end
end
endmodule

17
tb/verilator/plusarg_reader.v
View File

@@ -1,17 +0,0 @@
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(
parameter FORMAT="borked=%d",
parameter WIDTH=1,
parameter [WIDTH-1:0] DEFAULT=0
) (
output [WIDTH-1:0] out
);
assign out = DEFAULT;
endmodule

183
tb/verilator/sim_main.cpp
View File

@@ -1,183 +0,0 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <verilated.h>
#include "VSimTop.h"
#include <memory>
#include <iostream>
#include <getopt.h>
#include <sstream>
#if VM_TRACE
#include "verilated_fst_c.h"
#endif
char* img;
VSimTop *top;
#if VM_TRACE
VerilatedFstC* tfp;
#endif
vluint64_t main_time = 0;
vluint64_t main_cycle = 0;
double sc_time_stamp () {
return main_time;
}
uint8_t flag_waveEnable = 0;
uint8_t flag_limitEnable = 0;
static void init_and_clock();
int prase_arg(int argc, char **argv) {
int opt;
while( -1 != ( opt = getopt( argc, argv, "pjldwf:" ) ) ) {
switch(opt) {
case 'l':
flag_limitEnable = 1;
break;
case 'w':
flag_waveEnable = 1;
std::cout << "Waveform is Enable" << std::endl;
break;
case 'f':
img = strdup(optarg);
// std::cout << "load in image is " << img << std::endl;
break;
case '?':
std::cout << "-w to enable waveform" << std::endl;
std::cout << "-f FILENAME to testfile" << std::endl;
return -1;
break;
default:
std::cout << opt << std::endl;
assert(0);
}
}
return 0;
}
static void sim_exit(){
#if VM_TRACE
if ( flag_waveEnable ) { tfp->close(); }
#endif
top->final();
delete top;
}
int main(int argc, char **argv, char **env) {
if ( -1 == prase_arg(argc, argv) ) {
std::cout << "Prase Error." << std::endl;
return -1;
}
// char * temp[2];
// char cmd[64] = "+";
// strcat(cmd, img);
// strcat(cmd, ".verilog");
// temp[0] = "Verilated";
// temp[1] = cmd;
// char **argv_temp = temp;
// Verilated::commandArgs(2, argv_temp);
top = new VSimTop();
#if VM_TRACE
tfp = new VerilatedFstC;
if (flag_waveEnable) {
Verilated::traceEverOn(true);
top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("./tb/build/wave.fst");
}
#endif
top->reset = 1;
top->clock = 0;
top->clk800 = 0;
while(!Verilated::gotFinish()) {
Verilated::timeInc(1);
init_and_clock();
top->eval();
#if VM_TRACE
if ( flag_waveEnable ) { tfp->dump(Verilated::time()); }
#endif
if ( flag_limitEnable ) {
if ( main_cycle > 45000 ){
std::cout << "Timeout!!!!!" << std::endl;
sim_exit();
return -1;
}
}
main_time ++;
}
sim_exit();
return -1;
}
static void init_and_clock(){
//de-assert reset
if ( main_time != 100 ){
} else {
top->reset = 0;
}
//main clock
if ( main_time % 40 == 1 ) {
top->clock = 1;
} else if ( main_time % 40 == 21 ) {
top->clock = 0;
main_cycle ++;
}
uint8_t phase = 1;
if ( main_time % 5 == (0+phase) ) {
top->clk800 = 1;
} else if ( main_time % 5 == (2+phase) ) {
top->clk800 = 0;
}
}