From 26367fd63c3f04338adf210e5bbf6a7837a936ef Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 11 Sep 2025 14:30:08 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=A0=E9=99=A4=E5=85=B6=E5=AE=83=E9=A1=B9?= =?UTF-8?q?=E7=9B=AE=E8=AE=BE=E8=AE=A1=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/FPGATop.v | 316 --- src/main/resources/picorv32.v | 2280 ----------------- src/main/scala/backBoard/BackBoardMst.scala | 647 ----- src/main/scala/backBoard/BackBoardSlv.scala | 86 - src/main/scala/backBoard/DIn16.scala | 139 - src/main/scala/backBoard/Dout16.scala | 115 - src/main/scala/backBoard/LocalRegisters.scala | 137 - src/main/scala/backBoard/MirrorSRAM.scala | 335 --- src/main/scala/backBoard/Qei.scala | 160 -- src/main/scala/backBoard/Readme.md | 36 - src/main/scala/backBoard/SpiSlv.scala | 153 -- .../scala/backBoard/ebus/Axis8toN.scala.bk | 29 - .../scala/backBoard/ebus/AxisNto8.scala.bk | 48 - .../backBoard/ebus/BackBoardMst.scala.bk | 52 - .../backBoard/ebus/BackBoardSlv.scala.bk | 105 - .../scala/backBoard/ebus/CDR4MultiIn.scala.bk | 82 - .../scala/backBoard/ebus/CDROutBus.scala.bk | 65 - .../scala/backBoard/ebus/RoCC2CDR.scala.bk | 649 ----- src/main/scala/backBoard/ebus/SpiSlv.scala.bk | 89 - src/main/scala/backBoard/ebus/TL2CDR.scala.bk | 456 ---- src/main/scala/backBoard/goWinBus.scala | 304 --- .../scala/backBoard/pico/BackSystem.scala.bk | 123 - .../backBoard/pico/Picorv32_mem.scala.bk | 60 - .../scala/backBoard/pico/Picorv32_tl.scala.bk | 79 - .../scala/backBoard/pico/SimpleGpio.scala.bk | 42 - .../scala/backBoard/pico/SimpleSRAM.scala.bk | 42 - src/main/scala/backBoard/pico/TLCDR.scala.bk | 219 -- .../scala/backBoard/pico/picorv32.scala.bk | 53 - src/main/verilog/CDRIn_fpga.v | 93 - src/main/verilog/CDROne_fpga.v | 69 - src/main/verilog/CDROut_fpga.v | 147 -- src/main/verilog/backBoardMstTop.v | 252 -- src/main/verilog/defineParam.v | 15 - src/main/verilog/di16_top.v | 319 --- src/main/verilog/do16c_top.v | 330 --- src/main/verilog/do16p_top.v | 333 --- src/main/verilog/oser_rst.v | 117 - src/main/verilog/spi_top.v | 336 --- src/test/scala/ethPhy.scala.bk | 1353 ---------- .../scala/gcd/BackPlaneChainTest.scala.bk | 87 - src/test/scala/gcd/BackPlaneMstTest.scala.bk | 87 - src/test/scala/gcd/BackPlaneSlvTest.scala.bk | 63 - src/test/scala/gcd/MacAXI.scala.bk | 82 - src/test/scala/gcd/Mac_test_top.scala | 41 - src/test/scala/gcd/test.scala | 113 - tb/ShinBack_tb.v | 243 -- tb/backSys_tb.v | 191 -- tb/cdrInOut_tb.v | 148 -- tb/cdrOut_tb.v | 113 - tb/sim_backChain.cpp | 244 -- tb/sim_backMst.cpp | 175 -- tb/sim_backSlv.cpp | 147 -- tb/verilator/SimTop.v | 946 ------- tb/verilator/plusarg_reader.v | 17 - tb/verilator/sim_main.cpp | 183 -- 55 files changed, 13145 deletions(-) delete mode 100644 src/FPGATop.v delete mode 100644 src/main/resources/picorv32.v delete mode 100644 src/main/scala/backBoard/BackBoardMst.scala delete mode 100644 src/main/scala/backBoard/BackBoardSlv.scala delete mode 100644 src/main/scala/backBoard/DIn16.scala delete mode 100644 src/main/scala/backBoard/Dout16.scala delete mode 100644 src/main/scala/backBoard/LocalRegisters.scala delete mode 100644 src/main/scala/backBoard/MirrorSRAM.scala delete mode 100644 src/main/scala/backBoard/Qei.scala delete mode 100644 src/main/scala/backBoard/Readme.md delete mode 100644 src/main/scala/backBoard/SpiSlv.scala delete mode 100644 src/main/scala/backBoard/ebus/Axis8toN.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/AxisNto8.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/BackBoardMst.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/CDROutBus.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/SpiSlv.scala.bk delete mode 100644 src/main/scala/backBoard/ebus/TL2CDR.scala.bk delete mode 100644 src/main/scala/backBoard/goWinBus.scala delete mode 100644 src/main/scala/backBoard/pico/BackSystem.scala.bk delete mode 100644 src/main/scala/backBoard/pico/Picorv32_mem.scala.bk delete mode 100644 src/main/scala/backBoard/pico/Picorv32_tl.scala.bk delete mode 100644 src/main/scala/backBoard/pico/SimpleGpio.scala.bk delete mode 100644 src/main/scala/backBoard/pico/SimpleSRAM.scala.bk delete mode 100644 src/main/scala/backBoard/pico/TLCDR.scala.bk delete mode 100644 src/main/scala/backBoard/pico/picorv32.scala.bk delete mode 100644 src/main/verilog/CDRIn_fpga.v delete mode 100644 src/main/verilog/CDROne_fpga.v delete mode 100644 src/main/verilog/CDROut_fpga.v delete mode 100644 src/main/verilog/backBoardMstTop.v delete mode 100644 src/main/verilog/defineParam.v delete mode 100644 src/main/verilog/di16_top.v delete mode 100644 src/main/verilog/do16c_top.v delete mode 100644 src/main/verilog/do16p_top.v delete mode 100644 src/main/verilog/oser_rst.v delete mode 100644 src/main/verilog/spi_top.v delete mode 100644 src/test/scala/ethPhy.scala.bk delete mode 100644 src/test/scala/gcd/BackPlaneChainTest.scala.bk delete mode 100644 src/test/scala/gcd/BackPlaneMstTest.scala.bk delete mode 100644 src/test/scala/gcd/BackPlaneSlvTest.scala.bk delete mode 100644 src/test/scala/gcd/MacAXI.scala.bk delete mode 100644 src/test/scala/gcd/Mac_test_top.scala delete mode 100644 src/test/scala/gcd/test.scala delete mode 100644 tb/ShinBack_tb.v delete mode 100644 tb/backSys_tb.v delete mode 100644 tb/cdrInOut_tb.v delete mode 100644 tb/cdrOut_tb.v delete mode 100644 tb/sim_backChain.cpp delete mode 100644 tb/sim_backMst.cpp delete mode 100644 tb/sim_backSlv.cpp delete mode 100644 tb/verilator/SimTop.v delete mode 100644 tb/verilator/plusarg_reader.v delete mode 100644 tb/verilator/sim_main.cpp diff --git a/src/FPGATop.v b/src/FPGATop.v deleted file mode 100644 index 60befa0..0000000 --- a/src/FPGATop.v +++ /dev/null @@ -1,316 +0,0 @@ - - -module FPGATop( - input clock, - input reset, - (* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TCK" *) - input debug_systemjtag_jtag_TCK, - (* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TMS" *) - input debug_systemjtag_jtag_TMS, - (* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TD_I" *) - input debug_systemjtag_jtag_TDI, - (* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TD_O" *) - output debug_systemjtag_jtag_TDO_data, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWREADY" *) - input mem_axi4_0_aw_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWVALID" *) - output mem_axi4_0_aw_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWID" *) - output [3:0] mem_axi4_0_aw_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWADDR" *) - output [31:0] mem_axi4_0_aw_bits_addr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWLEN" *) - output [7:0] mem_axi4_0_aw_bits_len, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWSIZE" *) - output [2:0] mem_axi4_0_aw_bits_size, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWBURST" *) - output [1:0] mem_axi4_0_aw_bits_burst, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWLOCK" *) - output mem_axi4_0_aw_bits_lock, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWCACHE" *) - output [3:0] mem_axi4_0_aw_bits_cache, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWPROT" *) - output [2:0] mem_axi4_0_aw_bits_prot, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWQOS" *) - output [3:0] mem_axi4_0_aw_bits_qos, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WREADY" *) - input mem_axi4_0_w_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WVALID" *) - output mem_axi4_0_w_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WDATA" *) - output [31:0] mem_axi4_0_w_bits_data, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WSTRB" *) - output [3:0] mem_axi4_0_w_bits_strb, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WLAST" *) - output mem_axi4_0_w_bits_last, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BREADY" *) - output mem_axi4_0_b_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BVALID" *) - input mem_axi4_0_b_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BID" *) - input [3:0] mem_axi4_0_b_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BRESP" *) - input [1:0] mem_axi4_0_b_bits_resp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARREADY" *) - input mem_axi4_0_ar_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARVALID" *) - output mem_axi4_0_ar_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARID" *) - output [3:0] mem_axi4_0_ar_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARADDR" *) - output [31:0] mem_axi4_0_ar_bits_addr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARLEN" *) - output [7:0] mem_axi4_0_ar_bits_len, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARSIZE" *) - output [2:0] mem_axi4_0_ar_bits_size, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARBURST" *) - output [1:0] mem_axi4_0_ar_bits_burst, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARLOCK" *) - output mem_axi4_0_ar_bits_lock, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARCACHE" *) - output [3:0] mem_axi4_0_ar_bits_cache, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARPROT" *) - output [2:0] mem_axi4_0_ar_bits_prot, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARQOS" *) - output [3:0] mem_axi4_0_ar_bits_qos, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RREADY" *) - output mem_axi4_0_r_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RVALID" *) - input mem_axi4_0_r_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RID" *) - input [3:0] mem_axi4_0_r_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RDATA" *) - input [31:0] mem_axi4_0_r_bits_data, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RRESP" *) - input [1:0] mem_axi4_0_r_bits_resp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RLAST" *) - input mem_axi4_0_r_bits_last, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWREADY" *) - input mmio_axi4_0_aw_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWVALID" *) - output mmio_axi4_0_aw_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWID" *) - output [3:0] mmio_axi4_0_aw_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWADDR" *) - output [30:0] mmio_axi4_0_aw_bits_addr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWLEN" *) - output [7:0] mmio_axi4_0_aw_bits_len, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWSIZE" *) - output [2:0] mmio_axi4_0_aw_bits_size, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWBURST" *) - output [1:0] mmio_axi4_0_aw_bits_burst, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWLOCK" *) - output mmio_axi4_0_aw_bits_lock, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWCACHE" *) - output [3:0] mmio_axi4_0_aw_bits_cache, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWPROT" *) - output [2:0] mmio_axi4_0_aw_bits_prot, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWQOS" *) - output [3:0] mmio_axi4_0_aw_bits_qos, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WREADY" *) - input mmio_axi4_0_w_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WVALID" *) - output mmio_axi4_0_w_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WDATA" *) - output [31:0] mmio_axi4_0_w_bits_data, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WSTRB" *) - output [3:0] mmio_axi4_0_w_bits_strb, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WLAST" *) - output mmio_axi4_0_w_bits_last, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BREADY" *) - output mmio_axi4_0_b_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BVALID" *) - input mmio_axi4_0_b_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BID" *) - input [3:0] mmio_axi4_0_b_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BRESP" *) - input [1:0] mmio_axi4_0_b_bits_resp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARREADY" *) - input mmio_axi4_0_ar_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARVALID" *) - output mmio_axi4_0_ar_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARID" *) - output [3:0] mmio_axi4_0_ar_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARADDR" *) - output [30:0] mmio_axi4_0_ar_bits_addr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARLEN" *) - output [7:0] mmio_axi4_0_ar_bits_len, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARSIZE" *) - output [2:0] mmio_axi4_0_ar_bits_size, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARBURST" *) - output [1:0] mmio_axi4_0_ar_bits_burst, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARLOCK" *) - output mmio_axi4_0_ar_bits_lock, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARCACHE" *) - output [3:0] mmio_axi4_0_ar_bits_cache, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARPROT" *) - output [2:0] mmio_axi4_0_ar_bits_prot, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARQOS" *) - output [3:0] mmio_axi4_0_ar_bits_qos, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RREADY" *) - output mmio_axi4_0_r_ready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RVALID" *) - input mmio_axi4_0_r_valid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RID" *) - input [3:0] mmio_axi4_0_r_bits_id, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RDATA" *) - input [31:0] mmio_axi4_0_r_bits_data, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RRESP" *) - input [1:0] mmio_axi4_0_r_bits_resp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RLAST" *) - input mmio_axi4_0_r_bits_last, - - output macIO_mdc, - inout mdio, - - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TX_CLK" *) - input macIO_mtx_clk_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TXD" *) - output [3:0] macIO_mtxd_pad_o, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TX_EN" *) - output macIO_mtxen_pad_o, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_CLK" *) - input macIO_mrx_clk_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RXD" *) - input [3:0] macIO_mrxd_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_DV" *) - input macIO_mrxdv_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_ER" *) - input macIO_mrxerr_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII COL" *) - input macIO_mcoll_pad_i, - (* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII CRS" *) - input macIO_mcrs_pad_i -); - - -wire active; -wire mdi; -wire mdo; -wire mdoEn; - - -ExampleRocketSystem i_rocketChip( - .clock(clock), - .reset(reset), - .resetctrl_hartIsInReset_0(reset), - .debug_clock(clock), - .debug_reset(reset), - .debug_systemjtag_jtag_TCK(debug_systemjtag_jtag_TCK), - .debug_systemjtag_jtag_TMS(debug_systemjtag_jtag_TMS), - .debug_systemjtag_jtag_TDI(debug_systemjtag_jtag_TDI), - .debug_systemjtag_jtag_TDO_data(debug_systemjtag_jtag_TDO_data), - .debug_systemjtag_jtag_TDO_driven(), - .debug_systemjtag_reset(reset), - .debug_systemjtag_mfr_id(11'b0), - .debug_systemjtag_part_number(16'b0), - .debug_systemjtag_version(4'b0), - .debug_ndreset(), - .debug_dmactive(active), - .debug_dmactiveAck(active), - .mem_axi4_0_aw_ready(mem_axi4_0_aw_ready), - .mem_axi4_0_aw_valid(mem_axi4_0_aw_valid), - .mem_axi4_0_aw_bits_id(mem_axi4_0_aw_bits_id), - .mem_axi4_0_aw_bits_addr(mem_axi4_0_aw_bits_addr), - .mem_axi4_0_aw_bits_len(mem_axi4_0_aw_bits_len), - .mem_axi4_0_aw_bits_size(mem_axi4_0_aw_bits_size), - .mem_axi4_0_aw_bits_burst(mem_axi4_0_aw_bits_burst), - .mem_axi4_0_aw_bits_lock(mem_axi4_0_aw_bits_lock), - .mem_axi4_0_aw_bits_cache(mem_axi4_0_aw_bits_cache), - .mem_axi4_0_aw_bits_prot(mem_axi4_0_aw_bits_prot), - .mem_axi4_0_aw_bits_qos(mem_axi4_0_aw_bits_qos), - .mem_axi4_0_w_ready(mem_axi4_0_w_ready), - .mem_axi4_0_w_valid(mem_axi4_0_w_valid), - .mem_axi4_0_w_bits_data(mem_axi4_0_w_bits_data), - .mem_axi4_0_w_bits_strb(mem_axi4_0_w_bits_strb), - .mem_axi4_0_w_bits_last(mem_axi4_0_w_bits_last), - .mem_axi4_0_b_ready(mem_axi4_0_b_ready), - .mem_axi4_0_b_valid(mem_axi4_0_b_valid), - .mem_axi4_0_b_bits_id(mem_axi4_0_b_bits_id), - .mem_axi4_0_b_bits_resp(mem_axi4_0_b_bits_resp), - .mem_axi4_0_ar_ready(mem_axi4_0_ar_ready), - .mem_axi4_0_ar_valid(mem_axi4_0_ar_valid), - .mem_axi4_0_ar_bits_id(mem_axi4_0_ar_bits_id), - .mem_axi4_0_ar_bits_addr(mem_axi4_0_ar_bits_addr), - .mem_axi4_0_ar_bits_len(mem_axi4_0_ar_bits_len), - .mem_axi4_0_ar_bits_size(mem_axi4_0_ar_bits_size), - .mem_axi4_0_ar_bits_burst(mem_axi4_0_ar_bits_burst), - .mem_axi4_0_ar_bits_lock(mem_axi4_0_ar_bits_lock), - .mem_axi4_0_ar_bits_cache(mem_axi4_0_ar_bits_cache), - .mem_axi4_0_ar_bits_prot(mem_axi4_0_ar_bits_prot), - .mem_axi4_0_ar_bits_qos(mem_axi4_0_ar_bits_qos), - .mem_axi4_0_r_ready(mem_axi4_0_r_ready), - .mem_axi4_0_r_valid(mem_axi4_0_r_valid), - .mem_axi4_0_r_bits_id(mem_axi4_0_r_bits_id), - .mem_axi4_0_r_bits_data(mem_axi4_0_r_bits_data), - .mem_axi4_0_r_bits_resp(mem_axi4_0_r_bits_resp), - .mem_axi4_0_r_bits_last(mem_axi4_0_r_bits_last), - - .mmio_axi4_0_aw_ready(mmio_axi4_0_aw_ready), - .mmio_axi4_0_aw_valid(mmio_axi4_0_aw_valid), - .mmio_axi4_0_aw_bits_id(mmio_axi4_0_aw_bits_id), - .mmio_axi4_0_aw_bits_addr(mmio_axi4_0_aw_bits_addr), - .mmio_axi4_0_aw_bits_len(mmio_axi4_0_aw_bits_len), - .mmio_axi4_0_aw_bits_size(mmio_axi4_0_aw_bits_size), - .mmio_axi4_0_aw_bits_burst(mmio_axi4_0_aw_bits_burst), - .mmio_axi4_0_aw_bits_lock(mmio_axi4_0_aw_bits_lock), - .mmio_axi4_0_aw_bits_cache(mmio_axi4_0_aw_bits_cache), - .mmio_axi4_0_aw_bits_prot(mmio_axi4_0_aw_bits_prot), - .mmio_axi4_0_aw_bits_qos(mmio_axi4_0_aw_bits_qos), - .mmio_axi4_0_w_ready(mmio_axi4_0_w_ready), - .mmio_axi4_0_w_valid(mmio_axi4_0_w_valid), - .mmio_axi4_0_w_bits_data(mmio_axi4_0_w_bits_data), - .mmio_axi4_0_w_bits_strb(mmio_axi4_0_w_bits_strb), - .mmio_axi4_0_w_bits_last(mmio_axi4_0_w_bits_last), - .mmio_axi4_0_b_ready(mmio_axi4_0_b_ready), - .mmio_axi4_0_b_valid(mmio_axi4_0_b_valid), - .mmio_axi4_0_b_bits_id(mmio_axi4_0_b_bits_id), - .mmio_axi4_0_b_bits_resp(mmio_axi4_0_b_bits_resp), - .mmio_axi4_0_ar_ready(mmio_axi4_0_ar_ready), - .mmio_axi4_0_ar_valid(mmio_axi4_0_ar_valid), - .mmio_axi4_0_ar_bits_id(mmio_axi4_0_ar_bits_id), - .mmio_axi4_0_ar_bits_addr(mmio_axi4_0_ar_bits_addr), - .mmio_axi4_0_ar_bits_len(mmio_axi4_0_ar_bits_len), - .mmio_axi4_0_ar_bits_size(mmio_axi4_0_ar_bits_size), - .mmio_axi4_0_ar_bits_burst(mmio_axi4_0_ar_bits_burst), - .mmio_axi4_0_ar_bits_lock(mmio_axi4_0_ar_bits_lock), - .mmio_axi4_0_ar_bits_cache(mmio_axi4_0_ar_bits_cache), - .mmio_axi4_0_ar_bits_prot(mmio_axi4_0_ar_bits_prot), - .mmio_axi4_0_ar_bits_qos(mmio_axi4_0_ar_bits_qos), - .mmio_axi4_0_r_ready(mmio_axi4_0_r_ready), - .mmio_axi4_0_r_valid(mmio_axi4_0_r_valid), - .mmio_axi4_0_r_bits_id(mmio_axi4_0_r_bits_id), - .mmio_axi4_0_r_bits_data(mmio_axi4_0_r_bits_data), - .mmio_axi4_0_r_bits_resp(mmio_axi4_0_r_bits_resp), - .mmio_axi4_0_r_bits_last(mmio_axi4_0_r_bits_last), - .interrupts(2'b0), - .macIO_mdi(mdi), - .macIO_mdc(macIO_mdc), - .macIO_mdo(mdo), - .macIO_mdoEn(mdoEn), - .macIO_mtx_clk_pad_i(macIO_mtx_clk_pad_i), - .macIO_mtxd_pad_o(macIO_mtxd_pad_o), - .macIO_mtxen_pad_o(macIO_mtxen_pad_o), - .macIO_mtxerr_pad_o(), - .macIO_mrx_clk_pad_i(macIO_mrx_clk_pad_i), - .macIO_mrxd_pad_i(macIO_mrxd_pad_i), - .macIO_mrxdv_pad_i(macIO_mrxdv_pad_i), - .macIO_mrxerr_pad_i(macIO_mrxerr_pad_i), - .macIO_mcoll_pad_i(macIO_mcoll_pad_i), - .macIO_mcrs_pad_i(macIO_mcrs_pad_i) -); - - - IOBUF #( - .DRIVE(12), // Specify the output drive strength - .IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE" - .IOSTANDARD("DEFAULT"), // Specify the I/O standard - .SLEW("SLOW") // Specify the output slew rate - ) IOBUF_inst ( - .O(mdi), // Buffer output - .IO(mdio), // Buffer inout port (connect directly to top-level port) - .I(mdo), // Buffer input - .T(~mdoEn) // 3-state enable input, high=input, low=output - ); - -endmodule diff --git a/src/main/resources/picorv32.v b/src/main/resources/picorv32.v deleted file mode 100644 index d7ca9d9..0000000 --- a/src/main/resources/picorv32.v +++ /dev/null @@ -1,2280 +0,0 @@ -/* - * PicoRV32 -- A Small RISC-V (RV32I) Processor Core - * - * Copyright (C) 2015 Claire Xenia Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -/* verilator lint_off WIDTH */ -/* verilator lint_off PINMISSING */ -/* verilator lint_off CASEOVERLAP */ -/* verilator lint_off CASEINCOMPLETE */ - -`timescale 1 ns / 1 ps -// `default_nettype none -// `define DEBUGNETS -// `define DEBUGREGS -// `define DEBUGASM -// `define DEBUG - -`ifndef PICORV32_REGS - `define PICORV32_REGS picosoc_regs -`endif - - - -`define debug(debug_command) - - - - -`define FORMAL_KEEP - -`define assert(assert_expr) empty_statement - - -// uncomment this for register file in extra module -// `define PICORV32_REGS picorv32_regs - -// this macro can be used to check if the verilog files in your -// design are read in the correct order. -`define PICORV32_V - - -/*************************************************************** - * picorv32 - ***************************************************************/ - -module picorv32 #( - parameter [ 0:0] ENABLE_COUNTERS = 1, - parameter [ 0:0] ENABLE_COUNTERS64 = 0, - parameter [ 0:0] ENABLE_REGS_16_31 = 1, - parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, - parameter [ 0:0] LATCHED_MEM_RDATA = 0, - parameter [ 0:0] TWO_STAGE_SHIFT = 0, - parameter [ 0:0] BARREL_SHIFTER = 0, - parameter [ 0:0] TWO_CYCLE_COMPARE = 0, - parameter [ 0:0] TWO_CYCLE_ALU = 0, - parameter [ 0:0] COMPRESSED_ISA = 0, - parameter [ 0:0] CATCH_MISALIGN = 0, - parameter [ 0:0] CATCH_ILLINSN = 0, - parameter [ 0:0] ENABLE_PCPI = 0, - parameter [ 0:0] ENABLE_MUL = 0, - parameter [ 0:0] ENABLE_FAST_MUL = 0, - parameter [ 0:0] ENABLE_DIV = 0, - parameter [ 0:0] ENABLE_IRQ = 1, - parameter [ 0:0] ENABLE_IRQ_QREGS = 0, - parameter [ 0:0] ENABLE_IRQ_TIMER = 0, - parameter [ 0:0] ENABLE_TRACE = 0, - parameter [ 0:0] REGS_INIT_ZERO = 0, - parameter [31:0] MASKED_IRQ = 32'h 0000_0000, - parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, - parameter [31:0] PROGADDR_RESET = 32'h 8000_0000, - parameter [31:0] PROGADDR_IRQ = 32'h 8000_0800, - parameter [31:0] STACKADDR = 32'h ffff_ffff -) ( - input clk, resetn, - output reg trap, - - output reg mem_valid, - output reg mem_instr, - input mem_ready, - - output reg [31:0] mem_addr, - output reg [31:0] mem_wdata, - output reg [ 3:0] mem_wstrb, - input [31:0] mem_rdata, - - // Look-Ahead Interface - output mem_la_read, - output mem_la_write, - output [31:0] mem_la_addr, - output reg [31:0] mem_la_wdata, - output reg [ 3:0] mem_la_wstrb, - - // Pico Co-Processor Interface (PCPI) - output reg pcpi_valid, - output reg [31:0] pcpi_insn, - output [31:0] pcpi_rs1, - output [31:0] pcpi_rs2, - input pcpi_wr, - input [31:0] pcpi_rd, - input pcpi_wait, - input pcpi_ready, - - // IRQ Interface - input [31:0] irq, - output reg [31:0] eoi, - - - // Trace Interface - output reg trace_valid, - output reg [35:0] trace_data -); - localparam integer irq_timer = 0; - localparam integer irq_ebreak = 1; - localparam integer irq_buserror = 2; - - localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; - localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; - localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS; - - localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV; - - localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; - localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; - localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; - - reg [63:0] count_cycle, count_instr; - reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; - reg [4:0] reg_sh; - - reg [31:0] next_insn_opcode; - reg [31:0] dbg_insn_opcode; - reg [31:0] dbg_insn_addr; - - wire dbg_mem_valid = mem_valid; - wire dbg_mem_instr = mem_instr; - wire dbg_mem_ready = mem_ready; - wire [31:0] dbg_mem_addr = mem_addr; - wire [31:0] dbg_mem_wdata = mem_wdata; - wire [ 3:0] dbg_mem_wstrb = mem_wstrb; - wire [31:0] dbg_mem_rdata = mem_rdata; - - assign pcpi_rs1 = reg_op1; - assign pcpi_rs2 = reg_op2; - - wire [31:0] next_pc; - - reg irq_delay; - reg irq_active; - reg [31:0] irq_mask; - reg [31:0] irq_pending; - reg [31:0] timer; - -`ifndef PICORV32_REGS - reg [31:0] cpuregs [0:regfile_size-1]; - - integer i; - initial begin - if (REGS_INIT_ZERO) begin - for (i = 0; i < regfile_size; i = i+1) - cpuregs[i] = 0; - end - end -`endif - - task empty_statement; - // This task is used by the `assert directive in non-formal mode to - // avoid empty statement (which are unsupported by plain Verilog syntax). - begin end - endtask - -`ifdef DEBUGREGS - wire [31:0] dbg_reg_x0 = 0; - wire [31:0] dbg_reg_x1 = cpuregs[1]; - wire [31:0] dbg_reg_x2 = cpuregs[2]; - wire [31:0] dbg_reg_x3 = cpuregs[3]; - wire [31:0] dbg_reg_x4 = cpuregs[4]; - wire [31:0] dbg_reg_x5 = cpuregs[5]; - wire [31:0] dbg_reg_x6 = cpuregs[6]; - wire [31:0] dbg_reg_x7 = cpuregs[7]; - wire [31:0] dbg_reg_x8 = cpuregs[8]; - wire [31:0] dbg_reg_x9 = cpuregs[9]; - wire [31:0] dbg_reg_x10 = cpuregs[10]; - wire [31:0] dbg_reg_x11 = cpuregs[11]; - wire [31:0] dbg_reg_x12 = cpuregs[12]; - wire [31:0] dbg_reg_x13 = cpuregs[13]; - wire [31:0] dbg_reg_x14 = cpuregs[14]; - wire [31:0] dbg_reg_x15 = cpuregs[15]; - wire [31:0] dbg_reg_x16 = cpuregs[16]; - wire [31:0] dbg_reg_x17 = cpuregs[17]; - wire [31:0] dbg_reg_x18 = cpuregs[18]; - wire [31:0] dbg_reg_x19 = cpuregs[19]; - wire [31:0] dbg_reg_x20 = cpuregs[20]; - wire [31:0] dbg_reg_x21 = cpuregs[21]; - wire [31:0] dbg_reg_x22 = cpuregs[22]; - wire [31:0] dbg_reg_x23 = cpuregs[23]; - wire [31:0] dbg_reg_x24 = cpuregs[24]; - wire [31:0] dbg_reg_x25 = cpuregs[25]; - wire [31:0] dbg_reg_x26 = cpuregs[26]; - wire [31:0] dbg_reg_x27 = cpuregs[27]; - wire [31:0] dbg_reg_x28 = cpuregs[28]; - wire [31:0] dbg_reg_x29 = cpuregs[29]; - wire [31:0] dbg_reg_x30 = cpuregs[30]; - wire [31:0] dbg_reg_x31 = cpuregs[31]; -`endif - - // Internal PCPI Cores - - wire pcpi_mul_wr; - wire [31:0] pcpi_mul_rd; - wire pcpi_mul_wait; - wire pcpi_mul_ready; - - wire pcpi_div_wr; - wire [31:0] pcpi_div_rd; - wire pcpi_div_wait; - wire pcpi_div_ready; - - reg pcpi_int_wr; - reg [31:0] pcpi_int_rd; - reg pcpi_int_wait; - reg pcpi_int_ready; - - generate if (ENABLE_FAST_MUL) begin - picorv32_pcpi_fast_mul pcpi_mul ( - .clk (clk ), - .resetn (resetn ), - .pcpi_valid(pcpi_valid ), - .pcpi_insn (pcpi_insn ), - .pcpi_rs1 (pcpi_rs1 ), - .pcpi_rs2 (pcpi_rs2 ), - .pcpi_wr (pcpi_mul_wr ), - .pcpi_rd (pcpi_mul_rd ), - .pcpi_wait (pcpi_mul_wait ), - .pcpi_ready(pcpi_mul_ready ) - ); - end else if (ENABLE_MUL) begin - picorv32_pcpi_mul pcpi_mul ( - .clk (clk ), - .resetn (resetn ), - .pcpi_valid(pcpi_valid ), - .pcpi_insn (pcpi_insn ), - .pcpi_rs1 (pcpi_rs1 ), - .pcpi_rs2 (pcpi_rs2 ), - .pcpi_wr (pcpi_mul_wr ), - .pcpi_rd (pcpi_mul_rd ), - .pcpi_wait (pcpi_mul_wait ), - .pcpi_ready(pcpi_mul_ready ) - ); - end else begin - assign pcpi_mul_wr = 0; - assign pcpi_mul_rd = 32'bx; - assign pcpi_mul_wait = 0; - assign pcpi_mul_ready = 0; - end endgenerate - - generate if (ENABLE_DIV) begin - picorv32_pcpi_div pcpi_div ( - .clk (clk ), - .resetn (resetn ), - .pcpi_valid(pcpi_valid ), - .pcpi_insn (pcpi_insn ), - .pcpi_rs1 (pcpi_rs1 ), - .pcpi_rs2 (pcpi_rs2 ), - .pcpi_wr (pcpi_div_wr ), - .pcpi_rd (pcpi_div_rd ), - .pcpi_wait (pcpi_div_wait ), - .pcpi_ready(pcpi_div_ready ) - ); - end else begin - assign pcpi_div_wr = 0; - assign pcpi_div_rd = 32'bx; - assign pcpi_div_wait = 0; - assign pcpi_div_ready = 0; - end endgenerate - - always @* begin - pcpi_int_wr = 0; - pcpi_int_rd = 32'bx; - pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait}; - pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready}; - - (* parallel_case *) - case (1'b1) - ENABLE_PCPI && pcpi_ready: begin - pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0; - pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0; - end - (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin - pcpi_int_wr = pcpi_mul_wr; - pcpi_int_rd = pcpi_mul_rd; - end - ENABLE_DIV && pcpi_div_ready: begin - pcpi_int_wr = pcpi_div_wr; - pcpi_int_rd = pcpi_div_rd; - end - endcase - end - - - // Memory Interface - - reg [1:0] mem_state; - reg [1:0] mem_wordsize; - reg [31:0] mem_rdata_word; - reg [31:0] mem_rdata_q; - reg mem_do_prefetch; - reg mem_do_rinst; - reg mem_do_rdata; - reg mem_do_wdata; - - wire mem_xfer; - reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid; - wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword; - wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg); - - reg prefetched_high_word; - reg clear_prefetched_high_word; - reg [15:0] mem_16bit_buffer; - - wire [31:0] mem_rdata_latched_noshuffle; - wire [31:0] mem_rdata_latched; - - wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word; - assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst); - - wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; - wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && - (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer)); - - assign mem_la_write = resetn && !mem_state && mem_do_wdata; - assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || - (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0])); - assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00}; - - assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q; - - assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} : - COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : - COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle; - - always @(posedge clk) begin - if (!resetn) begin - mem_la_firstword_reg <= 0; - last_mem_valid <= 0; - end else begin - if (!last_mem_valid) - mem_la_firstword_reg <= mem_la_firstword; - last_mem_valid <= mem_valid && !mem_ready; - end - end - - always @* begin - (* full_case *) - case (mem_wordsize) - 0: begin - mem_la_wdata = reg_op2; - mem_la_wstrb = 4'b1111; - mem_rdata_word = mem_rdata; - end - 1: begin - mem_la_wdata = {2{reg_op2[15:0]}}; - mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; - case (reg_op1[1]) - 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; - 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; - endcase - end - 2: begin - mem_la_wdata = {4{reg_op2[7:0]}}; - mem_la_wstrb = 4'b0001 << reg_op1[1:0]; - case (reg_op1[1:0]) - 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; - 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; - 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; - 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; - endcase - end - endcase - end - - always @(posedge clk) begin - if (mem_xfer) begin - mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; - next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; - end - - if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin - case (mem_rdata_latched[1:0]) - 2'b00: begin // Quadrant 0 - case (mem_rdata_latched[15:13]) - 3'b000: begin // C.ADDI4SPN - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00}; - end - 3'b010: begin // C.LW - mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; - mem_rdata_q[14:12] <= 3'b 010; - end - 3'b 110: begin // C.SW - {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; - mem_rdata_q[14:12] <= 3'b 010; - end - endcase - end - 2'b01: begin // Quadrant 1 - case (mem_rdata_latched[15:13]) - 3'b 000: begin // C.ADDI - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); - end - 3'b 010: begin // C.LI - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); - end - 3'b 011: begin - if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3], - mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000}); - end else begin // C.LUI - mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); - end - end - 3'b100: begin - if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI - mem_rdata_q[31:25] <= 7'b0000000; - mem_rdata_q[14:12] <= 3'b 101; - end - if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI - mem_rdata_q[31:25] <= 7'b0100000; - mem_rdata_q[14:12] <= 3'b 101; - end - if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI - mem_rdata_q[14:12] <= 3'b111; - mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); - end - if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND - if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000; - if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100; - if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110; - if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111; - mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000; - end - end - 3'b 110: begin // C.BEQZ - mem_rdata_q[14:12] <= 3'b000; - { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= - $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], - mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); - end - 3'b 111: begin // C.BNEZ - mem_rdata_q[14:12] <= 3'b001; - { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= - $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], - mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); - end - endcase - end - 2'b10: begin // Quadrant 2 - case (mem_rdata_latched[15:13]) - 3'b000: begin // C.SLLI - mem_rdata_q[31:25] <= 7'b0000000; - mem_rdata_q[14:12] <= 3'b 001; - end - 3'b010: begin // C.LWSP - mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00}; - mem_rdata_q[14:12] <= 3'b 010; - end - 3'b100: begin - if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= 12'b0; - end - if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:25] <= 7'b0000000; - end - if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:20] <= 12'b0; - end - if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD - mem_rdata_q[14:12] <= 3'b000; - mem_rdata_q[31:25] <= 7'b0000000; - end - end - 3'b110: begin // C.SWSP - {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; - mem_rdata_q[14:12] <= 3'b 010; - end - endcase - end - endcase - end - end - - always @(posedge clk) begin - if (resetn && !trap) begin - if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) - `assert(!mem_do_wdata); - - if (mem_do_prefetch || mem_do_rinst) - `assert(!mem_do_rdata); - - if (mem_do_rdata) - `assert(!mem_do_prefetch && !mem_do_rinst); - - if (mem_do_wdata) - `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata)); - - if (mem_state == 2 || mem_state == 3) - `assert(mem_valid || mem_do_prefetch); - end - end - - always @(posedge clk) begin - if (!resetn || trap) begin - if (!resetn) - mem_state <= 0; - if (!resetn || mem_ready) - mem_valid <= 0; - mem_la_secondword <= 0; - prefetched_high_word <= 0; - end else begin - if (mem_la_read || mem_la_write) begin - mem_addr <= mem_la_addr; - mem_wstrb <= mem_la_wstrb & {4{mem_la_write}}; - end - if (mem_la_write) begin - mem_wdata <= mem_la_wdata; - end - case (mem_state) - 0: begin - if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin - mem_valid <= !mem_la_use_prefetched_high_word; - mem_instr <= mem_do_prefetch || mem_do_rinst; - mem_wstrb <= 0; - mem_state <= 1; - end - if (mem_do_wdata) begin - mem_valid <= 1; - mem_instr <= 0; - mem_state <= 2; - end - end - 1: begin - `assert(mem_wstrb == 0); - `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata); - `assert(mem_valid == !mem_la_use_prefetched_high_word); - `assert(mem_instr == (mem_do_prefetch || mem_do_rinst)); - if (mem_xfer) begin - if (COMPRESSED_ISA && mem_la_read) begin - mem_valid <= 1; - mem_la_secondword <= 1; - if (!mem_la_use_prefetched_high_word) - mem_16bit_buffer <= mem_rdata[31:16]; - end else begin - mem_valid <= 0; - mem_la_secondword <= 0; - if (COMPRESSED_ISA && !mem_do_rdata) begin - if (~&mem_rdata[1:0] || mem_la_secondword) begin - mem_16bit_buffer <= mem_rdata[31:16]; - prefetched_high_word <= 1; - end else begin - prefetched_high_word <= 0; - end - end - mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3; - end - end - end - 2: begin - `assert(mem_wstrb != 0); - `assert(mem_do_wdata); - if (mem_xfer) begin - mem_valid <= 0; - mem_state <= 0; - end - end - 3: begin - `assert(mem_wstrb == 0); - `assert(mem_do_prefetch); - if (mem_do_rinst) begin - mem_state <= 0; - end - end - endcase - end - - if (clear_prefetched_high_word) - prefetched_high_word <= 0; - end - - - // Instruction Decoder - - reg instr_lui, instr_auipc, instr_jal, instr_jalr; - reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; - reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; - reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; - reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; - reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak, instr_fence; - reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; - wire instr_trap; - - reg [regindex_bits-1:0] decoded_rd, decoded_rs1; - reg [4:0] decoded_rs2; - reg [31:0] decoded_imm, decoded_imm_j; - reg decoder_trigger; - reg decoder_trigger_q; - reg decoder_pseudo_trigger; - reg decoder_pseudo_trigger_q; - reg compressed_instr; - - reg is_lui_auipc_jal; - reg is_lb_lh_lw_lbu_lhu; - reg is_slli_srli_srai; - reg is_jalr_addi_slti_sltiu_xori_ori_andi; - reg is_sb_sh_sw; - reg is_sll_srl_sra; - reg is_lui_auipc_jal_jalr_addi_add_sub; - reg is_slti_blt_slt; - reg is_sltiu_bltu_sltu; - reg is_beq_bne_blt_bge_bltu_bgeu; - reg is_lbu_lhu_lw; - reg is_alu_reg_imm; - reg is_alu_reg_reg; - reg is_compare; - - assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, - instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, - instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, - instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, - instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, - instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_fence, - instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; - - wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; - assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; - - reg [63:0] new_ascii_instr; - `FORMAL_KEEP reg [63:0] dbg_ascii_instr; - `FORMAL_KEEP reg [31:0] dbg_insn_imm; - `FORMAL_KEEP reg [4:0] dbg_insn_rs1; - `FORMAL_KEEP reg [4:0] dbg_insn_rs2; - `FORMAL_KEEP reg [4:0] dbg_insn_rd; - `FORMAL_KEEP reg [31:0] dbg_rs1val; - `FORMAL_KEEP reg [31:0] dbg_rs2val; - `FORMAL_KEEP reg dbg_rs1val_valid; - `FORMAL_KEEP reg dbg_rs2val_valid; - - always @* begin - new_ascii_instr = ""; - - if (instr_lui) new_ascii_instr = "lui"; - if (instr_auipc) new_ascii_instr = "auipc"; - if (instr_jal) new_ascii_instr = "jal"; - if (instr_jalr) new_ascii_instr = "jalr"; - - if (instr_beq) new_ascii_instr = "beq"; - if (instr_bne) new_ascii_instr = "bne"; - if (instr_blt) new_ascii_instr = "blt"; - if (instr_bge) new_ascii_instr = "bge"; - if (instr_bltu) new_ascii_instr = "bltu"; - if (instr_bgeu) new_ascii_instr = "bgeu"; - - if (instr_lb) new_ascii_instr = "lb"; - if (instr_lh) new_ascii_instr = "lh"; - if (instr_lw) new_ascii_instr = "lw"; - if (instr_lbu) new_ascii_instr = "lbu"; - if (instr_lhu) new_ascii_instr = "lhu"; - if (instr_sb) new_ascii_instr = "sb"; - if (instr_sh) new_ascii_instr = "sh"; - if (instr_sw) new_ascii_instr = "sw"; - - if (instr_addi) new_ascii_instr = "addi"; - if (instr_slti) new_ascii_instr = "slti"; - if (instr_sltiu) new_ascii_instr = "sltiu"; - if (instr_xori) new_ascii_instr = "xori"; - if (instr_ori) new_ascii_instr = "ori"; - if (instr_andi) new_ascii_instr = "andi"; - if (instr_slli) new_ascii_instr = "slli"; - if (instr_srli) new_ascii_instr = "srli"; - if (instr_srai) new_ascii_instr = "srai"; - - if (instr_add) new_ascii_instr = "add"; - if (instr_sub) new_ascii_instr = "sub"; - if (instr_sll) new_ascii_instr = "sll"; - if (instr_slt) new_ascii_instr = "slt"; - if (instr_sltu) new_ascii_instr = "sltu"; - if (instr_xor) new_ascii_instr = "xor"; - if (instr_srl) new_ascii_instr = "srl"; - if (instr_sra) new_ascii_instr = "sra"; - if (instr_or) new_ascii_instr = "or"; - if (instr_and) new_ascii_instr = "and"; - - if (instr_rdcycle) new_ascii_instr = "rdcycle"; - if (instr_rdcycleh) new_ascii_instr = "rdcycleh"; - if (instr_rdinstr) new_ascii_instr = "rdinstr"; - if (instr_rdinstrh) new_ascii_instr = "rdinstrh"; - if (instr_fence) new_ascii_instr = "fence"; - - if (instr_getq) new_ascii_instr = "getq"; - if (instr_setq) new_ascii_instr = "setq"; - if (instr_retirq) new_ascii_instr = "retirq"; - if (instr_maskirq) new_ascii_instr = "maskirq"; - if (instr_waitirq) new_ascii_instr = "waitirq"; - if (instr_timer) new_ascii_instr = "timer"; - end - - reg [63:0] q_ascii_instr; - reg [31:0] q_insn_imm; - reg [31:0] q_insn_opcode; - reg [4:0] q_insn_rs1; - reg [4:0] q_insn_rs2; - reg [4:0] q_insn_rd; - reg dbg_next; - - wire launch_next_insn; - reg dbg_valid_insn; - - reg [63:0] cached_ascii_instr; - reg [31:0] cached_insn_imm; - reg [31:0] cached_insn_opcode; - reg [4:0] cached_insn_rs1; - reg [4:0] cached_insn_rs2; - reg [4:0] cached_insn_rd; - - always @(posedge clk) begin - q_ascii_instr <= dbg_ascii_instr; - q_insn_imm <= dbg_insn_imm; - q_insn_opcode <= dbg_insn_opcode; - q_insn_rs1 <= dbg_insn_rs1; - q_insn_rs2 <= dbg_insn_rs2; - q_insn_rd <= dbg_insn_rd; - dbg_next <= launch_next_insn; - - if (!resetn || trap) - dbg_valid_insn <= 0; - else if (launch_next_insn) - dbg_valid_insn <= 1; - - if (decoder_trigger_q) begin - cached_ascii_instr <= new_ascii_instr; - cached_insn_imm <= decoded_imm; - if (&next_insn_opcode[1:0]) - cached_insn_opcode <= next_insn_opcode; - else - cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]}; - cached_insn_rs1 <= decoded_rs1; - cached_insn_rs2 <= decoded_rs2; - cached_insn_rd <= decoded_rd; - end - - if (launch_next_insn) begin - dbg_insn_addr <= next_pc; - end - end - - always @* begin - dbg_ascii_instr = q_ascii_instr; - dbg_insn_imm = q_insn_imm; - dbg_insn_opcode = q_insn_opcode; - dbg_insn_rs1 = q_insn_rs1; - dbg_insn_rs2 = q_insn_rs2; - dbg_insn_rd = q_insn_rd; - - if (dbg_next) begin - if (decoder_pseudo_trigger_q) begin - dbg_ascii_instr = cached_ascii_instr; - dbg_insn_imm = cached_insn_imm; - dbg_insn_opcode = cached_insn_opcode; - dbg_insn_rs1 = cached_insn_rs1; - dbg_insn_rs2 = cached_insn_rs2; - dbg_insn_rd = cached_insn_rd; - end else begin - dbg_ascii_instr = new_ascii_instr; - if (&next_insn_opcode[1:0]) - dbg_insn_opcode = next_insn_opcode; - else - dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]}; - dbg_insn_imm = decoded_imm; - dbg_insn_rs1 = decoded_rs1; - dbg_insn_rs2 = decoded_rs2; - dbg_insn_rd = decoded_rd; - end - end - end - -`ifdef DEBUGASM - always @(posedge clk) begin - if (dbg_next) begin - $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); - end - end -`endif - - always @(posedge clk) begin - is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; - is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; - is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt}; - is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu}; - is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw}; - is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu}; - - if (mem_do_rinst && mem_done) begin - instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; - instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; - instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; - instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000; - instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; - instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; - - is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011; - is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011; - is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011; - is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; - is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; - - { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); - - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[19:15]; - decoded_rs2 <= mem_rdata_latched[24:20]; - - if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS) - decoded_rs1[regindex_bits-1] <= 1; // instr_getq - - if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ) - decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq - - compressed_instr <= 0; - if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin - compressed_instr <= 1; - decoded_rd <= 0; - decoded_rs1 <= 0; - decoded_rs2 <= 0; - - { decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6], - decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0}); - - case (mem_rdata_latched[1:0]) - 2'b00: begin // Quadrant 0 - case (mem_rdata_latched[15:13]) - 3'b000: begin // C.ADDI4SPN - is_alu_reg_imm <= |mem_rdata_latched[12:5]; - decoded_rs1 <= 2; - decoded_rd <= 8 + mem_rdata_latched[4:2]; - end - 3'b010: begin // C.LW - is_lb_lh_lw_lbu_lhu <= 1; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rd <= 8 + mem_rdata_latched[4:2]; - end - 3'b110: begin // C.SW - is_sb_sh_sw <= 1; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rs2 <= 8 + mem_rdata_latched[4:2]; - end - endcase - end - 2'b01: begin // Quadrant 1 - case (mem_rdata_latched[15:13]) - 3'b000: begin // C.NOP / C.ADDI - is_alu_reg_imm <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[11:7]; - end - 3'b001: begin // C.JAL - instr_jal <= 1; - decoded_rd <= 1; - end - 3'b 010: begin // C.LI - is_alu_reg_imm <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= 0; - end - 3'b 011: begin - if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin - if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP - is_alu_reg_imm <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[11:7]; - end else begin // C.LUI - instr_lui <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= 0; - end - end - end - 3'b100: begin - if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI - is_alu_reg_imm <= 1; - decoded_rd <= 8 + mem_rdata_latched[9:7]; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; - end - if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI - is_alu_reg_imm <= 1; - decoded_rd <= 8 + mem_rdata_latched[9:7]; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - end - if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND - is_alu_reg_reg <= 1; - decoded_rd <= 8 + mem_rdata_latched[9:7]; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rs2 <= 8 + mem_rdata_latched[4:2]; - end - end - 3'b101: begin // C.J - instr_jal <= 1; - end - 3'b110: begin // C.BEQZ - is_beq_bne_blt_bge_bltu_bgeu <= 1; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rs2 <= 0; - end - 3'b111: begin // C.BNEZ - is_beq_bne_blt_bge_bltu_bgeu <= 1; - decoded_rs1 <= 8 + mem_rdata_latched[9:7]; - decoded_rs2 <= 0; - end - endcase - end - 2'b10: begin // Quadrant 2 - case (mem_rdata_latched[15:13]) - 3'b000: begin // C.SLLI - if (!mem_rdata_latched[12]) begin - is_alu_reg_imm <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[11:7]; - decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; - end - end - 3'b010: begin // C.LWSP - if (mem_rdata_latched[11:7]) begin - is_lb_lh_lw_lbu_lhu <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= 2; - end - end - 3'b100: begin - if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR - instr_jalr <= 1; - decoded_rd <= 0; - decoded_rs1 <= mem_rdata_latched[11:7]; - end - if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV - is_alu_reg_reg <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= 0; - decoded_rs2 <= mem_rdata_latched[6:2]; - end - if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR - instr_jalr <= 1; - decoded_rd <= 1; - decoded_rs1 <= mem_rdata_latched[11:7]; - end - if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD - is_alu_reg_reg <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[11:7]; - decoded_rs2 <= mem_rdata_latched[6:2]; - end - end - 3'b110: begin // C.SWSP - is_sb_sh_sw <= 1; - decoded_rs1 <= 2; - decoded_rs2 <= mem_rdata_latched[6:2]; - end - endcase - end - endcase - end - end - - if (decoder_trigger && !decoder_pseudo_trigger) begin - pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx; - - instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000; - instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001; - instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100; - instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101; - instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110; - instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111; - - instr_lb <= 1'b0;//is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000; - instr_lh <= 1'b0;//is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001; - instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010; - instr_lbu <= 1'b0;//is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100; - instr_lhu <= 1'b0;//is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101; - - instr_sb <= 1'b0;//is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000; - instr_sh <= 1'b0;//is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001; - instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010; - - instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000; - instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010; - instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011; - instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100; - instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110; - instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111; - - instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; - instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; - instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; - - instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000; - instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000; - instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; - instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000; - instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000; - instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000; - instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; - instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; - instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000; - instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000; - - instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) || - (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS; - instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) || - (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64; - instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; - instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; - - instr_ecall_ebreak <= 1'b0;//((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || - //(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); - instr_fence <= 1'b0;//(mem_rdata_q[6:0] == 7'b0001111 && !mem_rdata_q[14:12]); - - instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; - instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; - instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; - instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER; - - is_slli_srli_srai <= is_alu_reg_imm && |{ - mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, - mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, - mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 - }; - - is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{ - mem_rdata_q[14:12] == 3'b000, - mem_rdata_q[14:12] == 3'b010, - mem_rdata_q[14:12] == 3'b011, - mem_rdata_q[14:12] == 3'b100, - mem_rdata_q[14:12] == 3'b110, - mem_rdata_q[14:12] == 3'b111 - }; - - is_sll_srl_sra <= is_alu_reg_reg && |{ - mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, - mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, - mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 - }; - - is_lui_auipc_jal_jalr_addi_add_sub <= 0; - is_compare <= 0; - - (* parallel_case *) - case (1'b1) - instr_jal: - decoded_imm <= decoded_imm_j; - |{instr_lui, instr_auipc}: - decoded_imm <= mem_rdata_q[31:12] << 12; - |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}: - decoded_imm <= $signed(mem_rdata_q[31:20]); - is_beq_bne_blt_bge_bltu_bgeu: - decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); - is_sb_sh_sw: - decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); - default: - decoded_imm <= 1'bx; - endcase - end - - if (!resetn) begin - is_beq_bne_blt_bge_bltu_bgeu <= 0; - is_compare <= 0; - - instr_beq <= 0; - instr_bne <= 0; - instr_blt <= 0; - instr_bge <= 0; - instr_bltu <= 0; - instr_bgeu <= 0; - - instr_addi <= 0; - instr_slti <= 0; - instr_sltiu <= 0; - instr_xori <= 0; - instr_ori <= 0; - instr_andi <= 0; - - instr_add <= 0; - instr_sub <= 0; - instr_sll <= 0; - instr_slt <= 0; - instr_sltu <= 0; - instr_xor <= 0; - instr_srl <= 0; - instr_sra <= 0; - instr_or <= 0; - instr_and <= 0; - - instr_fence <= 0; - end - end - - - // Main State Machine - - localparam cpu_state_trap = 8'b10000000; - localparam cpu_state_fetch = 8'b01000000; - localparam cpu_state_ld_rs1 = 8'b00100000; - localparam cpu_state_ld_rs2 = 8'b00010000; - localparam cpu_state_exec = 8'b00001000; - localparam cpu_state_shift = 8'b00000100; - localparam cpu_state_stmem = 8'b00000010; - localparam cpu_state_ldmem = 8'b00000001; - - reg [7:0] cpu_state; - reg [1:0] irq_state; - - `FORMAL_KEEP reg [127:0] dbg_ascii_state; - - always @* begin - dbg_ascii_state = ""; - if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap"; - if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch"; - if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1"; - if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2"; - if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec"; - if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift"; - if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem"; - if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; - end - - reg set_mem_do_rinst; - reg set_mem_do_rdata; - reg set_mem_do_wdata; - - reg latched_store; - reg latched_stalu; - reg latched_branch; - reg latched_compr; - reg latched_trace; - reg latched_is_lu; - reg latched_is_lh; - reg latched_is_lb; - reg [regindex_bits-1:0] latched_rd; - - reg [31:0] current_pc; - assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc; - - reg [3:0] pcpi_timeout_counter; - reg pcpi_timeout; - - reg [31:0] next_irq_pending; - reg do_waitirq; - - reg [31:0] alu_out, alu_out_q; - reg alu_out_0, alu_out_0_q; - reg alu_wait, alu_wait_2; - - reg [31:0] alu_add_sub; - reg [31:0] alu_shl, alu_shr; - reg alu_eq, alu_ltu, alu_lts; - - generate if (TWO_CYCLE_ALU) begin - always @(posedge clk) begin - alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; - alu_eq <= reg_op1 == reg_op2; - alu_lts <= $signed(reg_op1) < $signed(reg_op2); - alu_ltu <= reg_op1 < reg_op2; - alu_shl <= reg_op1 << reg_op2[4:0]; - alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; - end - end else begin - always @* begin - alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; - alu_eq = reg_op1 == reg_op2; - alu_lts = $signed(reg_op1) < $signed(reg_op2); - alu_ltu = reg_op1 < reg_op2; - alu_shl = reg_op1 << reg_op2[4:0]; - alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; - end - end endgenerate - - always @* begin - alu_out_0 = 'bx; - (* parallel_case, full_case *) - case (1'b1) - instr_beq: - alu_out_0 = alu_eq; - instr_bne: - alu_out_0 = !alu_eq; - instr_bge: - alu_out_0 = !alu_lts; - instr_bgeu: - alu_out_0 = !alu_ltu; - is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): - alu_out_0 = alu_lts; - is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): - alu_out_0 = alu_ltu; - endcase - - alu_out = 'bx; - (* parallel_case, full_case *) - case (1'b1) - is_lui_auipc_jal_jalr_addi_add_sub: - alu_out = alu_add_sub; - is_compare: - alu_out = alu_out_0; - instr_xori || instr_xor: - alu_out = reg_op1 ^ reg_op2; - instr_ori || instr_or: - alu_out = reg_op1 | reg_op2; - instr_andi || instr_and: - alu_out = reg_op1 & reg_op2; - BARREL_SHIFTER && (instr_sll || instr_slli): - alu_out = alu_shl; - BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): - alu_out = alu_shr; - endcase - - end - - reg clear_prefetched_high_word_q; - always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word; - - always @* begin - clear_prefetched_high_word = clear_prefetched_high_word_q; - if (!prefetched_high_word) - clear_prefetched_high_word = 0; - if (latched_branch || irq_state || !resetn) - clear_prefetched_high_word = COMPRESSED_ISA; - end - - reg cpuregs_write; - reg [31:0] cpuregs_wrdata; - reg [31:0] cpuregs_rs1; - reg [31:0] cpuregs_rs2; - reg [regindex_bits-1:0] decoded_rs; - - always @* begin - cpuregs_write = 0; - cpuregs_wrdata = 'bx; - - if (cpu_state == cpu_state_fetch) begin - (* parallel_case *) - case (1'b1) - latched_branch: begin - cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); - cpuregs_write = 1; - end - latched_store && !latched_branch: begin - cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; - cpuregs_write = 1; - end - ENABLE_IRQ && irq_state[0]: begin - cpuregs_wrdata = reg_next_pc | latched_compr; - cpuregs_write = 1; - end - ENABLE_IRQ && irq_state[1]: begin - cpuregs_wrdata = irq_pending & ~irq_mask; - cpuregs_write = 1; - end - endcase - end - end - -`ifndef PICORV32_REGS - always @(posedge clk) begin - if (resetn && cpuregs_write && latched_rd) -`ifdef PICORV32_TESTBUG_001 - cpuregs[latched_rd ^ 1] <= cpuregs_wrdata; -`elsif PICORV32_TESTBUG_002 - cpuregs[latched_rd] <= cpuregs_wrdata ^ 1; -`else - cpuregs[latched_rd] <= cpuregs_wrdata; -`endif - end - - always @* begin - decoded_rs = 'bx; - if (ENABLE_REGS_DUALPORT) begin - cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; - cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; - end else begin - decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; - cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; - cpuregs_rs2 = cpuregs_rs1; - end - end -`else - wire[31:0] cpuregs_rdata1; - wire[31:0] cpuregs_rdata2; - - wire [5:0] cpuregs_waddr = latched_rd; - wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; - wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; - - `PICORV32_REGS cpuregs ( - .clk(clk), - .wen(resetn && cpuregs_write && latched_rd), - .waddr(cpuregs_waddr), - .raddr1(cpuregs_raddr1), - .raddr2(cpuregs_raddr2), - .wdata(cpuregs_wrdata), - .rdata1(cpuregs_rdata1), - .rdata2(cpuregs_rdata2) - ); - - always @* begin - decoded_rs = 'bx; - if (ENABLE_REGS_DUALPORT) begin - cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; - cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; - end else begin - decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; - cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; - cpuregs_rs2 = cpuregs_rs1; - end - end -`endif - - assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask)); - - always @(posedge clk) begin - trap <= 0; - reg_sh <= 'bx; - reg_out <= 'bx; - set_mem_do_rinst = 0; - set_mem_do_rdata = 0; - set_mem_do_wdata = 0; - - alu_out_0_q <= alu_out_0; - alu_out_q <= alu_out; - - alu_wait <= 0; - alu_wait_2 <= 0; - - if (launch_next_insn) begin - dbg_rs1val <= 'bx; - dbg_rs2val <= 'bx; - dbg_rs1val_valid <= 0; - dbg_rs2val_valid <= 0; - end - - if (WITH_PCPI && CATCH_ILLINSN) begin - if (resetn && pcpi_valid && !pcpi_int_wait) begin - if (pcpi_timeout_counter) - pcpi_timeout_counter <= pcpi_timeout_counter - 1; - end else - pcpi_timeout_counter <= ~0; - pcpi_timeout <= !pcpi_timeout_counter; - end - - if (ENABLE_COUNTERS) begin - count_cycle <= resetn ? count_cycle + 1 : 0; - if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0; - end else begin - count_cycle <= 'bx; - count_instr <= 'bx; - end - - next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; - - if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin - timer <= timer - 1; - end - - decoder_trigger <= mem_do_rinst && mem_done; - decoder_trigger_q <= decoder_trigger; - decoder_pseudo_trigger <= 0; - decoder_pseudo_trigger_q <= decoder_pseudo_trigger; - do_waitirq <= 0; - - trace_valid <= 0; - - if (!ENABLE_TRACE) - trace_data <= 'bx; - - if (!resetn) begin - reg_pc <= PROGADDR_RESET; - reg_next_pc <= PROGADDR_RESET; - if (ENABLE_COUNTERS) - count_instr <= 0; - latched_store <= 0; - latched_stalu <= 0; - latched_branch <= 0; - latched_trace <= 0; - latched_is_lu <= 0; - latched_is_lh <= 0; - latched_is_lb <= 0; - pcpi_valid <= 0; - pcpi_timeout <= 0; - irq_active <= 0; - irq_delay <= 0; - irq_mask <= ~0; - next_irq_pending = 0; - irq_state <= 0; - eoi <= 0; - timer <= 0; - if (~STACKADDR) begin - latched_store <= 1; - latched_rd <= 2; - reg_out <= STACKADDR; - end - cpu_state <= cpu_state_fetch; - end else - (* parallel_case, full_case *) - case (cpu_state) - cpu_state_trap: begin - trap <= 1; - end - - cpu_state_fetch: begin - mem_do_rinst <= !decoder_trigger && !do_waitirq; - mem_wordsize <= 0; - - current_pc = reg_next_pc; - - (* parallel_case *) - case (1'b1) - latched_branch: begin - current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; - `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) - end - latched_store && !latched_branch: begin - `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) - end - ENABLE_IRQ && irq_state[0]: begin - current_pc = PROGADDR_IRQ; - irq_active <= 1; - mem_do_rinst <= 1; - end - ENABLE_IRQ && irq_state[1]: begin - eoi <= irq_pending & ~irq_mask; - next_irq_pending = next_irq_pending & irq_mask; - end - endcase - - if (ENABLE_TRACE && latched_trace) begin - latched_trace <= 0; - trace_valid <= 1; - if (latched_branch) - trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); - else - trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out); - end - - reg_pc <= current_pc; - reg_next_pc <= current_pc; - - latched_store <= 0; - latched_stalu <= 0; - latched_branch <= 0; - latched_is_lu <= 0; - latched_is_lh <= 0; - latched_is_lb <= 0; - latched_rd <= decoded_rd; - latched_compr <= compressed_instr; - - if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin - irq_state <= - irq_state == 2'b00 ? 2'b01 : - irq_state == 2'b01 ? 2'b10 : 2'b00; - latched_compr <= latched_compr; - if (ENABLE_IRQ_QREGS) - latched_rd <= irqregs_offset | irq_state[0]; - else - latched_rd <= irq_state[0] ? 4 : 3; - end else - if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin - if (irq_pending) begin - latched_store <= 1; - reg_out <= irq_pending; - reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); - mem_do_rinst <= 1; - end else - do_waitirq <= 1; - end else - if (decoder_trigger) begin - `debug($display("-- %-0t", $time);) - irq_delay <= irq_active; - reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); - if (ENABLE_TRACE) - latched_trace <= 1; - if (ENABLE_COUNTERS) begin - count_instr <= count_instr + 1; - if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0; - end - if (instr_jal) begin - mem_do_rinst <= 1; - reg_next_pc <= current_pc + decoded_imm_j; - latched_branch <= 1; - end else begin - mem_do_rinst <= 0; - mem_do_prefetch <= !instr_jalr && !instr_retirq; - cpu_state <= cpu_state_ld_rs1; - end - end - end - - cpu_state_ld_rs1: begin - reg_op1 <= 'bx; - reg_op2 <= 'bx; - - (* parallel_case *) - case (1'b1) - (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin - if (WITH_PCPI) begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_op1 <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - if (ENABLE_REGS_DUALPORT) begin - pcpi_valid <= 1; - `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) - reg_sh <= cpuregs_rs2; - reg_op2 <= cpuregs_rs2; - dbg_rs2val <= cpuregs_rs2; - dbg_rs2val_valid <= 1; - if (pcpi_int_ready) begin - mem_do_rinst <= 1; - pcpi_valid <= 0; - reg_out <= pcpi_int_rd; - latched_store <= pcpi_int_wr; - cpu_state <= cpu_state_fetch; - end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin - pcpi_valid <= 0; - `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin - next_irq_pending[irq_ebreak] = 1; - cpu_state <= cpu_state_fetch; - end else - cpu_state <= cpu_state_trap; - end - end else begin - cpu_state <= cpu_state_ld_rs2; - end - end else begin - `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin - next_irq_pending[irq_ebreak] = 1; - cpu_state <= cpu_state_fetch; - end else - cpu_state <= cpu_state_trap; - end - end - ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin - (* parallel_case, full_case *) - case (1'b1) - instr_rdcycle: - reg_out <= count_cycle[31:0]; - instr_rdcycleh && ENABLE_COUNTERS64: - reg_out <= count_cycle[63:32]; - instr_rdinstr: - reg_out <= count_instr[31:0]; - instr_rdinstrh && ENABLE_COUNTERS64: - reg_out <= count_instr[63:32]; - endcase - latched_store <= 1; - cpu_state <= cpu_state_fetch; - end - is_lui_auipc_jal: begin - reg_op1 <= instr_lui ? 0 : reg_pc; - reg_op2 <= decoded_imm; - if (TWO_CYCLE_ALU) - alu_wait <= 1; - else - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_exec; - end - ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_out <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - latched_store <= 1; - cpu_state <= cpu_state_fetch; - end - ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_out <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - latched_rd <= latched_rd | irqregs_offset; - latched_store <= 1; - cpu_state <= cpu_state_fetch; - end - ENABLE_IRQ && instr_retirq: begin - eoi <= 0; - irq_active <= 0; - latched_branch <= 1; - latched_store <= 1; - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - cpu_state <= cpu_state_fetch; - end - ENABLE_IRQ && instr_maskirq: begin - latched_store <= 1; - reg_out <= irq_mask; - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - irq_mask <= cpuregs_rs1 | MASKED_IRQ; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - cpu_state <= cpu_state_fetch; - end - ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin - latched_store <= 1; - reg_out <= timer; - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - timer <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - cpu_state <= cpu_state_fetch; - end - is_lb_lh_lw_lbu_lhu && !instr_trap: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_op1 <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - cpu_state <= cpu_state_ldmem; - mem_do_rinst <= 1; - end - is_slli_srli_srai && !BARREL_SHIFTER: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_op1 <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - reg_sh <= decoded_rs2; - cpu_state <= cpu_state_shift; - end - is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_op1 <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; - if (TWO_CYCLE_ALU) - alu_wait <= 1; - else - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_exec; - end - default: begin - `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_op1 <= cpuregs_rs1; - dbg_rs1val <= cpuregs_rs1; - dbg_rs1val_valid <= 1; - if (ENABLE_REGS_DUALPORT) begin - `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) - reg_sh <= cpuregs_rs2; - reg_op2 <= cpuregs_rs2; - dbg_rs2val <= cpuregs_rs2; - dbg_rs2val_valid <= 1; - (* parallel_case *) - case (1'b1) - is_sb_sh_sw: begin - cpu_state <= cpu_state_stmem; - mem_do_rinst <= 1; - end - is_sll_srl_sra && !BARREL_SHIFTER: begin - cpu_state <= cpu_state_shift; - end - default: begin - if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin - alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); - alu_wait <= 1; - end else - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_exec; - end - endcase - end else - cpu_state <= cpu_state_ld_rs2; - end - endcase - end - - cpu_state_ld_rs2: begin - `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) - reg_sh <= cpuregs_rs2; - reg_op2 <= cpuregs_rs2; - dbg_rs2val <= cpuregs_rs2; - dbg_rs2val_valid <= 1; - - (* parallel_case *) - case (1'b1) - WITH_PCPI && instr_trap: begin - pcpi_valid <= 1; - if (pcpi_int_ready) begin - mem_do_rinst <= 1; - pcpi_valid <= 0; - reg_out <= pcpi_int_rd; - latched_store <= pcpi_int_wr; - cpu_state <= cpu_state_fetch; - end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin - pcpi_valid <= 0; - `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin - next_irq_pending[irq_ebreak] = 1; - cpu_state <= cpu_state_fetch; - end else - cpu_state <= cpu_state_trap; - end - end - is_sb_sh_sw: begin - cpu_state <= cpu_state_stmem; - mem_do_rinst <= 1; - end - is_sll_srl_sra && !BARREL_SHIFTER: begin - cpu_state <= cpu_state_shift; - end - default: begin - if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin - alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); - alu_wait <= 1; - end else - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_exec; - end - endcase - end - - cpu_state_exec: begin - reg_out <= reg_pc + decoded_imm; - if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin - mem_do_rinst <= mem_do_prefetch && !alu_wait_2; - alu_wait <= alu_wait_2; - end else - if (is_beq_bne_blt_bge_bltu_bgeu) begin - latched_rd <= 0; - latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; - latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; - if (mem_done) - cpu_state <= cpu_state_fetch; - if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin - decoder_trigger <= 0; - set_mem_do_rinst = 1; - end - end else begin - latched_branch <= instr_jalr; - latched_store <= 1; - latched_stalu <= 1; - cpu_state <= cpu_state_fetch; - end - end - - cpu_state_shift: begin - latched_store <= 1; - if (reg_sh == 0) begin - reg_out <= reg_op1; - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_fetch; - end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin - (* parallel_case, full_case *) - case (1'b1) - instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; - instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4; - instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4; - endcase - reg_sh <= reg_sh - 4; - end else begin - (* parallel_case, full_case *) - case (1'b1) - instr_slli || instr_sll: reg_op1 <= reg_op1 << 1; - instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1; - instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1; - endcase - reg_sh <= reg_sh - 1; - end - end - - cpu_state_stmem: begin - if (ENABLE_TRACE) - reg_out <= reg_op2; - if (!mem_do_prefetch || mem_done) begin - if (!mem_do_wdata) begin - (* parallel_case, full_case *) - case (1'b1) - instr_sb: mem_wordsize <= 2; - instr_sh: mem_wordsize <= 1; - instr_sw: mem_wordsize <= 0; - endcase - if (ENABLE_TRACE) begin - trace_valid <= 1; - trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); - end - reg_op1 <= reg_op1 + decoded_imm; - set_mem_do_wdata = 1; - end - if (!mem_do_prefetch && mem_done) begin - cpu_state <= cpu_state_fetch; - decoder_trigger <= 1; - decoder_pseudo_trigger <= 1; - end - end - end - - cpu_state_ldmem: begin - latched_store <= 1; - if (!mem_do_prefetch || mem_done) begin - if (!mem_do_rdata) begin - (* parallel_case, full_case *) - case (1'b1) - instr_lb || instr_lbu: mem_wordsize <= 2; - instr_lh || instr_lhu: mem_wordsize <= 1; - instr_lw: mem_wordsize <= 0; - endcase - latched_is_lu <= is_lbu_lhu_lw; - latched_is_lh <= instr_lh; - latched_is_lb <= instr_lb; - if (ENABLE_TRACE) begin - trace_valid <= 1; - trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); - end - reg_op1 <= reg_op1 + decoded_imm; - set_mem_do_rdata = 1; - end - if (!mem_do_prefetch && mem_done) begin - (* parallel_case, full_case *) - case (1'b1) - latched_is_lu: reg_out <= mem_rdata_word; - latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]); - latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]); - endcase - decoder_trigger <= 1; - decoder_pseudo_trigger <= 1; - cpu_state <= cpu_state_fetch; - end - end - end - endcase - - if (ENABLE_IRQ) begin - next_irq_pending = next_irq_pending | irq; - if(ENABLE_IRQ_TIMER && timer) - if (timer - 1 == 0) - next_irq_pending[irq_timer] = 1; - end - - if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin - if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin - `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) - if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin - next_irq_pending[irq_buserror] = 1; - end else - cpu_state <= cpu_state_trap; - end - if (mem_wordsize == 1 && reg_op1[0] != 0) begin - `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) - if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin - next_irq_pending[irq_buserror] = 1; - end else - cpu_state <= cpu_state_trap; - end - end - if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin - `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin - next_irq_pending[irq_buserror] = 1; - end else - cpu_state <= cpu_state_trap; - end - if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin - cpu_state <= cpu_state_trap; - end - - if (!resetn || mem_done) begin - mem_do_prefetch <= 0; - mem_do_rinst <= 0; - mem_do_rdata <= 0; - mem_do_wdata <= 0; - end - - if (set_mem_do_rinst) - mem_do_rinst <= 1; - if (set_mem_do_rdata) - mem_do_rdata <= 1; - if (set_mem_do_wdata) - mem_do_wdata <= 1; - - irq_pending <= next_irq_pending & ~MASKED_IRQ; - - if (!CATCH_MISALIGN) begin - if (COMPRESSED_ISA) begin - reg_pc[0] <= 0; - reg_next_pc[0] <= 0; - end else begin - reg_pc[1:0] <= 0; - reg_next_pc[1:0] <= 0; - end - end - current_pc = 'bx; - end - -endmodule - -// This is a simple example implementation of PICORV32_REGS. -// Use the PICORV32_REGS mechanism if you want to use custom -// memory resources to implement the processor register file. -// Note that your implementation must match the requirements of -// the PicoRV32 configuration. (e.g. QREGS, etc) -module picorv32_regs ( - input clk, wen, - input [5:0] waddr, - input [5:0] raddr1, - input [5:0] raddr2, - input [31:0] wdata, - output [31:0] rdata1, - output [31:0] rdata2 -); - reg [31:0] regs [0:30]; - - always @(posedge clk) - if (wen) regs[~waddr[4:0]] <= wdata; - - assign rdata1 = regs[~raddr1[4:0]]; - assign rdata2 = regs[~raddr2[4:0]]; -endmodule - - -/*************************************************************** - * picorv32_pcpi_mul - ***************************************************************/ - -module picorv32_pcpi_mul #( - parameter STEPS_AT_ONCE = 1, - parameter CARRY_CHAIN = 4 -) ( - input clk, resetn, - - input pcpi_valid, - input [31:0] pcpi_insn, - input [31:0] pcpi_rs1, - input [31:0] pcpi_rs2, - output reg pcpi_wr, - output reg [31:0] pcpi_rd, - output reg pcpi_wait, - output reg pcpi_ready -); - reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; - wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; - wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; - wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; - wire instr_rs2_signed = |{instr_mulh}; - - reg pcpi_wait_q; - wire mul_start = pcpi_wait && !pcpi_wait_q; - - always @(posedge clk) begin - instr_mul <= 0; - instr_mulh <= 0; - instr_mulhsu <= 0; - instr_mulhu <= 0; - - if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin - case (pcpi_insn[14:12]) - 3'b000: instr_mul <= 1; - 3'b001: instr_mulh <= 1; - 3'b010: instr_mulhsu <= 1; - 3'b011: instr_mulhu <= 1; - endcase - end - - pcpi_wait <= instr_any_mul; - pcpi_wait_q <= pcpi_wait; - end - - reg [63:0] rs1, rs2, rd, rdx; - reg [63:0] next_rs1, next_rs2, this_rs2; - reg [63:0] next_rd, next_rdx, next_rdt; - reg [6:0] mul_counter; - reg mul_waiting; - reg mul_finish; - integer i, j; - - // carry save accumulator - always @* begin - next_rd = rd; - next_rdx = rdx; - next_rs1 = rs1; - next_rs2 = rs2; - - for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin - this_rs2 = next_rs1[0] ? next_rs2 : 0; - if (CARRY_CHAIN == 0) begin - next_rdt = next_rd ^ next_rdx ^ this_rs2; - next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1; - next_rd = next_rdt; - end else begin - next_rdt = 0; - for (j = 0; j < 64; j = j + CARRY_CHAIN) - {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} = - next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN]; - next_rdx = next_rdt << 1; - end - next_rs1 = next_rs1 >> 1; - next_rs2 = next_rs2 << 1; - end - end - - always @(posedge clk) begin - mul_finish <= 0; - if (!resetn) begin - mul_waiting <= 1; - end else - if (mul_waiting) begin - if (instr_rs1_signed) - rs1 <= $signed(pcpi_rs1); - else - rs1 <= $unsigned(pcpi_rs1); - - if (instr_rs2_signed) - rs2 <= $signed(pcpi_rs2); - else - rs2 <= $unsigned(pcpi_rs2); - - rd <= 0; - rdx <= 0; - mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE); - mul_waiting <= !mul_start; - end else begin - rd <= next_rd; - rdx <= next_rdx; - rs1 <= next_rs1; - rs2 <= next_rs2; - - mul_counter <= mul_counter - STEPS_AT_ONCE; - if (mul_counter[6]) begin - mul_finish <= 1; - mul_waiting <= 1; - end - end - end - - always @(posedge clk) begin - pcpi_wr <= 0; - pcpi_ready <= 0; - if (mul_finish && resetn) begin - pcpi_wr <= 1; - pcpi_ready <= 1; - pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; - end - end -endmodule - -module picorv32_pcpi_fast_mul #( - parameter EXTRA_MUL_FFS = 0, - parameter EXTRA_INSN_FFS = 0, - parameter MUL_CLKGATE = 0 -) ( - input clk, resetn, - - input pcpi_valid, - input [31:0] pcpi_insn, - input [31:0] pcpi_rs1, - input [31:0] pcpi_rs2, - output pcpi_wr, - output [31:0] pcpi_rd, - output pcpi_wait, - output pcpi_ready -); - reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; - wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; - wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; - wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; - wire instr_rs2_signed = |{instr_mulh}; - - reg shift_out; - reg [3:0] active; - reg [32:0] rs1, rs2, rs1_q, rs2_q; - reg [63:0] rd, rd_q; - - wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001; - reg pcpi_insn_valid_q; - - always @* begin - instr_mul = 0; - instr_mulh = 0; - instr_mulhsu = 0; - instr_mulhu = 0; - - if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin - case (pcpi_insn[14:12]) - 3'b000: instr_mul = 1; - 3'b001: instr_mulh = 1; - 3'b010: instr_mulhsu = 1; - 3'b011: instr_mulhu = 1; - endcase - end - end - - always @(posedge clk) begin - pcpi_insn_valid_q <= pcpi_insn_valid; - if (!MUL_CLKGATE || active[0]) begin - rs1_q <= rs1; - rs2_q <= rs2; - end - if (!MUL_CLKGATE || active[1]) begin - rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2); - end - if (!MUL_CLKGATE || active[2]) begin - rd_q <= rd; - end - end - - always @(posedge clk) begin - if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin - if (instr_rs1_signed) - rs1 <= $signed(pcpi_rs1); - else - rs1 <= $unsigned(pcpi_rs1); - - if (instr_rs2_signed) - rs2 <= $signed(pcpi_rs2); - else - rs2 <= $unsigned(pcpi_rs2); - active[0] <= 1; - end else begin - active[0] <= 0; - end - - active[3:1] <= active; - shift_out <= instr_any_mulh; - - if (!resetn) - active <= 0; - end - - assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; - assign pcpi_wait = 0; - assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; -`ifdef RISCV_FORMAL_ALTOPS - assign pcpi_rd = - instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e : - instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 : - instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 : - instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx; -`else - assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); -`endif -endmodule - - -/*************************************************************** - * picorv32_pcpi_div - ***************************************************************/ - -module picorv32_pcpi_div ( - input clk, resetn, - - input pcpi_valid, - input [31:0] pcpi_insn, - input [31:0] pcpi_rs1, - input [31:0] pcpi_rs2, - output reg pcpi_wr, - output reg [31:0] pcpi_rd, - output reg pcpi_wait, - output reg pcpi_ready -); - reg instr_div, instr_divu, instr_rem, instr_remu; - wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu}; - - reg pcpi_wait_q; - wire start = pcpi_wait && !pcpi_wait_q; - - always @(posedge clk) begin - instr_div <= 0; - instr_divu <= 0; - instr_rem <= 0; - instr_remu <= 0; - - if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin - case (pcpi_insn[14:12]) - 3'b100: instr_div <= 1; - 3'b101: instr_divu <= 1; - 3'b110: instr_rem <= 1; - 3'b111: instr_remu <= 1; - endcase - end - - pcpi_wait <= instr_any_div_rem && resetn; - pcpi_wait_q <= pcpi_wait && resetn; - end - - reg [31:0] dividend; - reg [62:0] divisor; - reg [31:0] quotient; - reg [31:0] quotient_msk; - reg running; - reg outsign; - - always @(posedge clk) begin - pcpi_ready <= 0; - pcpi_wr <= 0; - pcpi_rd <= 'bx; - - if (!resetn) begin - running <= 0; - end else - if (start) begin - running <= 1; - dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; - divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; - outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); - quotient <= 0; - quotient_msk <= 1 << 31; - end else - if (!quotient_msk && running) begin - running <= 0; - pcpi_ready <= 1; - pcpi_wr <= 1; -`ifdef RISCV_FORMAL_ALTOPS - case (1) - instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec; - instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70; - instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5; - instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1; - endcase -`else - if (instr_div || instr_divu) - pcpi_rd <= outsign ? -quotient : quotient; - else - pcpi_rd <= outsign ? -dividend : dividend; -`endif - end else begin - if (divisor <= dividend) begin - dividend <= dividend - divisor; - quotient <= quotient | quotient_msk; - end - divisor <= divisor >> 1; -`ifdef RISCV_FORMAL_ALTOPS - quotient_msk <= quotient_msk >> 5; -`else - quotient_msk <= quotient_msk >> 1; -`endif - end - end -endmodule - -module picosoc_regs ( - input clk, wen, - input [5:0] waddr, - input [5:0] raddr1, - input [5:0] raddr2, - input [31:0] wdata, - output [31:0] rdata1, - output [31:0] rdata2 -); - reg [31:0] regs [0:31]; - - always @(posedge clk) - if (wen) regs[waddr[4:0]] <= wdata; - - assign rdata1 = regs[raddr1[4:0]]; - assign rdata2 = regs[raddr2[4:0]]; -endmodule - diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala deleted file mode 100644 index cce410f..0000000 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ /dev/null @@ -1,647 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - - -class FSMC_Port_Bundle extends Bundle{ - - val ADIn = Input(UInt(16.W)) - val ADOut = Output(UInt(16.W)) - val ADOEn = Output(Bool()) - val csn = Input(Bool()) - val rdn = Input(Bool()) - val wrn = Input(Bool()) - val advn = Input(Bool()) -} - -class LVDS_MST_Bundle extends Bundle{ - val frame_info_update_en = Output(Bool()) - val slave_type_num = Output(UInt(8.W)) - val slave_data_length = Output(UInt(8.W)) - val tx_start = Output(Bool()) - - val slave_link_num_valid = Input(Bool()) - val slave_link_num = Input(UInt(7.W)) - - val downstream_busy = Input(Bool()) - val upstream_crc_valid = Input(Bool()) - - val closed_loop_err = Input(Bool()) - val link_err_location = Input(UInt(7.W)) - - val upstream_cdr_err = Input(Bool()) - val upstream_crc_err = Input(Bool()) - - val tx_data_ready = Input(Bool()) - val tx_data_in = Output(UInt(8.W)) - val rx_data_valid = Input(Bool()) - val rx_data_out = Input(UInt(8.W)) -} - - - -class BackBoardMstIO extends Bundle{ - val FSMC = new FSMC_Port_Bundle - - val oser_pclk = Input(Bool()) //10M - val oser_fclk = Input(Bool()) //50M - val ides_pclk = Input(Bool()) //100M - val ides_fclk = Input(Bool()) //400M - - - val interrupt = Output(Bool()) - - val testIO = Input(Bool()) - - val lvdsMst = new LVDS_MST_Bundle - -} - -class BackBoardMstBase extends Module{ //10M - - def OPERATORADDR = 0.U - def STATUSINITADDR = 1.U - def STATUSSYNCHADDR = 2.U - def STATUSTRANSADDR = 3.U - def STATUSUNICASTADDR = 4.U - def SLVNUMADDR = 5.U - def SLVDATALENADDR = 6.U - def SLVLINKNUMADDR = 7.U - def LINKERRLOCADDR = 8.U - def STATUSLINKERRADDR = 9.U - def STATUSCDRERRADDR = 10.U - def STATUSCRCERRADDR = 11.U - - - val io: BackBoardMstIO = IO(new BackBoardMstIO) - - val mirrorDown = Module(new MirrorSRAMDP()) - val mirrorUp = Module(new MirrorSRAMDP()) - val mirrorReg = Module(new MirrorSRAMDP()) - - mirrorReg.io.addrB := DontCare - mirrorReg.io.datawB := DontCare - mirrorReg.io.enwB := false.B - mirrorReg.io.enrB := false.B - - assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) ) - assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) ) - - val ctrlTransmit = RegInit( false.B ) - val ctrlUnicast = RegInit( false.B ) - val ctrlSynch = RegInit( false.B ) - val ctrlInit = RegInit( false.B ) - - val slvNum = RegInit(0.U(6.W)) - val interrupt = RegInit(false.B); io.interrupt := interrupt - val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1 - - - - - - mirrorDown.io.clockA := io.ides_pclk.asBool //100M - mirrorDown.io.clockB := io.oser_pclk.asBool - - mirrorUp.io.clockA := io.ides_pclk.asBool //100M - mirrorUp.io.clockB := io.oser_pclk.asBool - - mirrorReg.io.clockA := io.ides_pclk.asBool //100M - mirrorReg.io.clockB := io.oser_pclk.asBool //10M - - when(interrupt === true.B){ - interrupt := false.B - } - - -} - - - - -trait BackBoardMstFSMC{ this: BackBoardMstBase => - - withClockAndReset( io.ides_pclk.asClock, reset ){//100M - - io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn - - val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn) - - val isAccessSRAM = ~latchAddr.extract(11) - val isAccessReg = latchAddr.extract(11) - val isAccessDown = ~latchAddr.extract(10) - val activeAddr = latchAddr(9,0) - - mirrorDown.io.addrA := activeAddr - mirrorDown.io.datawA := io.FSMC.ADIn - mirrorDown.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown - mirrorDown.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown - - mirrorUp.io.addrA := activeAddr - mirrorUp.io.datawA := io.FSMC.ADIn - mirrorUp.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown - mirrorUp.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown - - mirrorReg.io.addrA := activeAddr - mirrorReg.io.datawA := io.FSMC.ADIn - mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn - mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn - - io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) ) - - - } - - //10M - val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B) - when(~testIOShift(0) & io.testIO){ - - mirrorReg.io.addrB := OPERATORADDR - mirrorReg.io.enrB := true.B - } .elsewhen( ~testIOShift(1) & testIOShift(0)){ - when( mirrorReg.io.datarB === 0.U ){ - ctrlInit := true.B - } - - when( mirrorReg.io.datarB === 1.U ){ - ctrlSynch := true.B - } - - when( mirrorReg.io.datarB === 5.U ){ - ctrlTransmit := true.B - } - - when( mirrorReg.io.datarB === 6.U ){ - ctrlUnicast := true.B - } - } - -} - -abstract class BackBoardMstLVDSBase extends BackBoardMstBase -with BackBoardMstFSMC -{ - - - val frame_info_update_en = RegInit(false.B) - val slave_type_num = RegInit(0.U(8.W)) - - val tx_start = RegInit(false.B) - - io.lvdsMst.frame_info_update_en := frame_info_update_en - io.lvdsMst.slave_type_num := slave_type_num - io.lvdsMst.slave_data_length := slaveDataLength - io.lvdsMst.tx_start := tx_start - - val stateCur = RegInit(15.U(4.W)) - - -} - - -trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase => - - val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit - val timeoutCnt = Reg(UInt(13.W)) - - when(ctrlInit){ - when( isInitStart ){ - - stateCur := 0.U - frame_info_update_en := false.B - slave_type_num := 0.U - tx_start := false.B - - } .elsewhen( stateCur === 0.U ){ - stateCur := 1.U - - // write statusInit - mirrorReg.io.addrB := STATUSINITADDR - mirrorReg.io.datawB := 0.U - mirrorReg.io.enwB := true.B - } .elsewhen( stateCur === 1.U ){ - stateCur := 2.U - - //req slvnum - mirrorReg.io.addrB := SLVNUMADDR - mirrorReg.io.enrB := true.B - - } .elsewhen( stateCur === 2.U ){ - stateCur := 3.U - - //lock slvNum - slvNum := mirrorReg.io.datarB - - //req slaveDataLength - mirrorReg.io.addrB := SLVDATALENADDR - mirrorReg.io.enrB := true.B - - } - .elsewhen( stateCur === 3.U ){ - stateCur := 4.U - - //lock slaveDataLength - slaveDataLength := mirrorReg.io.datarB - - frame_info_update_en := true.B - slave_type_num := Cat( "b00".U(2.W), slvNum ) - - tx_start := false.B - } .elsewhen( stateCur === 4.U ){ // tx start - stateCur := 5.U - timeoutCnt := 0.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 5.U ){ - tx_start := false.B - timeoutCnt := timeoutCnt + 1.U - - when( io.lvdsMst.slave_link_num_valid ){ - stateCur := 6.U - - //linkNum - mirrorReg.io.addrB := SLVLINKNUMADDR - mirrorReg.io.datawB := io.lvdsMst.slave_link_num - mirrorReg.io.enwB := true.B - - } - - when( timeoutCnt === 6000.U ){ - stateCur := 6.U - - //linkNum - mirrorReg.io.addrB := SLVLINKNUMADDR - mirrorReg.io.datawB := 0.U - mirrorReg.io.enwB := true.B - - } - - - - } .elsewhen( stateCur === 6.U ){ - stateCur := 7.U - - //statusInit - mirrorReg.io.addrB := STATUSINITADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlInit := false.B - ctrlSynch := false.B - ctrlTransmit := false.B - ctrlUnicast := false.B - interrupt := true.B - - } .elsewhen( stateCur === 7.U ){ - - } - } -} - -trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase => - val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch - - when( ctrlSynch ){ - when( isSyncStart ){ - stateCur := 0.U - frame_info_update_en := false.B - slave_type_num := 0.U - tx_start := false.B - - } .elsewhen( stateCur === 0.U ){ //statusSynch - stateCur := 1.U - - mirrorReg.io.addrB := STATUSSYNCHADDR - mirrorReg.io.datawB := 0.U - mirrorReg.io.enwB := true.B - } .elsewhen( stateCur === 1.U ){ - stateCur := 2.U - - //req slvnum - mirrorReg.io.addrB := SLVNUMADDR - mirrorReg.io.enrB := true.B - - - } .elsewhen( stateCur === 2.U ){ //slaveDataLength - stateCur := 3.U - - //lock slvNum - slvNum := mirrorReg.io.datarB - - //slaveDataLength - mirrorReg.io.addrB := SLVDATALENADDR - mirrorReg.io.enrB := true.B - - - } .elsewhen( stateCur === 3.U ){ - stateCur := 4.U - - //lock slaveDataLength - slaveDataLength := mirrorReg.io.datarB - - frame_info_update_en := true.B - slave_type_num := Cat( "b01".U(2.W), slvNum ) - - tx_start := false.B - } .elsewhen( stateCur === 4.U ){ // tx start - stateCur := 5.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 5.U ){ - - tx_start := false.B - - when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ - stateCur := 6.U - - //statusSync - mirrorReg.io.addrB := STATUSSYNCHADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlSynch := false.B - interrupt := true.B - } - - } .otherwise{ - - } - } - -} - - -trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase => - - val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B) - - when(ctrlTransmit){ - when( isTransStart ){ //reset - stateCur := 0.U - - frame_info_update_en := false.B - slave_type_num := 0.U - - tx_start := false.B - - - } .elsewhen( stateCur === 0.U ){ //statusTransmit - stateCur := 1.U - - mirrorReg.io.addrB := STATUSTRANSADDR - mirrorReg.io.datawB := 0.U - mirrorReg.io.enwB := true.B - } .elsewhen( stateCur === 1.U ){ //slvnum - stateCur := 2.U - - mirrorReg.io.addrB := SLVNUMADDR - mirrorReg.io.enrB := true.B - - } .elsewhen( stateCur === 2.U ){ //slaveDataLength - stateCur := 3.U - - //lock slvNum - slvNum := mirrorReg.io.datarB - - mirrorReg.io.addrB := SLVDATALENADDR - mirrorReg.io.enrB := true.B - - } .elsewhen( stateCur === 3.U ){ //setting - stateCur := 4.U - - //lock slaveDataLength - slaveDataLength := mirrorReg.io.datarB - - frame_info_update_en := true.B - slave_type_num := Cat( "b10".U(2.W), slvNum ) - - tx_start := false.B - } .elsewhen( stateCur === 4.U ){ // tx start - stateCur := 5.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 5.U ){ //waiting for busy drop - - tx_start := false.B - - when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ - stateCur := 6.U - } - - } .elsewhen( stateCur === 6.U ){ - when( io.lvdsMst.upstream_crc_valid ){ - stateCur := 7.U - - when( io.lvdsMst.upstream_crc_err ){ - mirrorReg.io.addrB := STATUSCRCERRADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - } - } - } .elsewhen( stateCur === 7.U ){ - stateCur := 8.U - - //statusTransmit - mirrorReg.io.addrB := STATUSTRANSADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlTransmit := false.B - interrupt := true.B - }.elsewhen( stateCur === 8.U ){ - - } .otherwise{ - - } - } - - - - -} - -trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase => - - val isUnicast = ctrlUnicast & ~RegNext(ctrlUnicast, false.B) - - when(ctrlUnicast){ - when( isUnicast ){ //reset - stateCur := 0.U - - frame_info_update_en := false.B - slave_type_num := 0.U - - tx_start := false.B - - - } .elsewhen( stateCur === 0.U ){ //statusUnicast - stateCur := 1.U - - mirrorReg.io.addrB := STATUSUNICASTADDR - mirrorReg.io.datawB := 0.U - mirrorReg.io.enwB := true.B - } .elsewhen( stateCur === 1.U ){ //slvnum - stateCur := 2.U - - mirrorReg.io.addrB := SLVNUMADDR - mirrorReg.io.enrB := true.B - - } .elsewhen( stateCur === 2.U ){ //slaveDataLength - stateCur := 3.U - - //lock slvNum - slvNum := mirrorReg.io.datarB - - mirrorReg.io.addrB := SLVDATALENADDR - mirrorReg.io.enrB := true.B - - } .elsewhen( stateCur === 3.U ){ //setting - stateCur := 4.U - - //lock slaveDataLength - slaveDataLength := mirrorReg.io.datarB - - frame_info_update_en := true.B - slave_type_num := Cat( "b11".U(2.W), slvNum ) - - tx_start := false.B - } .elsewhen( stateCur === 4.U ){ // tx start - stateCur := 5.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 5.U ){ //waiting for busy drop - - tx_start := false.B - - when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){ - stateCur := 6.U - } - - } .elsewhen( stateCur === 6.U ){ - when( io.lvdsMst.upstream_crc_valid ){ - stateCur := 7.U - - when( io.lvdsMst.upstream_crc_err ){ - mirrorReg.io.addrB := STATUSCRCERRADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - } - - } - } .elsewhen( stateCur === 7.U ){ - stateCur := 8.U - - //statusUnicast - mirrorReg.io.addrB := STATUSUNICASTADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlUnicast := false.B - interrupt := true.B - - } .elsewhen( stateCur === 8.U ){ - - } .otherwise{ - - } - } - -} - - -trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => - val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B ) - when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){ - mirrorReg.io.addrB := LINKERRLOCADDR - mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0) - mirrorReg.io.enwB := true.B - - } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){ - mirrorReg.io.addrB := STATUSLINKERRADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - } .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){ - mirrorReg.io.addrB := STATUSSYNCHADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlSynch := false.B - - } .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){ - mirrorReg.io.addrB := STATUSTRANSADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlTransmit := false.B - - } .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){ - mirrorReg.io.addrB := STATUSUNICASTADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - - ctrlUnicast := false.B - } .elsewhen( ~shiftClosedLoopErr(5) & shiftClosedLoopErr(4) ){ - interrupt := true.B - } - - - - val shiftCDRErr = ShiftRegisters( io.lvdsMst.upstream_cdr_err, 2, false.B, true.B ) - when( ~shiftCDRErr(0) & io.lvdsMst.upstream_cdr_err ){ - mirrorReg.io.addrB := STATUSCDRERRADDR - mirrorReg.io.datawB := 1.U - mirrorReg.io.enwB := true.B - interrupt := true.B - } - -} - -class BackBoardMst extends BackBoardMstLVDSBase -with BackBoardMstLVDSInit -with BackBoardMstLVDSSync -with BackBoardMstLVDSTransmit -with BackBoardMstLVDSUnicast -with BackBoardMstLVDSError{ - - val addrr = RegInit(0.U(11.W)) - val addrw = RegInit(0.U(11.W)) - - when( isTransStart | isUnicast ){ - addrw := 0.U - } .elsewhen( io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){ - assert( (stateCur === 5.U) || (stateCur === 6.U) ) - addrw := addrw + 1.U - } - - when( isTransStart | isUnicast ){ - addrr := 0.U - } .elsewhen( io.lvdsMst.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){ - addrr := addrr + 1.U - } - - mirrorDown.io.enwB := false.B - mirrorDown.io.datawB := 0.U - mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast) - io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ) - mirrorDown.io.addrB := addrr >> 1 - - - val rxData_lsb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) ) - mirrorUp.io.enrB := false.B - mirrorUp.io.enwB := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0) - mirrorUp.io.datawB := Cat( io.lvdsMst.rx_data_out, rxData_lsb ) - mirrorUp.io.addrB := addrw >> 1 - -} diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala deleted file mode 100644 index 6ae0c7e..0000000 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ /dev/null @@ -1,86 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class LVDS_SLV_Bundle extends Bundle{ - val downstream_rx_data_valid = Input(Bool()) - val downstream_rx_data_out = Input(UInt(8.W)) - val downstream_rx_crc_valid = Input(Bool()) - val downstream_rx_crc_err = Input(Bool()) - val upstream_tx_data_in = Output(UInt(8.W)) - val upstream_tx_data_ready = Input(Bool()) - - val downstream_rx_cdr_err = Input(Bool()) - val upstream_rx_cdr_err = Input(Bool()) -} - - -class BackBoardSlvIO extends Bundle{ - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) - - val DCIn = Input(Bool()) - - val lvdsSlv = new LVDS_SLV_Bundle -} - - -abstract class BackBoardSlvBase extends Module{ - val io: BackBoardSlvIO = IO(new BackBoardSlvIO) - - val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) - val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) -} - - -trait BackBoardSlvDown{ this: BackBoardSlvBase => - - - val downCnt = Reg(UInt(6.W)) - - - when( io.lvdsSlv.downstream_rx_data_valid ){ - downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out - downCnt := downCnt + 1.U - } .otherwise{ - downCnt := 0.U - } - - val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err - - // when( io.lvdsSlv.downstream_rx_crc_valid ){ - // when( ~io.lvdsSlv.downstream_rx_crc_err ){ - // for( i <- 1 until 32 ) { - // downReg(i) := downRegTemp(i) - // } - // } - // } - - // when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){ - // for( i <- 1 until 32 ) { - // downReg(i) := downRegTemp(i) - // } - // } - -} -trait BackBoardSlvUp{ this: BackBoardSlvBase => - - val upCnt = Reg(UInt(6.W)) - - io.lvdsSlv.upstream_tx_data_in := upReg(upCnt) - - when( io.lvdsSlv.upstream_tx_data_ready ){ - when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){ - upCnt := 0.U - } .otherwise{ - upCnt := upCnt + 1.U - } - } - - -} - - - diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala deleted file mode 100644 index 74421c7..0000000 --- a/src/main/scala/backBoard/DIn16.scala +++ /dev/null @@ -1,139 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -trait BackBoardSlvIn16 { this: BackBoardSlvLocal => - - val inPin = Wire(UInt(16.W)) - - - val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) - val flitTrigger = Wire(Vec(9, Bool())) - val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 2.U(8.W) ) } - val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) } - - - flitTrigger(0) := ~RegNext(flitTrigger(0)) - - flitTrigger(1) := flitCnt(1) === 15.U - when( ~RegNext(usTrigger) & usTrigger ){ - flitCnt(1) := flitCnt(1) + 1.U - } - - flitTrigger(2) := flitCnt(2) - when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){ - flitCnt(2) := ~flitCnt(2) - } - - flitTrigger(3) := flitCnt(3) - when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){ - flitCnt(3) := ~flitCnt(3) - } - - flitTrigger(4) := flitCnt(4) - when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){ - flitCnt(4) := ~flitCnt(4) - } - - flitTrigger(5) := flitCnt(5) - when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){ - flitCnt(5) := ~flitCnt(5) - } - - flitTrigger(6) := flitCnt(6) - when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){ - flitCnt(6) := ~flitCnt(6) - } - - flitTrigger(7) := flitCnt(7) - when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){ - flitCnt(7) := ~flitCnt(7) - } - - flitTrigger(8) := flitCnt(8) - when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){ - flitCnt(8) := ~flitCnt(8) - } - - - - - - - for( i <- 0 until 8 ) { - for( j <- 0 until 2 ) { - val flitter = RegInit(VecInit( Seq.fill(16){false.B})) - val flitHi = RegInit(0.U((log2Ceil(16)).W)) - val shiftIn = RegNext( inPin(i+8*j) ) - - val sample = - Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1), - Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2), - Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3), - Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4), - Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5), - Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6), - Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7), - Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B - )))))))) - - - when( sample ){ - flitter(0) := shiftIn - (1 until 16).map{ k => - flitter(k) := flitter(k-1) - } - - when( ~flitter(15) & flitter(0) ){ - flitHi := flitHi + 1.U - } .elsewhen( flitter(15) & ~flitter(0) ){ - flitHi := flitHi - 1.U - } - - when( flitHi === 12.U ){ - digitalIn(j)(i) := true.B - } .elsewhen( flitHi === 3.U ){ - digitalIn(j)(i) := false.B - } - - // val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) ) - - // assert( flitHi <= 15.U ) - // assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi ) - - } - } - } - -} - - - - -class DIn16 extends BackBoardSlvLocal -with BackBoardSlvStatusPR -with BackBoardSlvIn16{ - - val in = IO(Input(UInt(16.W))) - - inPin := in - - - when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ - digitalFilter(0) := downRegTemp(4) - digitalFilter(1) := downRegTemp(5) - } - - val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) } - - when( statusPage === 0.U ){ - upReg(2) := digitalInSync(0) - upReg(3) := digitalInSync(1) - upReg(4) := digitalFilter(0) - upReg(5) := digitalFilter(1) - } - -} - diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala deleted file mode 100644 index b94c759..0000000 --- a/src/main/scala/backBoard/Dout16.scala +++ /dev/null @@ -1,115 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -trait BackBoardSlvOut16{ this: BackBoardSlvLocal => - - val outRegSync = Wire(UInt(16.W)) - - val mthodReg = RegInit(0.U(16.W)) - val valueReg = RegInit(0.U(16.W)) - - val outPin = Wire(UInt(16.W)) - - outPin := - Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync)) - -} - -trait DoutInspect{ this: BackBoardSlvLocal => - val flt = IO(Input(Vec(2, Bool()))) - val v24Det = IO(Input(Bool())) - val LED_ERR = IO(Output(Bool())) - - LED_ERR := ~RegNext(~v24Det) - - when( statusPage === 0.U ){ - upReg(2) := Cat( 0.U(7.W), RegNext(~v24Det) ) - upReg(3) := 0.U - upReg(4) := Cat( 0.U(7.W), RegNext(~flt(0)) ) - upReg(5) := 0.U - upReg(6) := Cat( 0.U(7.W), RegNext(~flt(1)) ) - upReg(7) := 0.U - } -} - -trait DoutInspect_Plus{ this: BackBoardSlvLocal => - val flashCounter: UInt - - val v24Det = IO(Input(Bool())) - val LED_ERR = IO(Output(Bool())) - - val fin_cur = IO(Input(UInt(4.W))) - val fin_sel = IO(Output(UInt(3.W))) - val fin_clk = IO(Output(Bool())) - val fin_vol = IO(Input(UInt(3.W))) - - val inspectCurr = for( i <- 0 until 4 ) yield { RegInit(0.U(8.W)) } - val finSelReg = RegInit(0.U(3.W)); fin_sel := finSelReg - val finClkReg = RegInit(false.B); fin_clk := finClkReg - - - when(flashCounter(2,0).andR){ - finClkReg := ~finClkReg - } - - when( flashCounter(2,0).andR & finClkReg ){ - finSelReg := finSelReg + 1.U - - inspectCurr(0) := ( inspectCurr(0) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(0) << finSelReg ) - inspectCurr(1) := ( inspectCurr(1) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(1) << finSelReg ) - inspectCurr(2) := ( inspectCurr(2) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(2) << finSelReg ) - inspectCurr(3) := ( inspectCurr(3) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(3) << finSelReg ) - } - - LED_ERR := ~( RegNext(~v24Det) | ( inspectCurr.map{ (isp: UInt) => (isp =/= 0.U) }.reduce(_|_) ) | ( RegNext(fin_vol) =/= 0.U ) ) - - when( statusPage === 0.U ){ - upReg(2) := Cat( 0.U(4.W), RegNext(fin_vol), RegNext(~v24Det) ) - upReg(3) := 0.U - upReg(4) := inspectCurr(0) - upReg(5) := inspectCurr(1) - upReg(6) := inspectCurr(2) - upReg(7) := inspectCurr(3) - } - - -} - - -abstract class DOut16 extends BackBoardSlvLocal -with BackBoardSlvStatusPR -with BackBoardSlvOut16{ - val out = IO(Output(UInt(16.W))) - val outReg = RegInit(0.U(16.W)) - - when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ - outReg := Cat(downRegTemp(13), downRegTemp(12)) - } - when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ - mthodReg := Cat(downRegTemp(9), downRegTemp(8)) - valueReg := Cat(downRegTemp(11), downRegTemp(10)) - } - - outRegSync := RegEnable( outReg, 0.U, isUpdate ) - - when( statusPage === 0.U ){ - upReg(8) := mthodReg(7,0) - upReg(9) := mthodReg(15,8) - - upReg(10) := valueReg(7,0) - upReg(11) := valueReg(15,8) - - upReg(12) := outReg(7,0) - upReg(13) := outReg(15,8) - } - - out := ~outPin - -} - - -class DOut16c extends DOut16 with DoutInspect -class DOut16p extends DOut16 with DoutInspect_Plus diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala deleted file mode 100644 index 5200c8d..0000000 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ /dev/null @@ -1,137 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class ManualParamBundle extends Bundle{ - val data2 = UInt(8.W) - val data3 = UInt(8.W) - val data4 = UInt(8.W) - val data5 = UInt(8.W) - val data6 = UInt(8.W) - val data7 = UInt(8.W) - val data8 = UInt(8.W) - val data9 = UInt(8.W) - - val vendorID = UInt( 16.W ) - val moduleID = UInt( 16.W ) - val hwVersion = UInt( 16.W ) - val swVersion = UInt( 16.W ) - val serial = UInt( 48.W ) -} - - -abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{ - - val param = IO(Input( new ManualParamBundle )) - - val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass ) - val statusP = RegInit(false.B) - val statusRF = RegInit(false.B) - val statusPR = RegInit(0.U(2.W)) - val statusER = RegInit(false.B) - val statusLE = RegInit(false.B) - val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass ) - val statusNone = ~ShiftRegister(io.isLast, 2) - val customData = for( i <- 0 until 3 ) yield { - RegEnable( downRegTemp(1).extract(5+i), false.B, isCrcPass ) - } - - upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage ) - upReg(1) := Cat( customData(2), customData(1), customData(0), statusNone, statusSync, statusLE, statusER, statusPR.extract(1) ) - - when( statusPage === 15.U ){ - upReg(2) := param.data2 - upReg(3) := param.data3 - upReg(4) := param.data4 - upReg(5) := param.data5 - upReg(6) := param.data6 - upReg(7) := param.data7 - upReg(8) := param.data8 - upReg(9) := param.data9 - - - upReg(10) := param.vendorID(7,0) - upReg(11) := param.vendorID(15,8) - - upReg(12) := param.moduleID(7,0) - upReg(13) := param.moduleID(15,8) - - upReg(14) := param.hwVersion(7,0) - upReg(15) := param.hwVersion(15,8) - - upReg(16) := param.swVersion(7,0) - upReg(17) := param.swVersion(15,8) - - upReg(18) := param.serial(7,0) - upReg(19) := param.serial(15,8) - upReg(20) := param.serial(23,16) - upReg(21) := param.serial(31,24) - upReg(22) := param.serial(39,32) - upReg(23) := param.serial(47,40) - } - - - - val (usCounter, usTrigger) = Counter(Range(0, 10)) - - io.isOnline := false.B - - val isUpdate = (statusSync & ShiftRegister(io.DCIn, 3)) | (~statusSync) - -} - - - - - -trait BackBoardSlvStatusPR { this: BackBoardSlvLocal => - val flashCounter = RegInit( 0.U( 19.W ) ) - val flash2HZ = Reg(Bool()) - val flash1HZ = Reg(Bool()) - - - when( usTrigger ){ - when( flashCounter >= 500000.U ){ - flashCounter := 0.U - flash2HZ := ~flash2HZ - when( flash2HZ ){ - flash1HZ := ~flash1HZ - } - } .otherwise{ - flashCounter := flashCounter + 1.U - } - } - - - - val LED_PR = IO(Output( Bool() )) - - LED_PR := ~Mux( statusPR === "b00".U, flash2HZ, - Mux( statusPR === "b01".U, flash1HZ, - Mux( statusPR === "b10".U, false.B, true.B - ))) - - - val watchDogTarget = RegInit( 0.U( 19.W ) ) - - when( isCrcPass ){ - watchDogTarget := flashCounter - } - - when( isCrcPass ){ - statusPR := Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ) - } .elsewhen( ((watchDogTarget === (flashCounter + 1.U)) | (watchDogTarget === 0.U & (flashCounter >= 500000.U))) & usTrigger ){ - statusPR := 0.U - } - - -} - - - - - - - - diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala deleted file mode 100644 index 96e3188..0000000 --- a/src/main/scala/backBoard/MirrorSRAM.scala +++ /dev/null @@ -1,335 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - -class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline { - class MirrorSRAMDownIO extends Bundle{ - val addrr = Input(UInt(11.W)) - val addrw = Input(UInt(10.W)) - - val dataw = Input( UInt(16.W) ) - val datar = Output( UInt(8.W) ) - val enw = Input(Bool()) - val enr = Input(Bool()) - - val clockr = Input(Bool()) - val clockw = Input(Bool()) - - } - val io: MirrorSRAMDownIO = IO(new MirrorSRAMDownIO) - - setInline("MirrorSRAMDown.v", - """ - | module MirrorSRAMDown( - | input [15:0] dataw, - | input [9:0] addrw, - | input enw, - | - | output [7:0] datar, - | input [10:0] addrr, - | input enr, - | - | input clockr, - | input clockw - | ); - | - | reg [15:0] ram[0:1023]; - | reg [7:0] data_r_reg; - | - | always @(posedge clockw) begin - | if(enw) begin - | ram[addrw] <= #1 dataw; - | end - | end - | - | always @(posedge clockr) begin - | if(enr) begin - | data_r_reg <= #1 addrr[0] ? ram[addrr[10:1]][15:8] : ram[addrr[10:1]][7:0]; - | end - | end - | - | assign datar = data_r_reg; - | - | initial begin - | for ( integer i = 0; i < 1024; i = i + 1 ) begin - | ram[i] = $random; - | end - | - | data_r_reg = $random; - | end - | - |endmodule - """.stripMargin) -} - - -class MirrorSRAMUp extends BlackBox with HasBlackBoxInline { - - class MirrorSRAMUpIO extends Bundle{ - val addrr = Input(UInt(10.W)) - val addrw = Input(UInt(11.W)) - - val dataw = Input( UInt(8.W) ) - val datar = Output( UInt(16.W) ) - val enw = Input(Bool()) - val enr = Input(Bool()) - - val clockr = Input(Bool()) - val clockw = Input(Bool()) - - } - val io: MirrorSRAMUpIO = IO(new MirrorSRAMUpIO) - - setInline("MirrorSRAMUp.v", - """ - | module MirrorSRAMUp( - | input [7:0] dataw, - | input [10:0] addrw, - | input enw, - | - | output [15:0] datar, - | input [9:0] addrr, - | input enr, - | - | input clockr, - | input clockw - | ); - | - | reg [7:0] ram[0:2047] /* synthesis syn_ramstyle="block_ram" */; - | reg [15:0] data_r_reg; - | - | always @(posedge clockw) begin - | if(enw) begin - | ram[addrw] <= #1 dataw; - | end - | end - | - | always @(posedge clockr) begin - | if(enr) begin - | data_r_reg <= #1 { ram[2*addrr+1], ram[2*addrr] }; - | end - | end - | - | assign datar = data_r_reg; - | - | - |endmodule - """.stripMargin) -} - - - -class MirrorSRAMDP extends BlackBox with HasBlackBoxInline { - - class MirrorSRAMDPIO extends Bundle{ - - val addrA = Input(UInt(10.W)) - val datawA = Input( UInt(16.W) ) - val datarA = Output( UInt(16.W) ) - val enwA = Input(Bool()) - val enrA = Input(Bool()) - val clockA = Input(Bool()) - - - val addrB = Input(UInt(10.W)) - val datawB = Input( UInt(16.W) ) - val datarB = Output( UInt(16.W) ) - val enwB = Input(Bool()) - val enrB = Input(Bool()) - val clockB = Input(Bool()) - - } - val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO) - - setInline("MirrorSRAMDP.v", - """ - | module MirrorSRAMDP( - | input [15:0] datawA, - | input [9:0] addrA, - | input enwA, - | input enrA, - | output [15:0] datarA, - | input clockA, - | - | input [15:0] datawB, - | input [9:0] addrB, - | input enwB, - | input enrB, - | output [15:0] datarB, - | input clockB - | ); - | - | reg [15:0] mem[0:1023]; - | reg [15:0] data_outa_reg = 16'b0; - | reg [15:0] data_outb_reg = 16'b0; - | - | assign datarA = data_outa_reg; - | assign datarB = data_outb_reg; - | - | always@( posedge clockA ) begin - | if( enrA ) begin - | end - | - | if( enwA ) begin - | mem[addrA] <= datawA; - | end else begin - | data_outa_reg <= mem[addrA]; - | end - | end - | - | - | always@( posedge clockB ) begin - | if(enrB) begin - | end - | - | if( enwB ) begin - | mem[addrB] <= datawB; - | end else begin - | data_outb_reg <= mem[addrB]; - | end - | end - | - | initial begin - | for( integer i = 0; i < 1024; i = i + 1 ) begin - | mem[i] = $random; - | end - | end - | - | //Gowin_DPB your_instance_name( - | // .douta(datarA), //output [15:0] douta - | // .doutb(datarB), //output [15:0] doutb - | // .clka(clockA), //input clka - | // .ocea(1'b1), //input ocea - | // .cea(1'b1), //input cea - | // .reseta(1'b0), //input reseta - | // .wrea(enwA), //input wrea - | // .clkb(clockB), //input clkb - | // .oceb(1'b1), //input oceb - | // .ceb(1'b1), //input ceb - | // .resetb(1'b0), //input resetb - | // .wreb(enwB), //input wreb - | // .ada(addrA), //input [3:0] ada - | // .dina(datawA), //input [15:0] dina - | // .adb(addrB), //input [3:0] adb - | // .dinb(datawB) //input [15:0] dinb - | //); - | - |endmodule - """.stripMargin) -} - - - - - - -class SpiSRAMDown() extends BlackBox with HasBlackBoxInline { - class SpiSRAMDownIO extends Bundle{ - val addrr = Input(UInt(9.W)) - val addrw = Input(UInt(9.W)) - - val dataw = Input( UInt(8.W) ) - val datar = Output( UInt(8.W) ) - val enw = Input(Bool()) - val enr = Input(Bool()) - - val clockr = Input(Bool()) - val clockw = Input(Bool()) - - } - val io: SpiSRAMDownIO = IO(new SpiSRAMDownIO) - - setInline("SpiSRAMDown.v", - """ - | module SpiSRAMDown( - | input [7:0] dataw, - | input [8:0] addrw, - | input enw, - | - | output [7:0] datar, - | input [8:0] addrr, - | input enr, - | - | input clockr, - | input clockw - | ); - | - | reg [7:0] ram[0:511]; - | reg [7:0] data_r_reg; - | - | always @(posedge clockw) begin - | if(enw) begin - | ram[addrw] <= #1 dataw; - | end - | end - | - | always @(posedge clockr) begin - | if(enr) begin - | data_r_reg <= #1 ram[addrr]; - | end - | end - | - | assign datar = data_r_reg; - | - | - |endmodule - """.stripMargin) -} - - -class SpiSRAMUp extends BlackBox with HasBlackBoxInline { - - class SpiSRAMUpIO extends Bundle{ - val addrr = Input(UInt(9.W)) - val addrw = Input(UInt(9.W)) - - val dataw = Input( UInt(8.W) ) - val datar = Output( UInt(8.W) ) - val enw = Input(Bool()) - val enr = Input(Bool()) - - val clockr = Input(Bool()) - val clockw = Input(Bool()) - - } - val io: SpiSRAMUpIO = IO(new SpiSRAMUpIO) - - setInline("SpiSRAMUp.v", - """ - | module SpiSRAMUp( - | input [7:0] dataw, - | input [8:0] addrw, - | input enw, - | - | output [7:0] datar, - | input [8:0] addrr, - | input enr, - | - | input clockr, - | input clockw - | ); - | - | reg [7:0] ram[0:511]; - | reg [7:0] data_r_reg; - | - | always @(posedge clockw) begin - | if(enw) begin - | ram[addrw] <= #1 dataw; - | end - | end - | - | always @(posedge clockr) begin - | if(enr) begin - | data_r_reg <= #1 ram[addrr]; - | end - | end - | - | assign datar = data_r_reg; - | - | - |endmodule - """.stripMargin) -} \ No newline at end of file diff --git a/src/main/scala/backBoard/Qei.scala b/src/main/scala/backBoard/Qei.scala deleted file mode 100644 index 4b6c611..0000000 --- a/src/main/scala/backBoard/Qei.scala +++ /dev/null @@ -1,160 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -trait BackBoardSlvQei{ this: BackBoardSlvLocal => - val phaseA = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val phaseB = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val phaseZ = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val counter = for( i <- 0 until 2 ) yield { Reg(UInt(33.W)) } - val encordNxt = for( i <- 0 until 2 ) yield { Cat( phaseB(i), phaseA(i) ) } - val encordCur = for( i <- 0 until 2 ) yield { RegNext(encordNxt(i)) } - - val isEnable = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isSign = for( i <- 0 until 2 ) yield { Reg(Bool()) } - val isSetVal = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val initVal = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } - val mode = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) } - val invDirect = for( i <- 0 until 2 ) yield { Reg(Bool()) } - val is2Phase = for( i <- 0 until 2 ) yield { Reg(Bool()) } - val isZPhaseEnable = for( i <- 0 until 2 ) yield { Reg(Bool()) } - val isSetValPos = for( i <- 0 until 2 ) yield { ~RegNext( isSetVal(i), false.B ) & isSetVal(i) } - val isSetValNeg = for( i <- 0 until 2 ) yield { RegNext( isSetVal(i), false.B ) & ~isSetVal(i) } - - val isAdvA = for( i <- 0 until 2 ) yield { - ( encordCur(i) === "b00".U & encordNxt(i) === "b01".U & mode(i).extract(1)) | - ( encordCur(i) === "b01".U & encordNxt(i) === "b11".U & mode(i) =/= "b00".U ) | - ( encordCur(i) === "b11".U & encordNxt(i) === "b10".U & mode(i).extract(1)) | - ( encordCur(i) === "b10".U & encordNxt(i) === "b00".U ) - } - - - val isAdvB = for( i <- 0 until 2 ) yield { - ( encordNxt(i) === "b00".U & encordCur(i) === "b01".U ) | - ( encordNxt(i) === "b01".U & encordCur(i) === "b11".U & mode(i).extract(1)) | - ( encordNxt(i) === "b11".U & encordCur(i) === "b10".U & mode(i) =/= "b00".U ) | - ( encordNxt(i) === "b10".U & encordCur(i) === "b00".U & mode(i).extract(1)) - } - - val isMiss = for( i <- 0 until 2 ) yield { encordCur(i) === ~encordNxt(i) } - // val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) === encordNxt(i) } - val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val isCounter32Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(32)) =/= counter(i).extract(32) } - val isCounter31Flip = for( i <- 0 until 2 ) yield { (RegNext( counter(i).extract(31)) =/= counter(i).extract(31)) & (RegNext( counter(i).extract(32)) === counter(i).extract(32)) } - - - for( i <- 0 until 2 ){ - - - isOverflow(i) := false.B - - when( isZPhaseEnable(i) & phaseZ(i) ){ //Z Phase reset - counter(i) := initVal(i) - } .elsewhen( isSetValPos(i) ){ - counter(i) := initVal(i) - } .elsewhen( isSetValNeg(i) ){ - counter(i) := 0.U - } .otherwise{ - when(isEnable(i)){ - when(~is2Phase(i)){ //A Phase only - when( RegNext( phaseA(i) ) & ~phaseA(i) ){ - counter(i) := counter(i) + 1.U - } - - isOverflow(i) := isSetVal(i) & isCounter32Flip(i) - - } .otherwise{ //AB Phase - - when( invDirect(i) ) { - when(isAdvA(i)){ - counter(i) := counter(i) - 1.U - } .elsewhen(isAdvB(i)){ - counter(i) := counter(i) + 1.U - } - } .otherwise{ //~invDirect(i) - when(isAdvA(i)){ - counter(i) := counter(i) + 1.U - } .elsewhen(isAdvB(i)){ - counter(i) := counter(i) - 1.U - } - } - - isOverflow(i) := - Mux( isSign(i), isSetVal(i) & isCounter31Flip(i), isSetVal(i) & isCounter32Flip(i) ) - } - - } .otherwise{ //~isEnable - counter(i) := initVal(i) - } - } - } - - -} - - -class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQei{ - val phaseAIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) } - val phaseBIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) } - val phaseZIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) } - - - for( i <- 0 until 2 ){ - phaseA(i) := RegNext(phaseAIO(i)) - phaseB(i) := RegNext(phaseBIO(i)) - phaseZ(i) := RegNext(phaseZIO(i)) - } - - for( i <- 0 until 2 ){ - - when(isOverflow(i)){ - isEnable(i) := false.B - } .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & ~downRegTemp(2+i).extract(0) ){ - isEnable(i) := false.B - } .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & downRegTemp(2+i).extract(0) ){ - isEnable(i) := true.B - } - - when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ - isZPhaseEnable(i) := downRegTemp(2+(2*i)).extract(1) - is2Phase(i) := downRegTemp(2+(2*i)).extract(2) - isSetVal(i) := downRegTemp(2+(2*i)).extract(3) - mode(i) := downRegTemp(2+(2*i))(5,4) - invDirect(i) := downRegTemp(2+(2*i)).extract(6) - isSign(i) := downRegTemp(2+(2*i)).extract(7) - - } - - when( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & ~downRegTemp(2+i).extract(3) ){ - initVal(i) := 0.U - } .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & downRegTemp(2+i).extract(3) ){ - initVal(i) := Cat( downRegTemp(9+(4*i)), downRegTemp(8+(4*i)), downRegTemp(7+(4*i)), downRegTemp(6+(4*i)) ) - } - - } - - val cntLatch = for( i <- 0 until 2 ) yield { RegEnable(counter(i), ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & io.lvdsSlv.upstream_tx_data_ready ) } - - - when( statusPage === 0.U ){ - upReg(2) := Cat( isSign(0), invDirect(0), mode(0), isSetVal(0), is2Phase(0), isZPhaseEnable(0), isEnable(0) ) - upReg(3) := 0.U - upReg(4) := Cat( isSign(1), invDirect(1), mode(1), isSetVal(1), is2Phase(1), isZPhaseEnable(1), isEnable(1) ) - upReg(5) := 0.U - - upReg(6) := cntLatch(0)(7,0) - upReg(7) := cntLatch(0)(15,8) - upReg(8) := cntLatch(0)(23,16) - upReg(9) := cntLatch(0)(31,24) - - upReg(10) := cntLatch(1)(7,0) - upReg(11) := cntLatch(1)(15,8) - upReg(12) := cntLatch(1)(23,16) - upReg(13) := cntLatch(1)(31,24) - } - -} - diff --git a/src/main/scala/backBoard/Readme.md b/src/main/scala/backBoard/Readme.md deleted file mode 100644 index 23be57b..0000000 --- a/src/main/scala/backBoard/Readme.md +++ /dev/null @@ -1,36 +0,0 @@ -# 背板总线 - -## 用户接口 - - -* 数据地址线 AD 16比特位宽 - -* 地址锁存 ADVn 负逻辑 -* 读使能 RDn 负逻辑 -* 写使能 WRn 负逻辑 -* 片选 CSn 负逻辑 - - -使用要求：地址锁存时ADV保持高至少30ns， 写入时CS,WR保持高至少30ns，读出时CS,RD保持高至少30ns方可读取数据线上数据 --------------------------------------- - -### 内存空间映射 - -* 总线上最多允许挂载64个从站，每个从站有8bits*32个下行寄存器（只写），8bits*32个上行寄存器（只读） -* 当地址线第11比特(AD[10])为低时，FSMC访问（只读或者只写）从站镜像寄存器（以8比特形式组织）， - - 通过16比特写用户接口 0x00 ~ 0x1F, 可以将数据同步写入到从站0的16个下行寄存器（只写）中，后续从站地址按序分配 - - 通过16比特读用户接口 0x00 ~ 0x1F, 可以将数据同步写入到从站0的16个上行寄存器（只读）中，后续从站地址按序分配 -* 当地址线第11比特(AD[10])为高时，FSMC通过地址9到0比特访问（可读可写）主站寄存器全部定义为16比特 - - 0x00 控制状态， - + statusCDRErr: 第4比特，表示LVDS总线发生CDR解析错误，写1清零 - + statusCRCErr: 第3比特，表示LVDS总线发生传输CRC错误，写1清零 - + statusLinkErr: 第2比特，表示LVDS总线发生从站掉线，写1清零 - + statusSynch: 第1比特，表示LVDS总线各个从站已经同步，初始化完成时且ctrlSynch为高自动置高，手动将ctrlInit置高时自动置低 - + statusInit: 第0比特，表示LVDS总线已经初始化，初始化完成时自动置高，手动将ctrlInit置高时自动置低 - - 0x01 操作寄存器 - + ctrlTransmit: 第5比特，手动写入1将触发LVDS总线传输，传输完成将自动清零 - + ctrlSynch: 第1比特，手动写入1表示初始化的同时同步所有从站 - + ctrlInit: 第0比特，手动写入1将触发LVDS总线初始化，初始化完成将自动清零 - - - 0x02 配置从栈数量（减一）: 从站数量当前无法手动配置，初始化过程中将自动检测在线从站数量，并以该数量进行初始化，从站数量将自动写入该寄存器 - - 0x03 离线位置: 当发生从站掉线，该寄存器可读出掉线从站编号 diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala deleted file mode 100644 index 62841bf..0000000 --- a/src/main/scala/backBoard/SpiSlv.scala +++ /dev/null @@ -1,153 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -trait BackBoardSpiSlv{ this: BackBoardSlvLocal => - - val sck = Wire(Bool()) - val mosi = Wire(Bool()) - val csn = Wire(Bool()) - val clk100M = Wire(Bool()) - - val spiRegDown = Module(new SpiSRAMDown) - val spiRegUp = Module(new SpiSRAMUp) - - - spiRegDown.io.clockr := clk100M - spiRegDown.io.clockw := clock.asBool - - spiRegUp.io.clockr := clock.asBool - spiRegUp.io.clockw := clk100M - - - val localUpdate = RegInit(0.U(16.W)) - - val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) } - val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) } - val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) } - - - val isSckPosedge = ~shiftSCK(2) & shiftSCK(1) - val isSckPosedgeNext = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(isSckPosedge, 2, false.B, true.B) } - - - val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) } - val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) } - val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) } - val pageSel = cmd_100M(5,4) - val spiCmd = cmd_100M(3,0) - - val bitSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) } - val byteSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(5.W)) } - - - spiRegDown.io.addrr := Cat(pageSel, byteSel) - spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0) - - spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U) - spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) } - spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U - - withClockAndReset( clk100M.asClock, reset ){//100M - - when( shiftCSn(2) & ~shiftCSn(1) ){ - bitSel := 0.U - byteSel := 0.U - } .elsewhen( isSckPosedge & ~shiftCSn(1) ){ - bitSel := bitSel + 1.U - when( bitSel === 7.U ){ - byteSel := byteSel + 1.U - } - } - - when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 - bitSel := 0.U - byteSel := 0.U - cmd_100M := 0.U - } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte - cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) ) - } - - when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 - exReg_100M := upReg(0) - } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit - when( byteSel === 1.U ){ - exReg_100M := upReg(1) - } .elsewhen( spiCmd === 2.U & byteSel === 2.U ){ - exReg_100M := localUpdate(7,0) - } .elsewhen( spiCmd === 2.U & byteSel === 3.U ){ - exReg_100M := localUpdate(15,8) - } .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){ - exReg_100M := spiRegDown.io.datar - } - } .elsewhen( isSckPosedge & ~shiftCSn(1) ){ - exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) ) - } - - - when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){ - exMask_100M := Cat( exReg_100M, exMask_100M(7,0) ) - } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){ - exMask_100M := Cat( exMask_100M(15,8), exReg_100M ) - } - - } -} - - -class SpiSlv extends BackBoardSlvLocal -with BackBoardSlvStatusPR -with BackBoardSpiSlv{ - - val spi = IO(new Bundle{ - val sck = Input(Bool()) - val mosi = Input(Bool()) - val miso = Output(Bool()) - val csn = Input(Bool()) - }) - val clk100MIO = IO(Input(Bool())) - val interrupt = IO(Output(Bool())) - - sck := spi.sck - mosi := spi.mosi - csn := spi.csn - spi.miso := exReg_100M.extract(exReg_100M.getWidth-1) - clk100M := clk100MIO - - val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B) - - - when( isCrcPass ){ - localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) ) - } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){ - localUpdate := localUpdate & ~exMask_100M - } - - - - - spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U) - spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out - spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0)) - - spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready - spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U ) - - - io.lvdsSlv.upstream_tx_data_in := - Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar) - - val int = RegInit(false.B); interrupt := int - when( int ){ - int := false.B - } .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){ - int := true.B - } - - -} - - - diff --git a/src/main/scala/backBoard/ebus/Axis8toN.scala.bk b/src/main/scala/backBoard/ebus/Axis8toN.scala.bk deleted file mode 100644 index 4866875..0000000 --- a/src/main/scala/backBoard/ebus/Axis8toN.scala.bk +++ /dev/null @@ -1,29 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class Axis8toNIO_Bundle(dw: Int) extends Bundle{ - val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(8))) - val deq = Decoupled(new AxisNto8IO_Bundle(dw)) -} - - - - -class Axis8toN(dw: Int) extends Module{ - - require( dw == 16 | dw == 32 | dw == 64 ) - assert( io.deq.ready === true.B ) - - val io: Axis8toNIO_Bundle = IO(new Axis8toNIO_Bundle(dw)) - - val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) ) - - val fifo = Reg( new AxisNto8IO_Bundle(dw) ) - - - -} - diff --git a/src/main/scala/backBoard/ebus/AxisNto8.scala.bk b/src/main/scala/backBoard/ebus/AxisNto8.scala.bk deleted file mode 100644 index d3c64cb..0000000 --- a/src/main/scala/backBoard/ebus/AxisNto8.scala.bk +++ /dev/null @@ -1,48 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class AxisNto8IO_Bundle(dw: Int) extends Bundle{ - val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(dw))) - val deq = Decoupled(new AxisNto8IO_Bundle(8)) -} - - -class AxisNto8(dw: Int) extends Module{ - - require( dw == 16 | dw == 32 | dw == 64 ) - - val io: AxisNto8IO_Bundle = IO(new AxisNto8IO_Bundle(dw)) - - val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) ) - val isBusy = RegInit(false.B) - - val fifo = RegEnable( io.enq.bits, io.enq.fire ) - io.enq.ready := ~isBusy | (io.deq.fire & cnt.andR) - - - - - when( io.deq.fire ){ - cnt := cnt + 1.U - } - - when( io.enq.fire ){ - isBusy := true.B - } .elsewhen( io.deq.fire & cnt.andR ){ - isBusy := false.B - } - - - - - io.deq.valid := isBusy - io.deq.bits.tdata := fifo.tdata >> (cnt << 3) - io.deq.bits.tlast := fifo.tlast & cnt.andR - io.deq.bits.tuser := fifo.tuser & cnt.andR - - -} - diff --git a/src/main/scala/backBoard/ebus/BackBoardMst.scala.bk b/src/main/scala/backBoard/ebus/BackBoardMst.scala.bk deleted file mode 100644 index e3f623d..0000000 --- a/src/main/scala/backBoard/ebus/BackBoardMst.scala.bk +++ /dev/null @@ -1,52 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class BackBoardMstIO extends Bundle{ - val downStreamReqDat = Input( Bool() ) - val downStreamRespdat = Output(Bool()) - - val CS = Input(Bool()) - val MISO = Output(Bool()) - val MOSI = Input(Bool()) - val SCK = Input(Bool()) - - val interrupt = Output(Bool()) - - val clk4 = Input( Bool() ) - -} - - -class BackBoardMst extends Module{ - val io: BackBoardMstIO = IO(new BackBoardMstIO) - - - val spi = Module( new SpiSlv ) - val in = Module( new CDR4MultiIn ) - val out = Module( new CDROutBus ) - - spi.io.CS := io.CS - io.MISO := spi.io.MISO - spi.io.MOSI := io.MOSI - spi.io.SCK := io.SCK - - // io.interrupt := spi.io.interrupt - io.interrupt := false.B - - spi.io.CDRIn <> in.io.latDat - spi.io.CDROut <> out.io.pkgDat - - in.io.clk4 := io.clk4 - spi.io.clk4 := io.clk4 - - in.io.dat := io.downStreamReqDat - io.downStreamRespdat := out.io.dat - - -} - - - diff --git a/src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk b/src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk deleted file mode 100644 index dc96062..0000000 --- a/src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk +++ /dev/null @@ -1,105 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class BackBoardSlvIO extends Bundle{ - val localHost = Input(UInt(5.W)) - - val upStreamReqDat = Input( Bool() ) - val downStreamReqDat = Input( Bool() ) - - val upStreamRespdat = Output(Bool()) - val downStreamRespdat = Output(Bool()) - - val clk4 = Input( Bool() ) -} - - -abstract class BackBoardSlvBase extends Module{ - val io: BackBoardSlvIO = IO(new BackBoardSlvIO) - - - val upStreamReq = Module(new CDR4MultiIn) - val downStreamReq = Module(new CDR4MultiIn) - - val upStreamResp = Module(new CDROutBus) - val downStreamResp = Module(new CDROutBus) - - upStreamReq.io.clk4 := io.clk4 - downStreamReq.io.clk4 := io.clk4 - upStreamReq.io.dat := io.upStreamReqDat - downStreamReq.io.dat := io.downStreamReqDat - - io.upStreamRespdat := upStreamResp.io.dat - io.downStreamRespdat := downStreamResp.io.dat - - - - def IDLE = 0.U - def UPSTREAM_RESP = 1.U - def DOWNSTREAM_RESP = 2.U - - val stateNext = Wire( UInt(2.W) ) - val stateCurr = RegNext(stateNext, 0.U) - - stateNext := Mux1H(Seq( - (stateCurr === IDLE) -> Mux(upStreamReq.io.latDat.fire, Mux(upStreamReq.io.latDat.bits.address(5,1) === io.localHost, UPSTREAM_RESP, DOWNSTREAM_RESP), Mux(downStreamReq.io.latDat.fire, UPSTREAM_RESP, IDLE) ), - (stateCurr === UPSTREAM_RESP) -> Mux(upStreamResp.io.pkgDat.fire, IDLE, UPSTREAM_RESP ), - (stateCurr === DOWNSTREAM_RESP) -> Mux(downStreamResp.io.pkgDat.fire, IDLE, DOWNSTREAM_RESP ), - )) - - val upStreamReqReady = RegInit(false.B); upStreamReq.io.latDat.ready := upStreamReqReady - val downStreamReqReady = RegInit(false.B); downStreamReq.io.latDat.ready := downStreamReqReady - - val upStreamRespValid = RegInit(false.B); upStreamResp.io.pkgDat.valid := upStreamRespValid - val upStreamRespInfo = Reg(new CDRData); upStreamResp.io.pkgDat.bits := upStreamRespInfo - val downStreamRespValid = RegInit(false.B); downStreamResp.io.pkgDat.valid := downStreamRespValid - val downStreamRespInfo = Reg(new CDRData); downStreamResp.io.pkgDat.bits := downStreamRespInfo - - val registersRD = Wire(UInt(32.W)) - - - -} - -trait StatusControl{ this: BackBoardSlvBase => - - when( upStreamResp.io.pkgDat.fire ){ - upStreamRespValid := false.B - } .elsewhen( downStreamResp.io.pkgDat.fire ){ - downStreamRespValid := false.B - }.elsewhen( upStreamReq.io.latDat.fire ){ - upStreamReqReady := false.B - - when( upStreamReq.io.latDat.bits.address(5,1) === io.localHost ){ - upStreamRespValid := true.B - upStreamRespInfo.address := upStreamReq.io.latDat.bits.address - upStreamRespInfo.register := upStreamReq.io.latDat.bits.register - upStreamRespInfo.data := Mux(upStreamReq.io.latDat.bits.address.extract(0) === 0.U, registersRD, 0.U ) - upStreamRespInfo.hash := 0.U - - } .otherwise{ - downStreamRespValid := true.B - downStreamRespInfo := upStreamReq.io.latDat.bits - } - - } .elsewhen( downStreamReq.io.latDat.fire ){ - downStreamReqReady := false.B - - upStreamRespValid := true.B - upStreamRespInfo := downStreamReq.io.latDat.bits - } .elsewhen( downStreamReq.io.latDat.valid & ~downStreamReq.io.latDat.ready && stateCurr === IDLE ){ - downStreamReqReady := true.B - } .elsewhen( upStreamReq.io.latDat.valid & ~upStreamReq.io.latDat.ready & ~downStreamReq.io.latDat.valid & stateCurr === IDLE ){ - upStreamReqReady := true.B - } - - - -} - - -class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters - diff --git a/src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk b/src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk deleted file mode 100644 index acdb31b..0000000 --- a/src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk +++ /dev/null @@ -1,82 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - -import freechips.rocketchip.util._ - - -class CDRData extends Bundle{ - val address = UInt(6.W) - val register = UInt(8.W) - val data = UInt(32.W) - val hash = UInt(16.W) - - def crcHash = 0.U - def isHashPass = true.B - -} - -class CDR4MultiInIO() extends Bundle{ - val dat = Input(Bool()) - val clk4 = Input(Bool()) - - val latDat = Decoupled(new CDRData) -} - - - -class CDR4MultiIn() extends Module{ - val io: CDR4MultiInIO = IO(new CDR4MultiInIO()) - - val latValidSet = Wire(Bool()) - - val latValidSetAsync = ShiftRegister( latValidSet, 2, false.B, true.B ) - val latValidReset = RegNext(latValidSetAsync, false.B) - - val transInfo = Wire(new CDRData) - - withClockAndReset( io.clk4.asClock, reset ){ - val latValidSetReg = RegInit(false.B); latValidSet := latValidSetReg - val latValidResetAsync = ShiftRegister(latValidReset, 2, false.B, true.B) - - val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) ) - - - transInfo := - Cat( - ( 0 until (6+8+32+16) ).map{ i => shiftDat( 4*(i+1) + 1 ) } - ).asTypeOf(new CDRData) - - - when( latValidSetReg & latValidResetAsync ){ - shiftDat := 0.U - latValidSetReg := false.B - } .elsewhen( shiftDat.extract(0) =/= 1.U ){ - shiftDat := Cat(io.dat, shiftDat( ((1+6+8+32+16)*4+2)-1, 1) ) - } .elsewhen( shiftDat.extract(0) === 1.U ){ - latValidSetReg := true.B - } - - - } - - val latDatValid = RegInit(false.B) - val latDatInfo = Reg(new CDRData) - - when( io.latDat.fire ){ - latDatValid := false.B - } .elsewhen( latValidSetAsync & ~latValidReset){ - latDatValid := true.B - latDatInfo := transInfo - } - - io.latDat.valid := latDatValid - io.latDat.bits := latDatInfo - - -} - - diff --git a/src/main/scala/backBoard/ebus/CDROutBus.scala.bk b/src/main/scala/backBoard/ebus/CDROutBus.scala.bk deleted file mode 100644 index 729d30a..0000000 --- a/src/main/scala/backBoard/ebus/CDROutBus.scala.bk +++ /dev/null @@ -1,65 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class CDROutBusIO() extends Bundle{ - val pkgDat = Flipped(Decoupled(new CDRData)) - val dat = Output(Bool()) - -} - -class CDROutBus extends Module{ - val io: CDROutBusIO = IO(new CDROutBusIO) - - val isBusy = RegInit(false.B) - io.pkgDat.ready := ~isBusy - - val address = Reg(UInt(6.W)) - val register = Reg(UInt(8.W)) - val data = Reg(UInt(32.W)) - val hash = Reg(UInt(16.W)) - - val cnt = RegInit( 0.U(7.W) ) - - - when( cnt === (1+6+8+32+16).U ){ - isBusy := false.B - } .elsewhen( io.pkgDat.fire ){ - isBusy := true.B - - address := io.pkgDat.bits.address - register := io.pkgDat.bits.register - data := io.pkgDat.bits.data - - } - - when(io.pkgDat.fire){ - cnt := 0.U - } .elsewhen( isBusy ){ - cnt := cnt + 1.U - } - - - - when( cnt === 1.U ){ - io.dat := true.B - } .elsewhen( cnt >= (1 + 1).U && cnt < (6 + 1 + 1).U ){ - io.dat := address(5) - address := address << 1 - } .elsewhen( cnt >= (1 + 1 + 6).U && cnt < (8 + 1+ 1 + 6).U ){ - io.dat := register(7) - register := register << 1 - } .elsewhen( cnt >= (1 + 1 + 6 + 8).U && cnt < (32 + 1 + 1 + 6 + 8).U ){ - io.dat := data(31) - data := data << 1 - } .elsewhen( cnt >= (1 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 1 + 6 + 8 + 32).U ){ - io.dat := hash(15) - hash := hash << 1 - } .otherwise{ - io.dat := false.B - } - -} - diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk b/src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk deleted file mode 100644 index 2cadb68..0000000 --- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk +++ /dev/null @@ -1,649 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ - -import freechips.rocketchip.tile._ - -class RocCC2CDRInIO extends Bundle{ - val overCLK = Bool() - val dDatIn = Bool() - val uDatIn = Bool() - - val isLast = Bool() -} - -class RocCC2CDROutIO extends Bundle{ - val dDatOut = Bool() - val uDatOut = Bool() - - val isOnline = Bool() -} - -class RoCC2CDRIO extends Bundle{ - val overCLK = Input(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) -} - - - -class RoCC2CDR()(implicit p: Parameters) extends LazyModule { - val opcodes: OpcodeSet = OpcodeSet.custom0 - val roccCSRs: Seq[CustomCSR] = Nil - lazy val module: RoCC2CDRImpl = new RoCC2CDRImpl(this) -} - - - -abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) { - val io = IO(new RoCCIO(0, 0)) - - // val cdrio: RoCC2CDRIO = IO(new RoCC2CDRIO) - val cdrInio = IO(Input(new RocCC2CDRInIO)) - val cdrOutio = IO(Output(new RocCC2CDROutIO)) - - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } - when(true.B){ - print("Warning!!! New Code has not been reviewed!\n") - } - - CDRIn(0).io.serDat := cdrInio.dDatIn - CDRIn(1).io.serDat := cdrInio.uDatIn - - CDRIn(0).overCLK := cdrInio.overCLK - CDRIn(1).overCLK := cdrInio.overCLK - - - - val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } - - cdrOutio.dDatOut := CDROut(0).io.serDat - cdrOutio.uDatOut := CDROut(1).io.serDat - - val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - - val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } - val isTLReadStatus = Wire( Bool() ) - - val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - - val wdata = Wire(UInt(32.W)) - - val isTLReadRxFifoBypassTx = for( i <- 0 until 4 ) yield { Wire(Bool()) } //0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 -} - - -trait RoCC2CDRImplTx{ this: RoCC2CDRImplBase => - - - val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) } - - - val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready } - val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) } - val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast } - val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) } - - val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire } - - val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) } - val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } - - for( i <- 0 until 2 ) { - when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U - txData(i) := txFifo(i).io.deq.bits - when( isTxBusy(i) ){ - assert(CDROut(i).io.axis.fire) - } - } .elsewhen( CDROut(i).io.axis.fire ){ - txData(i) := txData(i) << 8 - } - - txFifo(i).io.deq.ready := - isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B ) - - txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - - CDROut(i).io.axis.bits.tdata := txData(i).head(8) - CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U - CDROut(i).io.axis.bits.tuser := false.B - CDROut(i).io.axis.valid := isTxBusy(i) - - - when( isTLWriteSoftReset(i) ){ - isTxBusy(i) := false.B - }.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){ - isTxBusy(i) := true.B - } .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){ - isTxBusy(i) := false.B - } - - - when( isTLWriteSoftReset(0+i) ){ - txCnt(i) := 0.U - } .elsewhen( CDROut(i).io.axis.fire ){ - txCnt(i) := txCnt(i) + 1.U - } - - - when( isTLWriteTxLen(i) ){ - txLen(i) := wdata - } .elsewhen( CDROut(i).io.axis.fire ){ - txLen(i) := txLen(i) - 1.U - } - - txFifo(i).io.enq.bits := Mux1H(Seq( - isTLWriteTxFifo(i) -> wdata, - isTLReadRxFifoBypassTx(0+i) -> rxFifo(0).io.deq.bits, - isTLReadRxFifoBypassTx(2+i) -> rxFifo(1).io.deq.bits, - )) - - - -//0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 - - txFifo(i).io.enq.valid := - txLen(i) =/= 0.U & ( - isTLWriteTxFifo(i) | - isTLReadRxFifoBypassTx(0+i) | - isTLReadRxFifoBypassTx(2+i) - ) - - when( isTLWriteSoftReset(0+i) ){ - txLeft(i) := 0.U - } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - } .elsewhen( txFifo(i).io.enq.fire ){ - txLeft(i) := txLeft(i) + 1.U - } .elsewhen( txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - 1.U - } - - } - - - -} - - -trait RoCC2CDRImplRx{ this: RoCC2CDRImplBase => - - val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid } - val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } - val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } - val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } - val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } - val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } - val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } - val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } - - for( i <- 0 until 2 ) { - when( isTLWriteSoftReset(2+i) ){ - isAxisEnd(i) := false.B - } .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){ - isAxisEnd(i) := true.B - } - - when( isTLWriteSoftReset(2+i) ){ - rxCnt(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxCnt(i) := rxCnt(i) + 1.U - rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata ) - } - - when( isTLWriteSoftReset(2+i) ){ - rxLen(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxLen(i) := rxLen(i) + 1.U - } - - rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U - rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata ) - - assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) - - CDRIn(i).io.axis.ready := true.B - - rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - - rxFifo(i).io.deq.ready := isTLReadRxFifo(i) - - - when( isTLWriteSoftReset(2+i) ){ - isRxError(i) := false.B - } .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){ - isRxError(i) := true.B - printf(s"Warning, RxFifo$i Overflow!\n") - } - - when( isTLWriteSoftReset(2+i) ){ - rxLeft(i) := 0.U - } .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - } .elsewhen( rxFifo(i).io.enq.fire ){ - rxLeft(i) := rxLeft(i) + 1.U - } .elsewhen( rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - 1.U - } - } - - - - -} - -trait RoCC2CDRImplIsLast{ this: RoCC2CDRImplBase => - cdrOutio.isOnline := false.B - val isReadIsLast = Wire(Bool()) - -} - -trait RoCC2CDRImplUserCRC{ this: RoCC2CDRImplBase => - val isTLWriteTxFifo: Seq[Bool] - val isTLReadRxFifo: Seq[Bool] - - val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - - val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - - for( i <- 0 until 2 ) { - txCrc(i).io.enq.valid := isTLWriteTxFifo(i) - txCrc(i).io.enq.bits := wdata - - rxCrc(i).io.enq.valid := isTLReadRxFifo(i) - rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits - - txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - } - - - - -} - -trait RoCC2CDRImplLimitTimmer{ this: RoCC2CDRImplBase => - val intRxStart: Seq[Bool] - val isTLWriteSoftReset: Seq[Bool] - val isTxFifoRelease: Seq[Bool] - - val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) } - - for( i <- 0 until 2 ){ - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - limitTimerCnt(i) := 0.U - } .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){ - when( isLimitTimerTrigger(i) ){ - limitTimerCnt(i) := limitTimerCnt(i) + 1.U - } - } - - when( isTLWriteLimitTimerAim(i) ){ - limitTimerAim(i) := wdata - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - isLimitTimerTrigger(i) := false.B - } .elsewhen( intRxStart(i) ){ - isLimitTimerTrigger(i) := true.B - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - txPairSel(i) := i.U - } .elsewhen( isTLWriteLimitTxPair(i) ){ - txPairSel(i) := wdata - } - - - isTxFifoRelease(i) := ( 0 until 2).map{ lmt => - ((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt))) - }.reduce(_&_) - - } - -} - -trait RoCC2CDRImplOutTimmer{ this: RoCC2CDRImplBase => - val isTxBusy: Seq[Bool] - - val timeOutCnt = for( _ <- 0 until 2 ) yield { RegInit(0.U(32.W)) } - val isTLClearTimeOut = for( _ <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadTimeOut = for( _ <- 0 until 2 ) yield { Wire(Bool()) } - - val isTxClearTimeOut = for( i <- 0 until 2 ) yield { ~RegNext(isTxBusy(i)) & isTxBusy(i) } - - for( i <- 0 until 2 ) { - when( isTLClearTimeOut(i) | isTxClearTimeOut(i) ){ - timeOutCnt(i) := 0.U - } .otherwise{ - timeOutCnt(i) := timeOutCnt(i) + 1.U - } - } - - - - -} - - - - - - -class RoCC2CDRImpl(outer: RoCC2CDR)(implicit p: Parameters) extends RoCC2CDRImplBase(outer) -with RoCC2CDRImplTx with RoCC2CDRImplRx -with RoCC2CDRImplIsLast -with RoCC2CDRImplUserCRC -with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer -{ - - - - io.mem.req.valid := false.B - io.mem.req.bits := DontCare - io.mem.s1_kill := false.B - io.mem.s1_data := DontCare - io.mem.s2_kill := false.B - io.mem.keep_clock_enabled := false.B - - io.fpu_req.valid := false.B - io.fpu_req.bits := DontCare - io.fpu_resp.ready := true.B - - - - - - - - - - - - - - - - - isTLWriteSoftReset(0) := io.cmd.fire & io.cmd.bits.inst.funct === 0.U - isTLWriteTxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 1.U - isTLWriteTxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 2.U - isTLReadTxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 3.U - isTLClearTimeOut(0) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U & io.cmd.bits.inst.xs1 - isTLReadTimeOut(0) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U & io.cmd.bits.inst.xd - - isTLWriteSoftReset(1) := io.cmd.fire & io.cmd.bits.inst.funct === 5.U - isTLWriteTxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 6.U - isTLWriteTxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 7.U - isTLReadTxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 8.U - isTLClearTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xs1 - isTLReadTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xd - -//0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 - isTLWriteSoftReset(2) := io.cmd.fire & io.cmd.bits.inst.funct === 10.U - isTLReadRxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 11.U - isTLReadRxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 12.U - isTLReadRxFifoBypassTx(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U - isTLReadRxFifoBypassTx(1) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U - isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U - isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U - isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U - - isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U - isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U - isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 20.U - isTLReadRxFifoBypassTx(2) := io.cmd.fire & io.cmd.bits.inst.funct === 21.U - isTLReadRxFifoBypassTx(3) := io.cmd.fire & io.cmd.bits.inst.funct === 22.U - isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 23.U - isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 24.U - isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 25.U - - isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 26.U - val isTLReadInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 27.U & io.cmd.bits.inst.xd - val isTLClearInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 27.U & io.cmd.bits.inst.xs1 - val isTLWriteIntMask = io.cmd.fire & io.cmd.bits.inst.funct === 28.U - isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 29.U - - - - - - val interruptReg = RegInit(0.U(32.W)) - val interruptMask = RegEnable(wdata, 0.U(32.W), isTLWriteIntMask) - - val statusRxStart = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val statusRxEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val statusTxEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - - for( i <- 0 until 2 ){ - - when( isTLWriteSoftReset(2+i) ){ - statusRxStart(i) := false.B - } .elsewhen( intRxStart(i) ){ - statusRxStart(i) := true.B - } - - when( isTLWriteSoftReset(2+i) ){ - statusRxEnd(i) := false.B - } .elsewhen( intRxEnd(i) ){ - statusRxEnd(i) := true.B - } - - when( isTLWriteSoftReset(0+i) ){ - statusTxEnd(i) := false.B - } .elsewhen( intTxEnd(i) ){ - statusTxEnd(i) := true.B - } - } - - - when(true.B){ - interruptReg := - ( - (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat( - intTxEnd(1), intTxEnd(0), - intRxError(1), intRxError(0), - intRxStart(1), intRxStart(0), - intRxEnd(1), intRxEnd(0), - intTxFifoDeq(1), intTxFifoDeq(0), - intRxFifoEnq(1), intRxFifoEnq(0) - ) - ) & interruptMask - } - - - - - io.interrupt := - ( intTxEnd(1) & interruptMask.extract(11) ) | - ( intTxEnd(0) & interruptMask.extract(10) ) | - ( intRxError(1) & interruptMask.extract( 9) ) | - ( intRxError(0) & interruptMask.extract( 8) ) | - ( intRxStart(1) & interruptMask.extract( 7) ) | - ( intRxStart(0) & interruptMask.extract( 6) ) | - ( intRxEnd(1) & interruptMask.extract( 5) ) | - ( intRxEnd(0) & interruptMask.extract( 4) ) | - ( intTxFifoDeq(1) & interruptMask.extract( 3) ) | - ( intTxFifoDeq(0) & interruptMask.extract( 2) ) | - ( intRxFifoEnq(1) & interruptMask.extract( 1) ) | - ( intRxFifoEnq(0) & interruptMask.extract( 0) ) - - wdata := io.cmd.bits.rs1 - - val cmdInfo = RegEnable(io.cmd.bits, io.cmd.fire) - val rdata = Reg(UInt(32.W)) - - - // val cmdReady = RegInit(true.B) - val respValid = RegInit(false.B) - - io.busy := respValid - io.cmd.ready := ~respValid - - io.resp.valid := respValid - io.resp.bits.rd := cmdInfo.inst.rd - - io.resp.bits.data := rdata - - - - - - printf("Warning, no protection on tx rx fifo!\n") - // MuxCase( true.B, Array( - // ( io.cmd.bits.inst.funct === 2.U ) -> txFifo(0).io.enq.ready, - // ( io.cmd.bits.inst.funct === 6.U ) -> txFifo(1).io.enq.ready, - // ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, - // ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, - // )) - - - - - - - - when( isTLReadStatus ){ - rdata := Cat( - txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), - isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), - statusRxStart(1), statusRxStart(0), statusRxEnd(1), statusRxEnd(0), statusTxEnd(1), statusTxEnd(0) - ) - } .elsewhen(isTLReadRxLen(0) ){ - rdata := rxLen(0) - } .elsewhen(isTLReadRxLen(1) ){ - rdata := rxLen(1) - } .elsewhen(isTLReadRxFifo(0) | isTLReadRxFifoBypassTx(0) | isTLReadRxFifoBypassTx(1) ){ - rdata := rxFifo(0).io.deq.bits - } .elsewhen(isTLReadRxFifo(1) | isTLReadRxFifoBypassTx(2) | isTLReadRxFifoBypassTx(3) ){ - rdata := rxFifo(1).io.deq.bits - } .elsewhen(isReadIsLast){ - rdata := cdrInio.isLast - } .elsewhen(isTLReadTxCrc(0)){ - rdata := txCrc(0).io.crc - } .elsewhen(isTLReadTxCrc(1)){ - rdata := txCrc(1).io.crc - } .elsewhen(isTLReadRxCrc(0)){ - rdata := rxCrc(0).io.crc - } .elsewhen(isTLReadRxCrc(1)){ - rdata := rxCrc(1).io.crc - } .elsewhen(isTLReadInterrupt){ - rdata := interruptReg - } .elsewhen(isTLReadTimeOut(0)){ - rdata := timeOutCnt(0) - } .elsewhen(isTLReadTimeOut(1)){ - rdata := timeOutCnt(1) - } - - - when( io.resp.fire ){ //允许连续触发 - respValid := false.B - } .elsewhen( isTLReadStatus ){ - respValid := true.B - } .elsewhen(isTLReadRxLen(0) ){ - respValid := true.B - } .elsewhen(isTLReadRxLen(1) ){ - respValid := true.B - } .elsewhen(isTLReadRxFifo(0) | isTLReadRxFifoBypassTx(0) | isTLReadRxFifoBypassTx(1) ){ - respValid := true.B - } .elsewhen(isTLReadRxFifo(1) | isTLReadRxFifoBypassTx(2) | isTLReadRxFifoBypassTx(3) ){ - respValid := true.B - } .elsewhen(isReadIsLast){ - respValid := true.B - } .elsewhen(isTLReadTxCrc(0)){ - respValid := true.B - } .elsewhen(isTLReadTxCrc(1)){ - respValid := true.B - } .elsewhen(isTLReadRxCrc(0)){ - respValid := true.B - } .elsewhen(isTLReadRxCrc(1)){ - respValid := true.B - } .elsewhen(isTLReadInterrupt){ - respValid := true.B - } .elsewhen(isTLReadTimeOut(0)){ - respValid := true.B - } .elsewhen(isTLReadTimeOut(1)){ - respValid := true.B - } - -} - - -trait HasLazyRoCC2CDR { this: BaseTile => - val roccs = LazyModule(new RoCC2CDR()) - - val roccCSRs = Seq(roccs.roccCSRs) // the set of custom CSRs requested by all roccs -} - -trait HasLazyRoCC2CDRModule extends HasCoreParameters { this: RocketTileModuleImp with HasFpuOpt => - - // val (respArb, cmdRouter) = { - // val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) - val cmdRouter = Module(new Queue( new RoCCCommand, 2, false, true ))//Module(new RoccCommandRouter( Seq(outer.roccs.opcodes) )(outer.p)) - - // outer.roccs.module.io.ptw ++=: ptwPorts - outer.roccs.module.io.cmd <> cmdRouter.io.deq - // val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) - // dcIF.io.requestor <> outer.roccs.module.io.mem - // dcachePorts += dcIF.io.cache - //respArb.io.in(0) <> Queue(outer.roccs.module.io.resp) - - - fpuOpt foreach { fpu => - fpu.io.cp_req.valid := false.B - fpu.io.cp_resp.ready := false.B - } - - // (Some(respArb), Some(cmdRouter)) - // } - - // val roccCSRIOs = Seq(outer.roccs.module.io.csrs) - - // (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 := t._1 } - - val cdrInio = IO(Input(new RocCC2CDRInIO)) - val cdrOutio = IO(Output(new RocCC2CDROutIO)) - - // val cdrio: RoCC2CDRIO = IO(new RoCC2CDRIO) - // dontTouch(cdrio) - - - cdrInio <> outer.roccs.module.cdrInio - cdrOutio <> outer.roccs.module.cdrOutio - -} - diff --git a/src/main/scala/backBoard/ebus/SpiSlv.scala.bk b/src/main/scala/backBoard/ebus/SpiSlv.scala.bk deleted file mode 100644 index 68170e6..0000000 --- a/src/main/scala/backBoard/ebus/SpiSlv.scala.bk +++ /dev/null @@ -1,89 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -class CDR_Master_Interface_Bundle extends CDRData{ - val op = UInt(2.W) -} - -class SpiSlvIO extends Bundle{ - val CS = Input(Bool()) - val MISO = Output(Bool()) - val MOSI = Input(Bool()) - val SCK = Input(Bool()) - - val clk4 = Input(Bool()) - - val CDRIn = Flipped(Decoupled(new CDRData)) - val CDROut = Decoupled(new CDRData) - -} - -class SpiSlv extends Module{ - val io: SpiSlvIO = IO(new SpiSlvIO) - - val CDROutValidSet = Wire(Bool()) - val CDROutValidSetAsync = ShiftRegister(CDROutValidSet, 2, false.B, true.B) - val CDROutValidReset = RegNext(CDROutValidSetAsync, false.B) - - // val CDRInValidSet = RegInit(false.B) - val CDRInValidReset = Wire(Bool()) - val CDRInValidResetAsync = ShiftRegister( CDRInValidReset, 2, false.B, true.B) - - val cent = Wire(new CDR_Master_Interface_Bundle) - withClockAndReset( io.clk4.asClock, reset ){ - val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg - val sckShift = ShiftRegisters( io.SCK, 3, false.B, true.B ) - val csShift = ShiftRegisters( io.CS, 3, true.B, true.B ) - val mosiShift = ShiftRegisters( io.MOSI, 2, true.B, true.B ) - - - val CDROutValidSetReg = RegInit(false.B); CDROutValidSet := CDROutValidSetReg - val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B ) - - val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B ) - val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(1) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg - - when( CDROutValidSetReg & CDROutValidResetAsync ){ - CDROutValidSetReg := false.B - centReg.op := 1.U - } .elsewhen( ~csShift(2) & csShift(1) ){ - CDROutValidSetReg := true.B - } - - io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 ) - - val sckPosedge = ~sckShift(2) & sckShift(1) - val sckNegedge = sckShift(2) & ~sckShift(1) - - when( ~csShift(1) ){ - when( sckPosedge ){ - centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), mosiShift(1)).asTypeOf(new CDR_Master_Interface_Bundle) - } - } .otherwise{ - when( CDRInValidSetAsync & ~CDROutValidSetReg ){ - centReg.address := io.CDRIn.bits.address - centReg.register := io.CDRIn.bits.register - centReg.data := io.CDRIn.bits.data - centReg.op := 0.U - } - } - } - - val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid - val CDROutInfo = Reg(new CDRData); io.CDROut.bits := CDROutInfo - - when( io.CDROut.fire ){ - CDROutValid := false.B - } .elsewhen( CDROutValidSet & ~CDROutValidSetAsync ){ - CDROutValid := true.B - CDROutInfo := cent - } - - io.CDRIn.ready := CDRInValidResetAsync - -} - - diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala.bk b/src/main/scala/backBoard/ebus/TL2CDR.scala.bk deleted file mode 100644 index fc40bde..0000000 --- a/src/main/scala/backBoard/ebus/TL2CDR.scala.bk +++ /dev/null @@ -1,456 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ - - -class TL2CDR(implicit p: Parameters) extends LazyModule{ - val device = new SimpleDevice("TL_CDR", Nil) - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - managers = Seq( - TLSlaveParameters.v2( - address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K - name = Some("TL_CDR"), - regionType = RegionType.VOLATILE, - resources = device.reg, - executable = false, - fifoId = Some(0), - supports = TLMasterToSlaveTransferSizes( - get = TransferSizes(1, 32/8), - putFull = TransferSizes(1, 32/8), - putPartial = TransferSizes(1, 32/8), - ), - ) - ), - beatBytes = 32/8))) - - val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int)) - - lazy val module: TL2CDRImpl = new TL2CDRImpl(this) -} - - - - - -abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) { - class TLCDRIO extends Bundle{ - val overCLK = Input(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) - } - - val io: TLCDRIO = IO(new TLCDRIO) - - val ( int, _ ) = outer.int_node.out(0) - val ( bus, edge ) = outer.node.in.head - - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } - when(true.B){ - print("Warning!!! New Code has not been reviewed!\n") - } - - CDRIn(0).io.serDat := io.dDatIn - CDRIn(1).io.serDat := io.uDatIn - - CDRIn(0).overCLK := io.overCLK - CDRIn(1).overCLK := io.overCLK - - val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } - - io.dDatOut := CDROut(0).io.serDat - io.uDatOut := CDROut(1).io.serDat - - val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - - val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } - val isTLReadStatus = Wire( Bool() ) - - val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - -} - - -trait TL2CDRImplTx{ this: TL2CDRImplBase => - - - val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) } - - - val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready } - val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) } - val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast } - val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) } - - val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire } - // println("Warning, TxEnd no confident\n") - - - val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) } - val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } - - for( i <- 0 until 2 ) { - when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U - txData(i) := txFifo(i).io.deq.bits - when( isTxBusy(i) ){ - assert(CDROut(i).io.axis.fire) - } - } .elsewhen( CDROut(i).io.axis.fire ){ - txData(i) := txData(i) << 8 - } - - txFifo(i).io.deq.ready := - isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B ) - - txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - - CDROut(i).io.axis.bits.tdata := txData(i).head(8) - CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U - CDROut(i).io.axis.bits.tuser := false.B - CDROut(i).io.axis.valid := isTxBusy(i) - - - when( isTLWriteSoftReset(i) ){ - isTxBusy(i) := false.B - }.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){ - isTxBusy(i) := true.B - } .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){ - isTxBusy(i) := false.B - } - - - when( isTLWriteSoftReset(0+i) ){ - txCnt(i) := 0.U - } .elsewhen( CDROut(i).io.axis.fire ){ - txCnt(i) := txCnt(i) + 1.U - } - - - when( isTLWriteTxLen(i) ){ - txLen(i) := bus.a.bits.data - } .elsewhen( CDROut(i).io.axis.fire ){ - txLen(i) := txLen(i) - 1.U - } - - txFifo(i).io.enq.bits := bus.a.bits.data - txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U - - when( isTLWriteSoftReset(0+i) ){ - txLeft(i) := 0.U - } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - } .elsewhen( txFifo(i).io.enq.fire ){ - txLeft(i) := txLeft(i) + 1.U - } .elsewhen( txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - 1.U - } - - } - - - -} - - -trait TL2CDRImplRx{ this: TL2CDRImplBase => - - val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid } - val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } - val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } - val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } - val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } - val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } - val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } - val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } - - for( i <- 0 until 2 ) { - when( isTLWriteSoftReset(2+i) ){ - isAxisEnd(i) := false.B - } .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){ - isAxisEnd(i) := true.B - } - - when( isTLWriteSoftReset(2+i) ){ - rxCnt(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxCnt(i) := rxCnt(i) + 1.U - rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata ) - } - - when( isTLWriteSoftReset(2+i) ){ - rxLen(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxLen(i) := rxLen(i) + 1.U - } - - rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U - rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata ) - - assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) - - CDRIn(i).io.axis.ready := true.B - - rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - - rxFifo(i).io.deq.ready := isTLReadRxFifo(i) - - - when( isTLWriteSoftReset(2+i) ){ - isRxError(i) := false.B - } .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){ - isRxError(i) := true.B - printf(s"Warning, RxFifo$i Overflow!\n") - } - - when( isTLWriteSoftReset(2+i) ){ - rxLeft(i) := 0.U - } .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - } .elsewhen( rxFifo(i).io.enq.fire ){ - rxLeft(i) := rxLeft(i) + 1.U - } .elsewhen( rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - 1.U - } - } - - - - -} - -trait TL2CDRImplIsLast{ this:TL2CDRImplBase => - io.isOnline := false.B - val isReadIsLast = Wire(Bool()) - -} - -trait TL2CDRImplUserCRC{ this: TL2CDRImplBase => - val isTLWriteTxFifo: Seq[Bool] - val isTLReadRxFifo: Seq[Bool] - - val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - - val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - - for( i <- 0 until 2 ) { - txCrc(i).io.enq.valid := isTLWriteTxFifo(i) - txCrc(i).io.enq.bits := bus.a.bits.data - - rxCrc(i).io.enq.valid := isTLReadRxFifo(i) - rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits - - txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - } - - - - -} - -trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase => - val intRxStart: Seq[Bool] - val isTLWriteSoftReset: Seq[Bool] - val isTxFifoRelease: Seq[Bool] - - val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) } - - for( i <- 0 until 2 ){ - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - limitTimerCnt(i) := 0.U - } .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){ - when( isLimitTimerTrigger(i) ){ - limitTimerCnt(i) := limitTimerCnt(i) + 1.U - } - } - - when( isTLWriteLimitTimerAim(i) ){ - limitTimerAim(i) := bus.a.bits.data - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - isLimitTimerTrigger(i) := false.B - } .elsewhen( intRxStart(i) ){ - isLimitTimerTrigger(i) := true.B - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - txPairSel(i) := i.U - } .elsewhen( isTLWriteLimitTxPair(i) ){ - txPairSel(i) := bus.a.bits.data - } - - - isTxFifoRelease(i) := ( 0 until 2).map{ lmt => - ((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt))) - }.reduce(_&_) - - } - -} - - - - - - - - -class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer) -with TL2CDRImplTx with TL2CDRImplRx -with TL2CDRImplIsLast -with TL2CDRImplUserCRC -with TL2CDRImplLimitTimmer -{ - - isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(7,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h0c".U & bus.a.bits.opcode === 4.U - - isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(7,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h1c".U & bus.a.bits.opcode === 4.U - - isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(7,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h24".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h28".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h2c".U & bus.a.bits.opcode === 4.U - isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(7,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(7,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - - isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(7,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h44".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h48".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h4c".U & bus.a.bits.opcode === 4.U - isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(7,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(7,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - - isTLReadStatus := bus.a.fire & bus.a.bits.address(7,0) === "h58".U & ( bus.a.bits.opcode === 4.U ) - isReadIsLast := bus.a.fire & bus.a.bits.address(7,0) === "h5c".U & ( bus.a.bits.opcode === 4.U ) - - int(0) := intTxEnd(0) - int(1) := intTxEnd(1) - - int(2) := intRxError(0) - int(3) := intRxError(1) - - int(4) := intRxStart(0) - int(5) := intRxStart(1) - - int(6) := intRxEnd(0) - int(7) := intRxEnd(1) - - int(8) := intTxFifoDeq(0) - int(9) := intTxFifoDeq(1) - - int(10) := intRxFifoEnq(0) - int(11) := intRxFifoEnq(1) - - - - - val tlaInfo = Reg(new TLBundleA(edge.bundle)) - val rdata = Reg(UInt(32.W)) - val tlAReady = RegInit(true.B) - val tlDValid = RegInit(false.B) - - val isRead = tlaInfo.opcode === 4.U - - - - - - bus.a.ready := - tlAReady & - MuxCase( true.B, Array( - ( bus.a.bits.address(7,0) === "h08".U ) -> txFifo(0).io.enq.ready, - ( bus.a.bits.address(7,0) === "h18".U ) -> txFifo(1).io.enq.ready, - ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, - ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, - )) - - - bus.d.valid := tlDValid - - - - - when( bus.a.fire ) { - tlaInfo := bus.a.bits - } - - when( bus.a.fire ){ - tlAReady := false.B - tlDValid := true.B - } .elsewhen( bus.d.fire ) { - tlAReady := true.B - tlDValid := false.B - } - - when(isRead) { - bus.d.bits := edge.AccessAck(tlaInfo, rdata) - } .otherwise { - bus.d.bits := edge.AccessAck(tlaInfo) - } - - - when( isTLReadStatus ){ - rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) ) - } .elsewhen(isTLReadRxLen(0) ){ - rdata := rxLen(0) - } .elsewhen(isTLReadRxLen(1) ){ - rdata := rxLen(1) - } .elsewhen(isTLReadRxFifo(0) ){ - rdata := rxFifo(0).io.deq.bits - } .elsewhen(isTLReadRxFifo(1) ){ - rdata := rxFifo(1).io.deq.bits - } .elsewhen(isReadIsLast){ - rdata := io.isLast - } .elsewhen(isTLReadTxCrc(0)){ - rdata := txCrc(0).io.crc - } .elsewhen(isTLReadTxCrc(1)){ - rdata := txCrc(1).io.crc - } .elsewhen(isTLReadRxCrc(0)){ - rdata := rxCrc(0).io.crc - } .elsewhen(isTLReadRxCrc(1)){ - rdata := rxCrc(1).io.crc - } - -} - - diff --git a/src/main/scala/backBoard/goWinBus.scala b/src/main/scala/backBoard/goWinBus.scala deleted file mode 100644 index 939c063..0000000 --- a/src/main/scala/backBoard/goWinBus.scala +++ /dev/null @@ -1,304 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - -class CRC_ERR_Bundle extends Bundle{ - val crc_err = Bool() - val crc_err_count = UInt(8.W) - val cdr_err = Bool() -} - -class Lvds_Bus_MasterIO extends Bundle{ - val rst_n = Input(Bool()) -val reset_calib = Input(Bool()) - val oser_pclk = Input(Bool()) - val oser_fclk = Input(Bool()) - val ides_pclk = Input(Bool()) - val ides_fclk = Input(Bool()) - - val lvds_down_dout = Output(Bool()) - val lvds_up_din = Input(Bool()) - - val frame_info_update_en = Input(Bool()) - val slave_type_num = Input(UInt(8.W)) - val slave_data_length = Input(UInt(8.W)) - -val slave_link_num_valid = Output(Bool()) -val slave_link_num = Output(UInt(7.W)) - - val tx_start = Input(Bool()) - val tx_data_in = Input(UInt(8.W)) - val tx_data_ready = Output(Bool()) - val downstream_busy = Output(Bool()) - val rx_data_out = Output(UInt(8.W)) - val rx_data_valid = Output(Bool()) - - val upstream_crc_valid = Output(Bool()) - val upstream_crc_err = Output(Bool()) - val upstream_crc_err_count = Output(UInt(8.W)) - - val upstream_cdr_err = Output(Bool()) - -val closed_loop_err = Output(Bool()) -val link_err_location = Output(UInt(7.W)) - -val test_downstream_tx_en = Output(Bool()) -val test_downstream_tx_8b_data = Output(UInt(8.W)) -val test_downstream_tx_10b_data = Output(UInt(10.W)) -val test_upstream_rx_busy = Output(Bool()) -val test_upstream_rx_10b_data = Output(UInt(10.W)) -val test_upstream_rx_8b_data = Output(UInt(8.W)) -} - -class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline { - - val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO) - - setInline("lvds_Bus_Master.v", - """ - | module Lvds_Bus_Master( - | input rst_n, - | input reset_calib, - | input oser_pclk, - | input oser_fclk, - | input ides_pclk, - | input ides_fclk, - | output lvds_down_dout, - | input lvds_up_din, - | input frame_info_update_en, - | input [7:0] slave_type_num, - | input [7:0] slave_data_length, - | - | output slave_link_num_valid, - | output [6:0] slave_link_num, - | - | input tx_start, - | input [7:0] tx_data_in, - | output tx_data_ready, - | output downstream_busy, - | output [7:0] rx_data_out, - | output rx_data_valid, - | output upstream_crc_valid, - | output upstream_crc_err, - | output [7:0] upstream_crc_err_count, - | output upstream_cdr_err, - | - | output closed_loop_err, - | output [6:0] link_err_location, - | - | output test_downstream_tx_en, - | output [7:0] test_downstream_tx_8b_data, - | output [9:0] test_downstream_tx_10b_data, - | output test_upstream_rx_busy, - | output [9:0] test_upstream_rx_10b_data, - | output [7:0] test_upstream_rx_8b_data - | ); - | - | lvds_bus_master_top i_lvds_bus_master( - | .rst_n(rst_n), //input - | .reset_calib(reset_calib), //input - | .oser_pclk(oser_pclk), //input - | .oser_fclk(oser_fclk), //input - | .ides_pclk(ides_pclk), //input - | .ides_fclk(ides_fclk), //input - | - | .lvds_down_dout(lvds_down_dout), //output - | .lvds_up_din(lvds_up_din), //input - | - | .frame_info_update_en(frame_info_update_en), //input - | .slave_type_num(slave_type_num), //input [7:0] - | .slave_data_length(slave_data_length), //input [7:0] - | - | .slave_link_num_valid(slave_link_num_valid), //output - | .slave_link_num(slave_link_num), //output [6:0] - | - | .tx_start(tx_start), //input - | .tx_data_in(tx_data_in), //input [7:0] - | .tx_data_ready(tx_data_ready), //output - | .downstream_busy(downstream_busy), //output - | .rx_data_out(rx_data_out), //output [7:0] - | .rx_data_valid(rx_data_valid), //output - | .upstream_crc_valid(upstream_crc_valid), //output - | .upstream_crc_err(upstream_crc_err), //output - | .upstream_crc_err_count(upstream_crc_err_count), //output [7:0] - | .upstream_cdr_err(upstream_cdr_err), //output - | - | .closed_loop_err(closed_loop_err), //output - | .link_err_location(link_err_location), //output [6:0] - | - | .test_downstream_tx_en(test_downstream_tx_en), //output - | .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output [7:0] - | .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output [9:0] - | .test_upstream_rx_busy(test_upstream_rx_busy), //output - | .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output [9:0] - | .test_upstream_rx_8b_data(test_upstream_rx_8b_data) //output [7:0] - | ); - |endmodule - """.stripMargin) -} - - - - - - - - - - - - - - - -class Lvds_Bus_SlaveIO extends Bundle{ - val rst_n = Input(Bool()) -val reset_calib = Input(Bool()) - val oser_pclk = Input(Bool()) - val oser_fclk = Input(Bool()) - val ides_pclk = Input(Bool()) - val ides_fclk = Input(Bool()) - - - val lvds_down_din = Input(Bool()) - val lvds_down_dout = Output(Bool()) - val lvds_up_din = Input(Bool()) - val lvds_up_dout = Output(Bool()) - - val downstream_rx_data_valid = Output(Bool()) - val downstream_rx_data_out = Output(UInt(8.W)) - val downstream_rx_crc_valid = Output(Bool()) - val downstream_rx_crc_err = Output(Bool()) - val downstream_rx_crc_err_counter = Output(UInt(8.W)) - val downstream_rx_cdr_err = Output(Bool()) - val downstream_sync = Output(Bool()) - - val upstream_tx_data_ready = Output(Bool()) - val upstream_tx_data_in = Input(UInt(8.W)) - - val upstream_rx_crc_valid = Output(Bool()) - val upstream_rx_crc_err = Output(Bool()) - val upstream_rx_crc_err_counter = Output(UInt(8.W)) - val upstream_rx_cdr_err = Output(Bool()) - -val local_slave_id = Output(UInt(7.W)) -val test_downstream_rx_10b_data = Output(UInt(10.W)) -val test_downstream_rx_8b_data = Output(UInt(8.W)) -val test_downstream_rx_state_machine = Output(UInt(4.W)) -val test_downstream_tx_en = Output(Bool()) -val test_downstream_tx_8b_data = Output(UInt(8.W)) -val test_downstream_tx_10b_data = Output(UInt(10.W)) -val test_upstream_rx_10b_data = Output(UInt(10.W)) -val test_upstream_rx_8b_data = Output(UInt(8.W)) -val test_upstream_rx_state_machine = Output(UInt(4.W)) -val test_upstream_tx_en = Output(Bool()) -val test_upstream_tx_8b_data = Output(UInt(8.W)) -val test_upstream_tx_10b_data = Output(UInt(10.W)) -} - - - -class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline { - val io: Lvds_Bus_SlaveIO = IO(new Lvds_Bus_SlaveIO) - - setInline("Lvds_Bus_Slave.v", - """ - module Lvds_Bus_Slave( - | input rst_n, - | input reset_calib, - | input oser_pclk, - | input oser_fclk, - | input ides_pclk, - | input ides_fclk, - | - | input lvds_down_din, - | output lvds_down_dout, - | input lvds_up_din, - | output lvds_up_dout, - | - | output downstream_rx_data_valid, - | output downstream_rx_unicast_pkg_valid, - | output [7:0] downstream_rx_data_out, - | output downstream_rx_crc_valid, - | output downstream_rx_crc_err, - | output [7:0] downstream_rx_crc_err_counter, - | output downstream_rx_cdr_err, - | output downstream_sync, - | output upstream_tx_data_ready, - | output upstream_tx_unicast_pkg_ready, - | input [7:0] upstream_tx_data_in, - | output upstream_rx_crc_valid, - | output upstream_rx_crc_err, - | output [7:0] upstream_rx_crc_err_counter, - | output upstream_rx_cdr_err, - | - | output [6:0] local_slave_id, - | output [9:0] test_downstream_rx_10b_data, - | output [7:0] test_downstream_rx_8b_data, - | output [3:0] test_downstream_rx_state_machine, - | output test_downstream_tx_en, - | output [7:0] test_downstream_tx_8b_data, - | output [9:0] test_downstream_tx_10b_data, - | output [9:0] test_upstream_rx_10b_data, - | output [7:0] test_upstream_rx_8b_data, - | output [3:0] test_upstream_rx_state_machine, - | output test_upstream_tx_en, - | output [7:0] test_upstream_tx_8b_data, - | output [9:0] test_upstream_tx_10b_data - |); - | - | lvds_bus_slave_top i_lvds_bus_slave( - | .rst_n(rst_n), - | .reset_calib(reset_calib), - | .oser_pclk(oser_pclk), - | .oser_fclk(oser_fclk), - | .ides_pclk(ides_pclk), - | .ides_fclk(ides_fclk), - | - | .lvds_down_din(lvds_down_din), - | .lvds_down_dout(lvds_down_dout), - | .lvds_up_din(lvds_up_din), - | .lvds_up_dout(lvds_up_dout), - | - | .downstream_rx_data_valid(downstream_rx_data_valid), - | .downstream_rx_unicast_pkg_valid(downstream_rx_unicast_pkg_valid), - | .downstream_rx_data_out(downstream_rx_data_out), - | .downstream_rx_crc_valid(downstream_rx_crc_valid), - | .downstream_rx_crc_err(downstream_rx_crc_err), - | .downstream_rx_crc_err_counter(downstream_rx_crc_err_counter), - | .downstream_rx_cdr_err(downstream_rx_cdr_err), - | .downstream_sync(downstream_sync), - | .upstream_tx_data_ready(upstream_tx_data_ready), - | .upstream_tx_unicast_pkg_ready(upstream_tx_unicast_pkg_ready), - | .upstream_tx_data_in(upstream_tx_data_in), - | .upstream_rx_crc_valid(upstream_rx_crc_valid), - | .upstream_rx_crc_err(upstream_rx_crc_err), - | .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter), - | .upstream_rx_cdr_err(upstream_rx_cdr_err), - | - | .local_slave_id(local_slave_id), //output[6:0] - | .test_downstream_rx_10b_data(test_downstream_rx_10b_data), //output[9:0] - | .test_downstream_rx_8b_data(test_downstream_rx_8b_data), //output[7:0] - | .test_downstream_rx_state_machine(test_downstream_rx_state_machine), //output[3:0] - | .test_downstream_tx_en(test_downstream_tx_en), //output - | .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output[7:0] - | .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output[9:0] - | .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output[9:0] - | .test_upstream_rx_8b_data(test_upstream_rx_8b_data), //output[7:0] - | .test_upstream_rx_state_machine(test_upstream_rx_state_machine), //output[3:0] - | .test_upstream_tx_en(test_upstream_tx_en), //output - | .test_upstream_tx_8b_data(test_upstream_tx_8b_data), //output[7:0] - | .test_upstream_tx_10b_data(test_upstream_tx_10b_data) //output[9:0] - | ); - |endmodule - """.stripMargin) -} - - - //Test Signal// - - - diff --git a/src/main/scala/backBoard/pico/BackSystem.scala.bk b/src/main/scala/backBoard/pico/BackSystem.scala.bk deleted file mode 100644 index 8d31482..0000000 --- a/src/main/scala/backBoard/pico/BackSystem.scala.bk +++ /dev/null @@ -1,123 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.gpio._ - - - - - - - - - - - - - - - -class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters { - - - lazy val module: BackSysImp = new BackSysImp(this) -} - -class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParameters { - class BackSysIO extends Bundle{ - val overCLK = Input(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - - val out = Output(UInt(32.W)) - val in = Input(UInt(32.W)) - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) - val DCIn = Input(Bool()) - } - - - val io: BackSysIO = IO(new BackSysIO) - - val pico = Module(new Picorv32_mem ) - val cdr = Module(new TLCDR() ) - val gpio = Module(new SimpleGpio() ) - val sram = Module(new SimpleSRAM) - - - pico.io.irq := Cat( io.DCIn, cdr.io.interrupt.asUInt ) - - - io.out := gpio.io.out - gpio.io.in := io.in - - io.isOnline := gpio.io.isOnline - gpio.io.isLast := io.isLast - - - - - cdr.io.overCLK := io.overCLK - - cdr.io.dDatIn := io.dDatIn - io.dDatOut := cdr.io.dDatOut - cdr.io.uDatIn := io.uDatIn - io.uDatOut := cdr.io.uDatOut - - io.out := gpio.io.out - - - - - sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U - cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b0".U & ~pico.io.mem.instr - gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b1".U & ~pico.io.mem.instr - - pico.io.mem.ready := - Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready, - Mux1H(Seq( - ( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.ready, - ( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.ready, - )) - ) - pico.io.mem.rdata := - Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.rdata, - Mux1H(Seq( - ( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.rdata, - ( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.rdata, - )) - ) - - sram.io.mem.wdata := pico.io.mem.wdata - cdr.io.mem.wdata := pico.io.mem.wdata - gpio.io.mem.wdata := pico.io.mem.wdata - - sram.io.mem.wstrb := pico.io.mem.wstrb - cdr.io.mem.wstrb := pico.io.mem.wstrb - gpio.io.mem.wstrb := pico.io.mem.wstrb - - sram.io.mem.addr := pico.io.mem.addr(11,0) - cdr.io.mem.addr := pico.io.mem.addr(11,0) - gpio.io.mem.addr := pico.io.mem.addr(11,0) - - sram.io.mem.instr := pico.io.mem.instr - cdr.io.mem.instr := false.B - gpio.io.mem.instr := false.B - - - assert( pico.io.mem.wstrb.andR | ~pico.io.mem.wstrb.orR ) - - - - -} \ No newline at end of file diff --git a/src/main/scala/backBoard/pico/Picorv32_mem.scala.bk b/src/main/scala/backBoard/pico/Picorv32_mem.scala.bk deleted file mode 100644 index 956453f..0000000 --- a/src/main/scala/backBoard/pico/Picorv32_mem.scala.bk +++ /dev/null @@ -1,60 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -class Mem_Port_Bundle extends Bundle{ - val valid = Output(Bool()) - val ready = Input(Bool()) - val instr = Output(Bool()) - - val addr = Output(UInt(32.W)) - val wdata = Output(UInt(32.W)) - val wstrb = Output(UInt(4.W)) - val rdata = Input(UInt(32.W)) - - def fire = valid & ready -} - - - - -class Picorv32_mem()(implicit p: Parameters) extends BackModule{ - class Picorv32IO_mem extends Bundle{ - - val mem = new Mem_Port_Bundle - - val irq = Input(UInt(32.W)) - - } - - val io: Picorv32IO_mem = IO(new Picorv32IO_mem) - - val core = Module(new picorv32) - - core.io.clk := clock.asBool - core.io.resetn := ~reset.asBool - - core.io.pcpi_wr := false.B - core.io.pcpi_rd := 0.U - core.io.pcpi_wait := false.B - core.io.pcpi_ready := true.B - - core.io.irq := io.irq - - io.mem.valid := core.io.mem_valid - core.io.mem_ready := io.mem.ready - - io.mem.addr := core.io.mem_addr - io.mem.wdata := core.io.mem_wdata - io.mem.wstrb := core.io.mem_wstrb - io.mem.instr := core.io.mem_instr - core.io.mem_rdata := io.mem.rdata -} - - - diff --git a/src/main/scala/backBoard/pico/Picorv32_tl.scala.bk b/src/main/scala/backBoard/pico/Picorv32_tl.scala.bk deleted file mode 100644 index 3fbeba1..0000000 --- a/src/main/scala/backBoard/pico/Picorv32_tl.scala.bk +++ /dev/null @@ -1,79 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{ - class Picorv32IO_tl extends Bundle{ - val trap = Output(Bool()) - - val tla = new DecoupledIO(new TLBundleA(edge.bundle)) - val tld = Flipped(new DecoupledIO(new TLBundleD(edge.bundle))) - - val irq = Input(UInt(32.W)) - val eoi = Output(UInt(32.W)) - } - - val io: Picorv32IO_tl = IO(new Picorv32IO_tl) - - val core = Module(new picorv32) - - core.io.clk := clock.asBool - core.io.resetn := ~reset.asBool - io.trap := core.io.trap - - core.io.pcpi_wr := false.B - core.io.pcpi_rd := 0.U - core.io.pcpi_wait := false.B - core.io.pcpi_ready := true.B - - core.io.irq := io.irq - io.eoi := core.io.eoi - - // val tlStateNext = Wire( UInt(2.W) ) - // val tlStateCurr = RegNext(tlStateNext, 0.U) - - // tlStateNext := Mux1H(Seq( - // (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE - // (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE - // (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE - // )) - - val isTlaValidAck = RegInit(true.B) - - when( io.tla.fire ){ - isTlaValidAck := false.B - } .elsewhen( io.tld.fire ){ - isTlaValidAck := true.B - } - - core.io.mem_ready := io.tld.fire - core.io.mem_rdata := io.tld.bits.data - io.tld.ready := true.B - io.tla.valid := isTlaValidAck & core.io.mem_valid - - when( core.io.mem_wstrb.orR ){ - io.tla.bits := - edge.Put( - fromSource = 0.U, - toAddress = core.io.mem_addr, - lgSize = log2Ceil(32/8).U, - data = core.io.mem_wdata, - mask = core.io.mem_wstrb - )._2 - } .otherwise{ - io.tla.bits := - edge.Get( - fromSource = 0.U, - toAddress = core.io.mem_addr, - lgSize = log2Ceil(32/8).U - )._2 - } -} - - - diff --git a/src/main/scala/backBoard/pico/SimpleGpio.scala.bk b/src/main/scala/backBoard/pico/SimpleGpio.scala.bk deleted file mode 100644 index 640cc6e..0000000 --- a/src/main/scala/backBoard/pico/SimpleGpio.scala.bk +++ /dev/null @@ -1,42 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - -class SimpleGpio()(implicit p: Parameters) extends BackModule{ - class SimpleGpioIO extends Bundle{ - val mem = Flipped(new Mem_Port_Bundle) - - val out = Output(UInt(32.W)) - val in = Input(UInt(32.W)) - - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) - - } - - val io: SimpleGpioIO = IO(new SimpleGpioIO) - - val isWriteGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb =/= 0.U - val isReadGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb === 0.U - // val isWriteDir = io.mem.fire & io.mem.addr(3,0) === "h4".U & io.mem.wstrb =/= 0.U - val isReadIsLast = io.mem.fire & io.mem.addr(3,0) === "h8".U & io.mem.wstrb === 0.U - - - io.isOnline := false.B - - io.out := RegEnable( io.mem.wdata, 0.U(32.W), isWriteGpio ) - - io.mem.ready := true.B - io.mem.rdata := - Mux( io.mem.addr(3,0) === "h0".U, io.in, - Mux( io.mem.addr(3,0) === "h8".U, io.isLast, 0.U ) ) - -} - diff --git a/src/main/scala/backBoard/pico/SimpleSRAM.scala.bk b/src/main/scala/backBoard/pico/SimpleSRAM.scala.bk deleted file mode 100644 index 16fa6cd..0000000 --- a/src/main/scala/backBoard/pico/SimpleSRAM.scala.bk +++ /dev/null @@ -1,42 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - -class SimpleSRAM()(implicit p: Parameters) extends BackModule{ - class SimpleSRAMIO extends Bundle{ - val mem = Flipped(new Mem_Port_Bundle) - } - - val io: SimpleSRAMIO = IO(new SimpleSRAMIO) - - val mem = SyncReadMem(1024, UInt(32.W)) - - - io.mem.rdata := DontCare - - when( io.mem.valid & io.mem.wstrb.extract(0) ){ - mem.write( io.mem.addr(11,2), io.mem.wdata ) - - assert( io.mem.wstrb.extract(1) & io.mem.wstrb.extract(2) & io.mem.wstrb.extract(3) ) - } - - io.mem.rdata := mem.read(io.mem.addr(11,2), true.B) - - val isReadAck = RegInit(false.B) - when( io.mem.fire ){ - isReadAck := false.B - } .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){ - isReadAck := true.B - } - - io.mem.ready := - ( io.mem.wstrb =/= 0.U & true.B ) | - ( io.mem.wstrb === 0.U & isReadAck ) - -} diff --git a/src/main/scala/backBoard/pico/TLCDR.scala.bk b/src/main/scala/backBoard/pico/TLCDR.scala.bk deleted file mode 100644 index c4105bd..0000000 --- a/src/main/scala/backBoard/pico/TLCDR.scala.bk +++ /dev/null @@ -1,219 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - -abstract class TLCDRBase()(implicit p: Parameters) extends BackModule { - class TLCDRIO extends Bundle{ - val overCLK = Input(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - - val mem = Flipped(new Mem_Port_Bundle) - - val interrupt = Output(Vec(4, Bool())) - } - - val io: TLCDRIO = IO(new TLCDRIO) - - val dirSel = RegInit(false.B) - - val CDRIn = Module(new CDRIn) - CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn ) - CDRIn.io.overCLK := io.overCLK - - val CDROut = Module(new CDROut) - io.dDatOut := ~dirSel & CDROut.io.serDat - io.uDatOut := dirSel & CDROut.io.serDat - - - - val txFifo = Module(new Queue(UInt(32.W), 16)) - val rxFifo = Module(new Queue(UInt(32.W), 16)) - - - val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) ) - -} - - -trait TLCDRTx{ this: TLCDRBase => - - val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U ) - val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U ) - val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U ) - - - val txLen = RegInit(0.U(12.W)) - val isTxBusy = RegInit(false.B) - val isTxFull = ~txFifo.io.enq.ready - - - val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B) - println("Warning, TxEnd no confident\n") - val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull - val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast - - val txCnt = Reg(UInt(2.W)) - - val txData = Reg(UInt(32.W)) - - when( txFifo.io.deq.fire ){ //txCnt === 3.U - txData := txFifo.io.deq.bits - when( isTxBusy ){ - assert(CDROut.io.axis.fire) - } - - } .elsewhen( CDROut.io.axis.fire ){ - txData := txData << 8 - } - - txFifo.io.deq.ready := - Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B ) - - txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset - CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset - - CDROut.io.axis.bits.tdata := txData.head(8) - - // PriorityMux(Seq( - // (txCnt === 0.U) -> txData(31, 24), - // (txCnt === 1.U) -> txData(23, 16), - // (txCnt === 2.U) -> txData(15, 8), - // (txCnt === 3.U) -> txData( 7, 0), - // )) - - CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U - CDROut.io.axis.bits.tuser := false.B - CDROut.io.axis.valid := isTxBusy - - - when( isTLWriteTxLen | isTLWriteSoftReset ){ - isTxBusy := false.B - }.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){ - isTxBusy := true.B - } .elsewhen( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast ){ - isTxBusy := false.B - } - - - when( isTLWriteTxLen ){ - txCnt := 0.U - } .elsewhen( CDROut.io.axis.fire ){ - txCnt := txCnt + 1.U - } - - - when( isTLWriteTxLen ){ - txLen := io.mem.wdata - } .elsewhen( CDROut.io.axis.fire ){ - txLen := txLen - 1.U - } - - txFifo.io.enq.bits := io.mem.wdata - txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U - - -} - - -trait TLCDRRx{ this: TLCDRBase => - - // val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U ) - val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U ) - val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U ) - - val rxLen = RegInit(0.U(12.W)) - val isRxValid = rxFifo.io.enq.fire - val isRxError = RegInit(false.B) - val isAxisEnd = RegInit(false.B) - val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid - - val intRxError = ~RegNext(isRxError, false.B) & isRxError - val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire - val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd - - - val rxCnt = RegInit(0.U(2.W)) - val rxData = Reg(UInt(24.W)) - - when(isTLWriteSoftReset ){ - isAxisEnd := false.B - } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){ - isAxisEnd := true.B - } - - - when( isTLWriteSoftReset ){ - rxCnt := 0.U - } .elsewhen( CDRIn.io.axis.fire ){ - rxCnt := rxCnt + 1.U - - rxData := Cat( rxData, CDRIn.io.axis.bits.tdata ) - } - - when( isTLWriteSoftReset ){ - rxLen := 0.U - } .elsewhen( CDRIn.io.axis.fire ){ - rxLen := rxLen + 1.U - } - - rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U - rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ) - - assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) - - CDRIn.io.axis.ready := true.B - - rxFifo.reset := reset.asBool | isTLWriteSoftReset - CDRIn.reset := reset.asBool | isTLWriteSoftReset - - rxFifo.io.deq.ready := isTLReadRxFifo - - - when( isTLWriteSoftReset ){ - isRxError := false.B - } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){ - isRxError := true.B - printf("Warning, RxFifo Overflow!\n") - } - - - -} - -class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCDRRx{ - - val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U - - when( isWriteTransDir ){ - dirSel := io.mem.wdata - } - - io.mem.ready := - ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | - ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) ) - - io.interrupt(0) := intTxEnd - io.interrupt(1) := intRxError - io.interrupt(2) := intRxStart - io.interrupt(3) := intRxEnd - - - io.mem.rdata := - Mux1H(Seq( - isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B), - isTLReadRxLen -> rxLen, - isTLReadRxFifo -> rxFifo.io.deq.bits - )) - -} - - diff --git a/src/main/scala/backBoard/pico/picorv32.scala.bk b/src/main/scala/backBoard/pico/picorv32.scala.bk deleted file mode 100644 index 790071f..0000000 --- a/src/main/scala/backBoard/pico/picorv32.scala.bk +++ /dev/null @@ -1,53 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ -import chisel3.experimental._ - - - - -class picorv32 extends BlackBox() with HasBlackBoxResource { - val io = IO(new Bundle { - val clk = Input(Bool()) - val resetn = Input(Bool()) - val trap = Output(Bool()) - - val mem_valid = Output(Bool()) - val mem_instr = Output(Bool()) - val mem_ready = Input(Bool()) - - val mem_addr = Output(UInt(32.W)) - val mem_wdata = Output(UInt(32.W)) - val mem_wstrb = Output(UInt(4.W)) - val mem_rdata = Input(UInt(32.W)) - - // Look-Ahead Interface - val mem_la_read = Output(Bool()) - val mem_la_write = Output(Bool()) - val mem_la_addr = Output(UInt(32.W)) - val mem_la_wdata = Output(UInt(32.W)) - val mem_la_wstrb = Output(UInt(4.W)) - - // Pico Co-Processor Interface (PCPI) - val pcpi_valid = Output(Bool()) - val pcpi_insn = Output(UInt(32.W)) - val pcpi_rs1 = Output(UInt(32.W)) - val pcpi_rs2 = Output(UInt(32.W)) - val pcpi_wr = Input(Bool()) - val pcpi_rd = Input(UInt(32.W)) - val pcpi_wait = Input(Bool()) - val pcpi_ready = Input(Bool()) - - // IRQ Interface - val irq = Input(UInt(32.W)) - val eoi = Output(UInt(32.W)) - - // Trace Interface - val trace_valid = Output(Bool()) - val trace_data = Output(UInt(36.W)) - }) - addResource("./picorv32.v") -} - - diff --git a/src/main/verilog/CDRIn_fpga.v b/src/main/verilog/CDRIn_fpga.v deleted file mode 100644 index 9d6ff5c..0000000 --- a/src/main/verilog/CDRIn_fpga.v +++ /dev/null @@ -1,93 +0,0 @@ -module CDRIn_fpga( - input clock, - - - output reg [7:0] led, -// input serDat - input lvds_down_din_p, - input lvds_down_din_n -); - -wire resetn =1'b1; -wire clk_400m; -wire clk_100m; - -Gowin_PLLO Gowin_PLLO( - .lock(), - .clkouta(clk_400m), - .clkin(clock) -); - -wire serDat; - - -TLVDS_IBUF lvds_downstream_in( - .O(serDat), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (resetn), - .HCLKIN (clk_400m), - .CALIB (1'b0 ), - .CLKOUT (clk_100m) -); - - - - wire rx_axis_valid; - wire [7:0] rx_axis_bits_tdata; - wire rx_axis_bits_tlast; - wire rx_axis_bits_tuser; - - - - CDRIn s_CDRIn( - .clock(clk_100m), - .reset(~resetn), - - .io_axis_ready(1'b1), - .io_axis_valid(rx_axis_valid), - .io_axis_bits_tdata(rx_axis_bits_tdata), - .io_axis_bits_tlast(rx_axis_bits_tlast), - .io_axis_bits_tuser(rx_axis_bits_tuser), - - .io_serDat(serDat), - .io_overCLK(clk_400m) - ); - - - - reg [7:0] led_temp; - reg [7:0] cnt; - - - - always @(posedge clk_100m) begin - if ( rx_axis_valid & 1'b1 ) begin - if ( cnt == 0 ) begin - led_temp <= rx_axis_bits_tdata; - cnt <= cnt + 1; - end - if ( rx_axis_bits_tlast ) begin - cnt <= 0; - if( ~rx_axis_bits_tuser ) begin - led <= led_temp; - end - end - end - end - - - - - - - - - -endmodule diff --git a/src/main/verilog/CDROne_fpga.v b/src/main/verilog/CDROne_fpga.v deleted file mode 100644 index 587b351..0000000 --- a/src/main/verilog/CDROne_fpga.v +++ /dev/null @@ -1,69 +0,0 @@ -module CDROne_fpga( - input clock, - input resetn, - output [7:0] led - -// output serDat_o_p, -// output serDat_o_n, - -// input serDat_i_p, -// input serDat_i_n - -); - -wire serDat_o; -wire serDat_i; -wire clk100; -wire clk400; - - -// IBUFDS #( -// .DIFF_TERM("FALSE"), // Differential Termination -// .IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE" -// .IOSTANDARD("DEFAULT") // Specify the input I/O standard -// ) IBUFDS_inst ( -// .O(serDat_i), // Buffer output -// .I(serDat_i_p), // Diff_p buffer input (connect directly to top-level port) -// .IB(serDat_i_n) // Diff_n buffer input (connect directly to top-level port) -// ); - -// OBUFDS #( -// .IOSTANDARD("DEFAULT"), // Specify the output I/O standard -// .SLEW("SLOW") // Specify the output slew rate -// ) OBUFDS_inst ( -// .O(serDat_o_p), // Diff_p output (connect directly to top-level port) -// .OB(serDat_o_n), // Diff_n output (connect directly to top-level port) -// .I(serDat_o) // Buffer input -// ); - -clk_wiz_0 - ( - // Clock out ports - .clk_out1(clk100), - .clk_out2(clk400), - // Clock in ports - .clk_in1(clock) - ); - - - - -CDROut_fpga( - .clock(clk100), - .reset(~resetn), - .serDat(serDat_o) -); - - -CDRIn_fpga( - .clock(clk100), - .reset(~resetn), - .overCLK(clk400), - .serDat(serDat_o), -// .serDat(serDat_i), - .led(led) - -); - - -endmodule diff --git a/src/main/verilog/CDROut_fpga.v b/src/main/verilog/CDROut_fpga.v deleted file mode 100644 index d757f08..0000000 --- a/src/main/verilog/CDROut_fpga.v +++ /dev/null @@ -1,147 +0,0 @@ -module CDROut_fpga( - input clock, // 100MHZ - input resetn, - -// output serDat - output lvds_down_dout_p, - output lvds_down_dout_n - - -); - - -wire clk_400m; -wire clk_100m; -wire serDat; - - -Gowin_PLLO Gowin_PLLO( - .lock(), - .clkouta(clk_400m), - .clkin(clock) -); - - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (resetn), - .HCLKIN (clk_400m), - .CALIB (1'b0 ), - .CLKOUT (clk_100m) -); - - - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(serDat) -); - - - - wire tx_axis_ready; - - reg tx_axis_valid = 0; - reg [7:0] tx_axis_bits_tdata; - reg tx_axis_bits_tlast; - reg tx_axis_bits_tuser; - - - CDROut s_CDROut( - .clock(clk_100m), - .reset(~resetn), - - .io_axis_ready(tx_axis_ready), - .io_axis_valid(tx_axis_valid), - .io_axis_bits_tdata(tx_axis_bits_tdata), - .io_axis_bits_tlast(tx_axis_bits_tlast), - .io_axis_bits_tuser(tx_axis_bits_tuser), - .io_serDat(serDat) - ); - - - - - reg [31:0] rtc_cnt; - always @(posedge clk_100m) begin - if( rtc_cnt > 10000000 ) begin - rtc_cnt <= #2 0; - end else begin - rtc_cnt <= #2 rtc_cnt + 1; - end - end - - - reg [7:0] cnt; - reg [7:0] led_state; - - - always @(posedge clk_100m) begin - if( rtc_cnt == 0 ) begin - cnt <= #2 0; - - led_state <= - led_state == 8'h1 ? 8'h2 : - led_state == 8'h2 ? 8'h4 : - led_state == 8'h4 ? 8'h8 : - led_state == 8'h8 ? 8'h10 : - led_state == 8'h10 ? 8'h20 : - led_state == 8'h20 ? 8'h40 : - led_state == 8'h40 ? 8'h80 : 8'h1; - - end else begin - if( cnt == 8'd0 ) begin - tx_axis_valid <= #2 1'b1; - tx_axis_bits_tlast <= #2 1'b0; - tx_axis_bits_tdata <= #2 8'h0; - tx_axis_bits_tuser <= #2 1'b0; - cnt <= #2 cnt + 8'd1; - end else begin - if( tx_axis_valid & tx_axis_ready ) begin - if ( tx_axis_bits_tlast ) begin - tx_axis_valid <= #2 1'b0; - tx_axis_bits_tlast <= #2 1'b0; - end else begin - tx_axis_bits_tuser <= #2 1'b0; - - if( cnt == 8'd0 ) begin - tx_axis_bits_tdata <= #2 8'h0; - end - - if( cnt == 8'd1 ) begin - tx_axis_bits_tdata <= #2 8'd1; - end - - if( cnt == 8'd2 ) begin - tx_axis_bits_tdata <= #2 8'h0; - end - - if( cnt == 8'd3 ) begin - tx_axis_bits_tdata <= #2 8'h0; - end - - if( cnt == 8'd4 ) begin - tx_axis_bits_tdata <= #2 led_state; - end - - if( cnt == 8'd4 ) begin - tx_axis_bits_tlast <= #2 1'b1; - end else begin - cnt <= #2 cnt + 8'd1; - end - end - end - end - end - end - - - - - - - -endmodule diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v deleted file mode 100644 index 212b403..0000000 --- a/src/main/verilog/backBoardMstTop.v +++ /dev/null @@ -1,252 +0,0 @@ -//////////////////////// -//LVDS-BUS SYSTEM DEMO// -//////////////////////// - -module master_top( - - input resetn, - input clock, - - input lvds_up_din_p, - input lvds_up_din_n, - - output lvds_down_dout_p, - output lvds_down_dout_n, - - inout [15:0] io_FSMC_AD, - - input io_FSMC_csn, - input io_FSMC_rdn, - input io_FSMC_wrn, - input io_FSMC_advn, - - output interrupt, - input testIO -); - -wire [15:0] io_FSMC_ADIn; -wire [15:0] io_FSMC_ADOut; -wire io_FSMC_ADOEn; - -wire clk_400m; -wire clk_400m_a; -wire clk_100m; -wire clk_100m_a; -wire clk_50m; -wire clk_50m_a; -wire clk_10m_a; - -reg rst_n; - -wire lvds_down_dout; -wire lvds_up_din; - -reg rstn_d; - -wire reset_calib; -wire lock_o; -wire reset_stop; - -wire resetn1; - -always@(posedge clock) begin - rstn_d <= resetn; - rst_n <= rstn_d; -end - - -reg [3:0] resetCnt = 4'd0; -always @( posedge clock ) begin - if( resetCnt != 4'd15 ) begin - resetCnt <= resetCnt + 4'd1; - end -end - -assign resetn1 = (resetCnt == 4'd15); - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - - -DHCEN dhcen_inst ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(rst_n && resetn1), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - -wire frame_info_update_en; -wire [7:0] slave_type_num; -wire [7:0] slave_data_length; -wire tx_start; -wire slave_link_num_valid; -wire [6:0] slave_link_num; -wire downstream_busy; -wire upstream_crc_valid; -wire closed_loop_err; -wire [6:0] link_err_location; -wire upstream_cdr_err; -wire upstream_crc_err; - -wire [7:0] tx_data_in; -wire tx_data_ready; -wire [7:0] rx_data_out; -wire rx_data_valid; - -lvds_bus_master_top i_lvds_bus_master( - .rst_n(rst_n && resetn1), - .reset_calib(reset_calib), - .oser_pclk(clk_10m_a), - .oser_fclk(clk_50m_a), - .ides_pclk(clk_100m_a), - .ides_fclk(clk_400m_a), - - .lvds_down_dout(lvds_down_dout), - .lvds_up_din(lvds_up_din), - - .frame_info_update_en(frame_info_update_en), - .slave_type_num(slave_type_num), - .slave_data_length(slave_data_length), - - .slave_link_num_valid(slave_link_num_valid), - .slave_link_num(slave_link_num), - - .tx_start(tx_start), - .tx_data_in(tx_data_in), - .tx_data_ready(tx_data_ready), - .downstream_busy(downstream_busy), - .rx_data_out(rx_data_out), - .rx_data_valid(rx_data_valid), - .upstream_crc_valid(upstream_crc_valid), - .upstream_crc_err(upstream_crc_err), - .upstream_crc_err_count(), - .upstream_cdr_err(upstream_cdr_err), - - .closed_loop_err(closed_loop_err), - .link_err_location(link_err_location), - - .test_downstream_tx_en(), - .test_downstream_tx_8b_data(), - .test_downstream_tx_10b_data(), - .test_upstream_rx_busy(), - .test_upstream_rx_10b_data(), - .test_upstream_rx_8b_data() - ); - - - - - -BackBoardMst i_BackBoardMst( - .io_FSMC_ADIn (io_FSMC_ADIn), - .io_FSMC_ADOut(io_FSMC_ADOut), - .io_FSMC_ADOEn(io_FSMC_ADOEn), - .io_FSMC_csn(io_FSMC_csn), - .io_FSMC_rdn(io_FSMC_rdn), - .io_FSMC_wrn(io_FSMC_wrn), - .io_FSMC_advn(io_FSMC_advn), - - .reset(~resetn1), - .clock(clk_10m_a), - .io_oser_pclk(clk_10m_a), - .io_oser_fclk(clk_50m_a), - .io_ides_pclk(clk_100m_a), - .io_ides_fclk(clk_400m_a), - - .io_interrupt(interrupt), - .io_testIO(testIO), - - .io_lvdsMst_frame_info_update_en(frame_info_update_en), - .io_lvdsMst_slave_type_num(slave_type_num), - .io_lvdsMst_slave_data_length(slave_data_length), - .io_lvdsMst_tx_start(tx_start), - .io_lvdsMst_slave_link_num_valid(slave_link_num_valid), - .io_lvdsMst_slave_link_num(slave_link_num), - .io_lvdsMst_downstream_busy(downstream_busy), - .io_lvdsMst_upstream_crc_valid(upstream_crc_valid), - .io_lvdsMst_closed_loop_err(closed_loop_err), - .io_lvdsMst_link_err_location(link_err_location), - - .io_lvdsMst_upstream_cdr_err(upstream_cdr_err), - .io_lvdsMst_upstream_crc_err(upstream_crc_err), - - .io_lvdsMst_tx_data_in(tx_data_in), - .io_lvdsMst_tx_data_ready(tx_data_ready), - .io_lvdsMst_rx_data_out(rx_data_out), - .io_lvdsMst_rx_data_valid(rx_data_valid) - -); - - - - generate - for( genvar i = 0; i < 16; i = i + 1 ) begin - IOBUF uut( - .O(io_FSMC_ADIn[i]), - .IO(io_FSMC_AD[i]), - .I(io_FSMC_ADOut[i]), - .OEN(~io_FSMC_ADOEn) - ); - end - endgenerate - - -endmodule diff --git a/src/main/verilog/defineParam.v b/src/main/verilog/defineParam.v deleted file mode 100644 index e91e170..0000000 --- a/src/main/verilog/defineParam.v +++ /dev/null @@ -1,15 +0,0 @@ -`define DATA2 8'h0 -`define DATA3 8'h0 -`define DATA4 8'h0 -`define DATA5 8'h0 -`define DATA6 8'h0 -`define DATA7 8'h0 -`define DATA8 8'h0 -`define DATA9 8'h0 - - -`define VENDORID 16'h1122 -`define MODULEID 16'h3344 -`define HWVERSION 16'h5566 -`define SWVERSION 16'h7788 -`define SERIAL 48'hbbccddeeff00 \ No newline at end of file diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v deleted file mode 100644 index cd026c4..0000000 --- a/src/main/verilog/di16_top.v +++ /dev/null @@ -1,319 +0,0 @@ - - -module di16_top( - input clock, - - input lvds_up_din_p, - input lvds_up_din_n, - output lvds_up_dout_p, - output lvds_up_dout_n, - - input lvds_down_din_p, - input lvds_down_din_n, - output lvds_down_dout_p, - output lvds_down_dout_n, - - input DCIn, - output isOnline, - input isLast, - - output LED_PR, - input [15:0] in - -); - -wire clk_400m; -wire clk_400m_a; -wire clk_100m_a; -wire clk_50m_a; -wire clk_10m_a; - -wire lock_o; -wire reset_stop; -wire reset_calib; - -reg rst_n; -reg rstn_d; - -wire resetn; -reg resetn1=1'b1; -wire timeout_rst; -reg timeout_rst_d1; -reg timeout_rst_d2; -reg timeout_rst_d3; -reg timeout_rst_d4; -reg timeout_rst_d5; -reg timeout_rst_d6; -reg timeout_rst_d7; -reg timeout_rst_d8; - -reg [3:0] resetCnt = 4'd0; -always @( posedge clock ) begin - if( resetCnt != 4'd15 ) begin - resetCnt <= resetCnt + 4'd1; - end -end - -assign resetn = resetCnt == 4'd15; - -always@(posedge clock or negedge resetn) begin - if(!resetn) begin - timeout_rst_d1 <= 0; - timeout_rst_d2 <= 0; - timeout_rst_d3 <= 0; - timeout_rst_d4 <= 0; - timeout_rst_d5 <= 0; - timeout_rst_d6 <= 0; - timeout_rst_d7 <= 0; - timeout_rst_d8 <= 0; - end else begin - timeout_rst_d1 <= timeout_rst; - timeout_rst_d2 <= timeout_rst_d1; - timeout_rst_d3 <= timeout_rst_d2; - timeout_rst_d4 <= timeout_rst_d3; - timeout_rst_d5 <= timeout_rst_d4; - timeout_rst_d6 <= timeout_rst_d5; - timeout_rst_d7 <= timeout_rst_d6; - timeout_rst_d8 <= timeout_rst_d7; - end -end - -always @(posedge clock or negedge resetn) begin - if(!resetn) begin - resetn1 <= 1'b1; - end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin - resetn1 <= 1'b0; - end else begin - resetn1 <= 1'b1; - end -end - - -reg [5:0] delay_io_last=6'b111111; -reg [15:0] counter0=0; -reg clk_en0; -wire isLast_temp; -wire isLast_temp1; - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - counter0 <= 16'd0; - clk_en0 <= 1'b0; - end - else if(counter0 == 16'd9999) begin - counter0 <= 16'd0; - clk_en0 <= 1'b1; - end - else begin - counter0 <= counter0 + 1; - clk_en0 <= 1'b0; - end -end - - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - delay_io_last <= 6'b111111; - end else if(clk_en0 == 1'b1) begin - delay_io_last[5:1] <= delay_io_last[4:0]; - delay_io_last[0] <= isLast; - end -end - - -assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]}; -assign isLast_temp1 = ~isLast_temp; - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - -wire lvds_down_din; -wire lvds_down_dout; -wire lvds_up_din; -wire lvds_up_dout; - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_downstream_in( - .O(lvds_down_din), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -TLVDS_OBUF lvds_upstream_out( - .O(lvds_up_dout_p), - .OB(lvds_up_dout_n), - .I(lvds_up_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - -DHCEN dhcen_inst2 ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(resetn && resetn1), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - -wire [7:0] downstream_rx_data_out; -wire downstream_rx_data_valid; -wire downstream_rx_crc_valid; -wire downstream_rx_crc_err; -wire upstream_tx_data_ready; -wire [7:0] upstream_tx_data_in; - -wire downstream_rx_cdr_err; -wire upstream_rx_cdr_err; - - - -lvds_bus_slave_top i_lvds_bus_slave( - .rst_n(resetn && resetn1), - .reset_calib(reset_calib), - .oser_pclk(clk_10m_a), - .oser_fclk(clk_50m_a), - .ides_pclk(clk_100m_a), - .ides_fclk(clk_400m_a), - .timeout_rst(timeout_rst), //add 240523 - - .lvds_down_din(lvds_down_din), - .lvds_down_dout(lvds_down_dout), - .lvds_up_din(lvds_up_din), - .lvds_up_dout(lvds_up_dout), - - .downstream_rx_data_valid(downstream_rx_data_valid), - .downstream_rx_unicast_pkg_valid(), - .downstream_rx_data_out(downstream_rx_data_out), - .downstream_rx_crc_valid(downstream_rx_crc_valid), - .downstream_rx_crc_err(downstream_rx_crc_err), - .downstream_rx_crc_err_counter(), - .downstream_rx_cdr_err(downstream_rx_cdr_err), - .downstream_sync(), - .upstream_tx_data_ready(upstream_tx_data_ready), - .upstream_tx_unicast_pkg_ready(), - .upstream_tx_data_in(upstream_tx_data_in), - .upstream_rx_crc_valid(), - .upstream_rx_crc_err(), - .upstream_rx_crc_err_counter(), - .upstream_rx_cdr_err(upstream_rx_cdr_err), - - .local_slave_id(), - .test_downstream_rx_10b_data(), - .test_downstream_rx_8b_data(), - .test_downstream_rx_state_machine(), - .test_downstream_tx_en(), - .test_downstream_tx_8b_data(), - .test_downstream_tx_10b_data(), - .test_upstream_rx_10b_data(), - .test_upstream_rx_8b_data(), - .test_upstream_rx_state_machine(), - .test_upstream_tx_en(), - .test_upstream_tx_8b_data(), - .test_upstream_tx_10b_data() - ); - -DIn16 i_din16( - .reset(~resetn), - .clock(clk_10m_a), - - .io_isOnline(isOnline), - .io_isLast(isLast_temp1), - .io_DCIn(DCIn), - - .param_data2(`DATA2), - .param_data3(`DATA3), - .param_data4(`DATA4), - .param_data5(`DATA5), - .param_data6(`DATA6), - .param_data7(`DATA7), - .param_data8(`DATA8), - .param_data9(`DATA9), - .param_vendorID(`VENDORID), - .param_moduleID(`MODULEID), - .param_hwVersion(`HWVERSION), - .param_swVersion(`SWVERSION), - .param_serial(`SERIAL), - .LED_PR(LED_PR), - .in(in), - - .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), - .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), - .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), - .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), - .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), - .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), - .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), - .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) -); - -endmodule - - - - diff --git a/src/main/verilog/do16c_top.v b/src/main/verilog/do16c_top.v deleted file mode 100644 index 4d4b1e4..0000000 --- a/src/main/verilog/do16c_top.v +++ /dev/null @@ -1,330 +0,0 @@ - - -module do16c_top( - - input clock, - - - input lvds_up_din_p, - input lvds_up_din_n, - output lvds_up_dout_p, - output lvds_up_dout_n, - - input lvds_down_din_p, - input lvds_down_din_n, - output lvds_down_dout_p, - output lvds_down_dout_n, - - output isOnline, - input isLast, - - input DCIn, - output LED_PR, - output LED_ERR, - output [15:0] out, - input flt_0, - input flt_1, - input v24Det - -); - - - -wire clk_400m; -wire clk_400m_a; -wire clk_100m_a; -wire clk_50m_a; -wire clk_10m_a; - -wire lock_o; -wire reset_stop; -wire reset_calib; - -reg rst_n; -reg rstn_d; - -wire resetn; -reg resetn1=1'b1; -wire timeout_rst; -reg timeout_rst_d1; -reg timeout_rst_d2; -reg timeout_rst_d3; -reg timeout_rst_d4; -reg timeout_rst_d5; -reg timeout_rst_d6; -reg timeout_rst_d7; -reg timeout_rst_d8; - -reg [3:0] resetCnt = 4'd0; -always @( posedge clock ) begin - if( resetCnt != 4'd15 ) begin - resetCnt <= resetCnt + 4'd1; - end -end - -assign resetn = resetCnt == 4'd15; - -always@(posedge clock or negedge resetn) begin - if(!resetn) begin - timeout_rst_d1 <= 0; - timeout_rst_d2 <= 0; - timeout_rst_d3 <= 0; - timeout_rst_d4 <= 0; - timeout_rst_d5 <= 0; - timeout_rst_d6 <= 0; - timeout_rst_d7 <= 0; - timeout_rst_d8 <= 0; - end - else begin - timeout_rst_d1 <= timeout_rst; - timeout_rst_d2 <= timeout_rst_d1; - timeout_rst_d3 <= timeout_rst_d2; - timeout_rst_d4 <= timeout_rst_d3; - timeout_rst_d5 <= timeout_rst_d4; - timeout_rst_d6 <= timeout_rst_d5; - timeout_rst_d7 <= timeout_rst_d6; - timeout_rst_d8 <= timeout_rst_d7; - end -end - -always @(posedge clock or negedge resetn) begin - if(!resetn) begin - resetn1 <= 1'b1; - end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin - resetn1 <= 1'b0; - end else begin - resetn1 <= 1'b1; - end -end - - -reg [5:0] delay_io_last=6'b111111; -reg [15:0] counter0=0; -reg clk_en0; -wire isLast_temp; -wire isLast_temp1; - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - counter0 <= 16'd0; - clk_en0 <= 1'b0; - end else if(counter0 == 16'd9999) begin - counter0 <= 16'd0; - clk_en0 <= 1'b1; - end else begin - counter0 <= counter0 + 1; - clk_en0 <= 1'b0; - end -end - - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - delay_io_last <= 6'b111111; - end else if(clk_en0 == 1'b1) begin - delay_io_last[5:1] <= delay_io_last[4:0]; - delay_io_last[0] <= isLast; - end -end - - -assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]}; -assign isLast_temp1 = ~isLast_temp; - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - -wire lvds_down_din; -wire lvds_down_dout; -wire lvds_up_din; -wire lvds_up_dout; - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_downstream_in( - .O(lvds_down_din), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -TLVDS_OBUF lvds_upstream_out( - .O(lvds_up_dout_p), - .OB(lvds_up_dout_n), - .I(lvds_up_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - -DHCEN dhcen_inst2 ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(resetn && resetn1), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - -wire [7:0] downstream_rx_data_out; -wire downstream_rx_data_valid; -wire downstream_rx_crc_valid; -wire downstream_rx_crc_err; -wire upstream_tx_data_ready; -wire [7:0] upstream_tx_data_in; - -wire downstream_rx_cdr_err; -wire upstream_rx_cdr_err; - -lvds_bus_slave_top i_lvds_bus_slave( - .rst_n(resetn && resetn1), - .reset_calib(reset_calib), - .oser_pclk(clk_10m_a), - .oser_fclk(clk_50m_a), - .ides_pclk(clk_100m_a), - .ides_fclk(clk_400m_a), - .timeout_rst(timeout_rst), //add 240523 - - .lvds_down_din(lvds_down_din), - .lvds_down_dout(lvds_down_dout), - .lvds_up_din(lvds_up_din), - .lvds_up_dout(lvds_up_dout), - - .downstream_rx_data_valid(downstream_rx_data_valid), - .downstream_rx_unicast_pkg_valid(), - .downstream_rx_data_out(downstream_rx_data_out), - .downstream_rx_crc_valid(downstream_rx_crc_valid), - .downstream_rx_crc_err(downstream_rx_crc_err), - .downstream_rx_crc_err_counter(), - .downstream_rx_cdr_err(downstream_rx_cdr_err), - .downstream_sync(), - .upstream_tx_data_ready(upstream_tx_data_ready), - .upstream_tx_unicast_pkg_ready(), - .upstream_tx_data_in(upstream_tx_data_in), - .upstream_rx_crc_valid(), - .upstream_rx_crc_err(), - .upstream_rx_crc_err_counter(), - .upstream_rx_cdr_err(upstream_rx_cdr_err), - - .local_slave_id(), - .test_downstream_rx_10b_data(), - .test_downstream_rx_8b_data(), - .test_downstream_rx_state_machine(), - .test_downstream_tx_en(), - .test_downstream_tx_8b_data(), - .test_downstream_tx_10b_data(), - .test_upstream_rx_10b_data(), - .test_upstream_rx_8b_data(), - .test_upstream_rx_state_machine(), - .test_upstream_tx_en(), - .test_upstream_tx_8b_data(), - .test_upstream_tx_10b_data() - ); - - -DOut16c i_dout16( - .reset(~resetn), - .clock(clk_10m_a), - - .io_isOnline(isOnline), - .io_isLast(isLast_temp1), - .io_DCIn(DCIn), - - .param_data2(`DATA2), - .param_data3(`DATA3), - .param_data4(`DATA4), - .param_data5(`DATA5), - .param_data6(`DATA6), - .param_data7(`DATA7), - .param_data8(`DATA8), - .param_data9(`DATA9), - .param_vendorID(`VENDORID), - .param_moduleID(`MODULEID), - .param_hwVersion(`HWVERSION), - .param_swVersion(`SWVERSION), - - .param_serial(`SERIAL), - .LED_PR(LED_PR), - .LED_ERR(LED_ERR), - .out(out), - .flt_0(flt_0), - .flt_1(flt_1), - .v24Det(v24Det), - - .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), - .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), - .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), - .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), - .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), - .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), - .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), - .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) -); - -endmodule - - - - diff --git a/src/main/verilog/do16p_top.v b/src/main/verilog/do16p_top.v deleted file mode 100644 index 3df48b8..0000000 --- a/src/main/verilog/do16p_top.v +++ /dev/null @@ -1,333 +0,0 @@ - - -module do16p_top( - - input clock, - - - input lvds_up_din_p, - input lvds_up_din_n, - output lvds_up_dout_p, - output lvds_up_dout_n, - - input lvds_down_din_p, - input lvds_down_din_n, - output lvds_down_dout_p, - output lvds_down_dout_n, - - output isOnline, - input isLast, - - input DCIn, - output LED_PR, - output LED_ERR, - output [15:0] out, - input v24Det, - input [3:0] fin_cur, - output [2:0] fin_sel, - output fin_clk, - input [2:0] fin_vol -); - - - -wire clk_400m; -wire clk_400m_a; -wire clk_100m_a; -wire clk_50m_a; -wire clk_10m_a; - -wire lock_o; -wire reset_stop; -wire reset_calib; - -reg rst_n; -reg rstn_d; - -wire resetn; -reg resetn1=1'b1; -wire timeout_rst; -reg timeout_rst_d1; -reg timeout_rst_d2; -reg timeout_rst_d3; -reg timeout_rst_d4; -reg timeout_rst_d5; -reg timeout_rst_d6; -reg timeout_rst_d7; -reg timeout_rst_d8; - -reg [3:0] resetCnt = 4'd0; -always @( posedge clock ) begin - if( resetCnt != 4'd15 ) begin - resetCnt <= resetCnt + 4'd1; - end -end - -assign resetn = resetCnt == 4'd15; - -always@(posedge clock or negedge resetn) begin - if(!resetn) begin - timeout_rst_d1 <= 0; - timeout_rst_d2 <= 0; - timeout_rst_d3 <= 0; - timeout_rst_d4 <= 0; - timeout_rst_d5 <= 0; - timeout_rst_d6 <= 0; - timeout_rst_d7 <= 0; - timeout_rst_d8 <= 0; - end - else begin - timeout_rst_d1 <= timeout_rst; - timeout_rst_d2 <= timeout_rst_d1; - timeout_rst_d3 <= timeout_rst_d2; - timeout_rst_d4 <= timeout_rst_d3; - timeout_rst_d5 <= timeout_rst_d4; - timeout_rst_d6 <= timeout_rst_d5; - timeout_rst_d7 <= timeout_rst_d6; - timeout_rst_d8 <= timeout_rst_d7; - end -end - -always @(posedge clock or negedge resetn) begin - if(!resetn) begin - resetn1 <= 1'b1; - end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin - resetn1 <= 1'b0; - end else begin - resetn1 <= 1'b1; - end -end - - -reg [5:0] delay_io_last=6'b111111; -reg [15:0] counter0=0; -reg clk_en0; -wire isLast_temp; -wire isLast_temp1; - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - counter0 <= 16'd0; - clk_en0 <= 1'b0; - end else if(counter0 == 16'd9999) begin - counter0 <= 16'd0; - clk_en0 <= 1'b1; - end else begin - counter0 <= counter0 + 1; - clk_en0 <= 1'b0; - end -end - - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - delay_io_last <= 6'b111111; - end else if(clk_en0 == 1'b1) begin - delay_io_last[5:1] <= delay_io_last[4:0]; - delay_io_last[0] <= isLast; - end -end - - -assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]}; -assign isLast_temp1 = ~isLast_temp; - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - -wire lvds_down_din; -wire lvds_down_dout; -wire lvds_up_din; -wire lvds_up_dout; - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_downstream_in( - .O(lvds_down_din), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -TLVDS_OBUF lvds_upstream_out( - .O(lvds_up_dout_p), - .OB(lvds_up_dout_n), - .I(lvds_up_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - -DHCEN dhcen_inst2 ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(resetn && resetn1), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - -wire [7:0] downstream_rx_data_out; -wire downstream_rx_data_valid; -wire downstream_rx_crc_valid; -wire downstream_rx_crc_err; -wire upstream_tx_data_ready; -wire [7:0] upstream_tx_data_in; - -wire downstream_rx_cdr_err; -wire upstream_rx_cdr_err; - -lvds_bus_slave_top i_lvds_bus_slave( - .rst_n(resetn && resetn1), - .reset_calib(reset_calib), - .oser_pclk(clk_10m_a), - .oser_fclk(clk_50m_a), - .ides_pclk(clk_100m_a), - .ides_fclk(clk_400m_a), - .timeout_rst(timeout_rst), //add 240523 - - .lvds_down_din(lvds_down_din), - .lvds_down_dout(lvds_down_dout), - .lvds_up_din(lvds_up_din), - .lvds_up_dout(lvds_up_dout), - - .downstream_rx_data_valid(downstream_rx_data_valid), - .downstream_rx_unicast_pkg_valid(), - .downstream_rx_data_out(downstream_rx_data_out), - .downstream_rx_crc_valid(downstream_rx_crc_valid), - .downstream_rx_crc_err(downstream_rx_crc_err), - .downstream_rx_crc_err_counter(), - .downstream_rx_cdr_err(downstream_rx_cdr_err), - .downstream_sync(), - .upstream_tx_data_ready(upstream_tx_data_ready), - .upstream_tx_unicast_pkg_ready(), - .upstream_tx_data_in(upstream_tx_data_in), - .upstream_rx_crc_valid(), - .upstream_rx_crc_err(), - .upstream_rx_crc_err_counter(), - .upstream_rx_cdr_err(upstream_rx_cdr_err), - - .local_slave_id(), - .test_downstream_rx_10b_data(), - .test_downstream_rx_8b_data(), - .test_downstream_rx_state_machine(), - .test_downstream_tx_en(), - .test_downstream_tx_8b_data(), - .test_downstream_tx_10b_data(), - .test_upstream_rx_10b_data(), - .test_upstream_rx_8b_data(), - .test_upstream_rx_state_machine(), - .test_upstream_tx_en(), - .test_upstream_tx_8b_data(), - .test_upstream_tx_10b_data() - ); - - -DOut16p i_dout16( - .reset(~resetn), - .clock(clk_10m_a), - - .io_isOnline(isOnline), - .io_isLast(isLast_temp1), - .io_DCIn(DCIn), - - .param_data2(`DATA2), - .param_data3(`DATA3), - .param_data4(`DATA4), - .param_data5(`DATA5), - .param_data6(`DATA6), - .param_data7(`DATA7), - .param_data8(`DATA8), - .param_data9(`DATA9), - .param_vendorID(`VENDORID), - .param_moduleID(`MODULEID), - .param_hwVersion(`HWVERSION), - .param_swVersion(`SWVERSION), - - .param_serial(`SERIAL), - .LED_PR(LED_PR), - .LED_ERR(LED_ERR), - .out(out), - .v24Det(v24Det), - .fin_cur(fin_cur), - .fin_sel(fin_sel), - .fin_clk(fin_clk), - .fin_vol(fin_vol), - - .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), - .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), - .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), - .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), - .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), - .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), - .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), - .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) -); - -endmodule - - - - diff --git a/src/main/verilog/oser_rst.v b/src/main/verilog/oser_rst.v deleted file mode 100644 index 664b83a..0000000 --- a/src/main/verilog/oser_rst.v +++ /dev/null @@ -1,117 +0,0 @@ -module oser_rst -(input clk_in, //!system clock or any other speed comparable with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - input rst_n, //!from system reset - input pll_lock, //!RX PLL lock flag - output reg reset_stop, //!to DHCEN CE port - output reg reset_calib, //!to IDES/CLKDIV reset port - output reg set_calib, //!not used - output reg ready //!ready -); - -/******************************************************************************* - * OSER FSM States defined - *******************************************************************************/ - parameter STATE_IDLE = 5'b0000; - parameter STATE_SERDES_STOP_S = 5'b0001; - parameter STATE_SERDES_RST_S = 5'b0010; - parameter STATE_SERDES_RST_E = 5'b0011; - parameter STATE_SERDES_STOP_E = 5'b0100; - parameter STATE_SERDES_WAIT = 5'b0101; - parameter STATE_SERDES_CALIB = 5'b0110; - parameter STATE_SERDES_READY = 5'b0111; - /******************************************************************************* - //reg and wire definition - *******************************************************************************/ - reg [4:0] Fsm_serdes_rst_ctrl; - reg [9:0] Cnt_serdes_rst_ctrl; - - /*******************************************************************************/ - /*******************************************************************************/ - always @(posedge clk_in or negedge rst_n) - begin - if (~rst_n) begin - Fsm_serdes_rst_ctrl <= STATE_IDLE; - Cnt_serdes_rst_ctrl <= 'd0; - reset_stop <= 1'b0; - reset_calib <= 1'b0; - set_calib <= 1'b0; - ready <= 1'b0; - end - else begin - case(Fsm_serdes_rst_ctrl) - STATE_IDLE:begin//idle - if(pll_lock) - Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_S; - Cnt_serdes_rst_ctrl <= 'd0; - reset_stop <= 1'b0; - reset_calib <= 1'b0; - set_calib <= 1'b0; - ready <= 1'b0; - end - STATE_SERDES_STOP_S:begin - Cnt_serdes_rst_ctrl<=Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[3])begin - // reset_stop <= 1'b1;// - reset_calib <= 1'b1;// - Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_S; - end - else begin - reset_stop <= 1'b0; - end - end - STATE_SERDES_RST_S:begin - Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[5])begin - // reset_calib <= 1'b1; - reset_stop <= 1'b1; - Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_E; - end - end - STATE_SERDES_RST_E:begin - Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[6])begin - reset_calib <= 1'b0; - Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_E; - end - end - STATE_SERDES_STOP_E:begin - Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[7])begin - reset_stop <= 1'b0; - Fsm_serdes_rst_ctrl <= STATE_SERDES_CALIB; - end - end - STATE_SERDES_CALIB:begin - Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[3:0] == 4'h04 )begin - set_calib <= 1'b1; - end - // if(Cnt_serdes_rst_ctrl[3:0] == 4'h08)begin - // set_calib <= 1'b0; - // end - if(Cnt_serdes_rst_ctrl[6])begin - set_calib <= 1'b0; - Fsm_serdes_rst_ctrl <= STATE_SERDES_READY; - end - end - - STATE_SERDES_READY:begin - Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; - if(Cnt_serdes_rst_ctrl[8])begin - ready <= 1'b1; - // set_calib <= 1'b0; - Fsm_serdes_rst_ctrl <= STATE_SERDES_WAIT; - end - end - STATE_SERDES_WAIT:begin - if(~pll_lock)begin - Fsm_serdes_rst_ctrl<=STATE_IDLE; - end - end - default:begin - Fsm_serdes_rst_ctrl<=STATE_IDLE; - end - endcase - end - end -endmodule \ No newline at end of file diff --git a/src/main/verilog/spi_top.v b/src/main/verilog/spi_top.v deleted file mode 100644 index 483b4ab..0000000 --- a/src/main/verilog/spi_top.v +++ /dev/null @@ -1,336 +0,0 @@ - - -module spi_top( - - input clock, - - - input lvds_up_din_p, - input lvds_up_din_n, - output lvds_up_dout_p, - output lvds_up_dout_n, - - input lvds_down_din_p, - input lvds_down_din_n, - output lvds_down_dout_p, - output lvds_down_dout_n, - - output isOnline, - input isLast, - - input DCIn, - output LED_PR, - - input sck, - input mosi, - output miso, - input csn, - - output interrupt - -); - - - -wire clk_400m; -wire clk_400m_a; -wire clk_100m_a; -wire clk_50m_a; -wire clk_10m_a; - -wire lock_o; -wire reset_stop; -wire reset_calib; - -reg rst_n; -reg rstn_d; - -wire resetn; -reg resetn1=1'b1; -wire timeout_rst; -reg timeout_rst_d1; -reg timeout_rst_d2; -reg timeout_rst_d3; -reg timeout_rst_d4; -reg timeout_rst_d5; -reg timeout_rst_d6; -reg timeout_rst_d7; -reg timeout_rst_d8; - -reg [3:0] resetCnt = 4'd0; -always @( posedge clock ) begin - if( resetCnt != 4'd15 ) begin - resetCnt <= resetCnt + 4'd1; - end -end - -assign resetn = resetCnt == 4'd15; - -always@(posedge clock or negedge resetn) begin - if(!resetn) begin - timeout_rst_d1 <= 0; - timeout_rst_d2 <= 0; - timeout_rst_d3 <= 0; - timeout_rst_d4 <= 0; - timeout_rst_d5 <= 0; - timeout_rst_d6 <= 0; - timeout_rst_d7 <= 0; - timeout_rst_d8 <= 0; - end - else begin - timeout_rst_d1 <= timeout_rst; - timeout_rst_d2 <= timeout_rst_d1; - timeout_rst_d3 <= timeout_rst_d2; - timeout_rst_d4 <= timeout_rst_d3; - timeout_rst_d5 <= timeout_rst_d4; - timeout_rst_d6 <= timeout_rst_d5; - timeout_rst_d7 <= timeout_rst_d6; - timeout_rst_d8 <= timeout_rst_d7; - end -end - -always @(posedge clock or negedge resetn) begin - if(!resetn) begin - resetn1 <= 1'b1; - end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin - resetn1 <= 1'b0; - end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin - resetn1 <= 1'b0; - end else begin - resetn1 <= 1'b1; - end -end - - -reg [5:0] delay_io_last=6'b111111; -reg [15:0] counter0=0; -reg clk_en0; -wire isLast_temp; -wire isLast_temp1; - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - counter0 <= 16'd0; - clk_en0 <= 1'b0; - end else if(counter0 == 16'd9999) begin - counter0 <= 16'd0; - clk_en0 <= 1'b1; - end else begin - counter0 <= counter0 + 1; - clk_en0 <= 1'b0; - end -end - - -always @(posedge clk_10m_a or negedge resetn) begin - if(!resetn) begin - delay_io_last <= 6'b111111; - end else if(clk_en0 == 1'b1) begin - delay_io_last[5:1] <= delay_io_last[4:0]; - delay_io_last[0] <= isLast; - end -end - - -assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]}; -assign isLast_temp1 = ~isLast_temp; - -Gowin_PLLO Gowin_PLLO( - .lock(lock_o), - .clkouta(clk_400m), - .clkin(clock) -); - -wire lvds_down_din; -wire lvds_down_dout; -wire lvds_up_din; -wire lvds_up_dout; - -TLVDS_OBUF lvds_downstream_out( - .O(lvds_down_dout_p), - .OB(lvds_down_dout_n), - .I(lvds_down_dout) -); - - -TLVDS_IBUF lvds_downstream_in( - .O(lvds_down_din), - .I(lvds_down_din_p), - .IB(lvds_down_din_n) -); - - -TLVDS_OBUF lvds_upstream_out( - .O(lvds_up_dout_p), - .OB(lvds_up_dout_n), - .I(lvds_up_dout) -); - - -TLVDS_IBUF lvds_upstream_in( - .O(lvds_up_din), - .I(lvds_up_din_p), - .IB(lvds_up_din_n) -); - - -DHCEN dhcen_inst2 ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - - -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(resetn && resetn1), - .pll_lock(lock_o), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - - -defparam Inst4_CLKDIVC.DIV_MODE="4"; -defparam Inst4_CLKDIVC.GSREN="false"; -CLKDIV Inst4_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_400m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_100m_a) -); - - -defparam Inst2_CLKDIVC.DIV_MODE="2"; -defparam Inst2_CLKDIVC.GSREN="false"; -CLKDIV Inst2_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_100m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_50m_a) -); - - -defparam Inst5_CLKDIVC.DIV_MODE="5"; -defparam Inst5_CLKDIVC.GSREN="false"; -CLKDIV Inst5_CLKDIVC( - .RESETN (~reset_calib), - .HCLKIN (clk_50m_a), - .CALIB (1'b0 ), - .CLKOUT (clk_10m_a) -); - -wire [7:0] downstream_rx_data_out; -wire downstream_rx_data_valid; -wire downstream_rx_crc_valid; -wire downstream_rx_crc_err; -wire upstream_tx_data_ready; -wire [7:0] upstream_tx_data_in; - -wire downstream_rx_cdr_err; -wire upstream_rx_cdr_err; - -lvds_bus_slave_top i_lvds_bus_slave( - .rst_n(resetn && resetn1), - .reset_calib(reset_calib), - .oser_pclk(clk_10m_a), - .oser_fclk(clk_50m_a), - .ides_pclk(clk_100m_a), - .ides_fclk(clk_400m_a), - .timeout_rst(timeout_rst), //add 240523 - - .lvds_down_din(lvds_down_din), - .lvds_down_dout(lvds_down_dout), - .lvds_up_din(lvds_up_din), - .lvds_up_dout(lvds_up_dout), - - .downstream_rx_data_valid(downstream_rx_data_valid), - .downstream_rx_unicast_pkg_valid(), - .downstream_rx_data_out(downstream_rx_data_out), - .downstream_rx_crc_valid(downstream_rx_crc_valid), - .downstream_rx_crc_err(downstream_rx_crc_err), - .downstream_rx_crc_err_counter(), - .downstream_rx_cdr_err(downstream_rx_cdr_err), - .downstream_sync(), - .upstream_tx_data_ready(upstream_tx_data_ready), - .upstream_tx_unicast_pkg_ready(), - .upstream_tx_data_in(upstream_tx_data_in), - .upstream_rx_crc_valid(), - .upstream_rx_crc_err(), - .upstream_rx_crc_err_counter(), - .upstream_rx_cdr_err(upstream_rx_cdr_err), - - .local_slave_id(), - .test_downstream_rx_10b_data(), - .test_downstream_rx_8b_data(), - .test_downstream_rx_state_machine(), - .test_downstream_tx_en(), - .test_downstream_tx_8b_data(), - .test_downstream_tx_10b_data(), - .test_upstream_rx_10b_data(), - .test_upstream_rx_8b_data(), - .test_upstream_rx_state_machine(), - .test_upstream_tx_en(), - .test_upstream_tx_8b_data(), - .test_upstream_tx_10b_data() - ); - - -SpiSlv i_spiSlv( - .reset(~resetn), - .clock(clk_10m_a), - - .io_isOnline(isOnline), - .io_isLast(isLast_temp1), - .io_DCIn(DCIn), - - .param_data2(`DATA2), - .param_data3(`DATA3), - .param_data4(`DATA4), - .param_data5(`DATA5), - .param_data6(`DATA6), - .param_data7(`DATA7), - .param_data8(`DATA8), - .param_data9(`DATA9), - .param_vendorID(`VENDORID), - .param_moduleID(`MODULEID), - .param_hwVersion(`HWVERSION), - .param_swVersion(`SWVERSION), - .param_serial(`SERIAL), - - .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), - .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), - .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid), - .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err), - .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready), - .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in), - .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), - .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err), - - .LED_PR(LED_PR), - .spi_sck(sck), - .spi_mosi(mosi), - .spi_miso(miso), - .spi_csn(csn), - .clk100MIO(clk_100m_a), - .interrupt(interrupt) -); - - - - -endmodule - - - - diff --git a/src/test/scala/ethPhy.scala.bk b/src/test/scala/ethPhy.scala.bk deleted file mode 100644 index da98117..0000000 --- a/src/test/scala/ethPhy.scala.bk +++ /dev/null @@ -1,1353 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -class EthPhy extends RawModule{ - - class EthPhyIO extends Bundle{ - val m_rst_n_i = Input(Bool()) - - val mtx_clk_o = Output(Bool()) - val mtxd_i = Input(UInt(4.W)) - val mtxen_i = Input(Bool()) - val mtxerr_i = Input( Bool() ) - - val mrx_clk_o = Output(Bool()) - val mrxd_o = Output(UInt(4.W)) - val mrxdv_o = Output(Bool()) - val mrxerr_o = Output(Bool()) - - val mcoll_o = Output(Bool()) - val mcrs_o = Output(Bool()) - - val mdc_i = Input(Bool()) - val md_i = Input(Bool()) - val md_o = Output(Bool()) - } - - val io: EthPhyIO = IO(new EthPhyIO) - - - // Control register - val control_bit15 = Reg(Bool()) - val control_bit14_10 = Reg(UInt(5.W)) - val control_bit9 = Reg(Bool()) - val control_bit8_0 = Reg(UInt(9.W)) - - // Status register - wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT; - wire status_bit8 = `EXTENDED_STATUS; - wire status_bit7 = 1'b0; // reserved - reg [6:0] status_bit6_0; - // PHY ID register 1 - wire [15:0] phy_id1 = `PHY_ID1; - // PHY ID register 2 - wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM}; - //-------------------------------------------------------------------- - // - // Data MEMORY - reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width - - - -} - -module eth_phy // This PHY model simulate simplified Intel LXT971A PHY - - - - - -////////////////////////////////////////////////////////////////////// -// -// PHY clocks - RX & TX -// -////////////////////////////////////////////////////////////////////// - -reg mtx_clk_o; -reg mrx_clk_o; - -// random generator for a RX period when link is down -real rx_link_down_halfperiod; - -always@(status_bit6_0[2]) -begin - if (!status_bit6_0[2]) // Link is down - begin - #1 rx_link_down_halfperiod = ({$random} % 243) + 13; - `ifdef VERBOSE - #1 $fdisplay(phy_log, " (%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!", - $time, (1000/(rx_link_down_halfperiod*2)) ); - `endif - end -end - -`ifdef VERBOSE -always@(status_bit6_0[2]) -begin - if (!status_bit6_0[2]) // Link is down - #1 $fdisplay(phy_log, " (%0t)(%m)Ethernet link is down!", $time); - else - #1 $fdisplay(phy_log, " (%0t)(%m)Ethernet link is up!", $time); -end -`endif - -// speed selection signal eth_speed: 1'b1 - 100 Mbps, 1'b0 - 10 Mbps -wire eth_speed; - -assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) ); - -`ifdef VERBOSE -always@(eth_speed) -begin - if (eth_speed) - #1 $fdisplay(phy_log, " (%0t)(%m)PHY configured to 100 Mbps!", $time); - else - #1 $fdisplay(phy_log, " (%0t)(%m)PHY configured tp 10 Mbps!", $time); -end -`endif - -// different clock calculation between RX and TX, so that there is alsways a litle difference -/*initial -begin - set_mrx_equal_mtx = 1; // default -end*/ - -always -begin - mtx_clk_o = 0; - #7; - forever - begin - if (eth_speed) // 100 Mbps - 25 MHz, 40 ns - begin - #20 mtx_clk_o = ~mtx_clk_o; - end - else // 10 Mbps - 2.5 MHz, 400 ns - begin - #200 mtx_clk_o = ~mtx_clk_o; - end - end -end - -always -begin - // EQUAL mrx_clk to mtx_clk - mrx_clk_o = 0; - #7; - forever - begin - if (eth_speed) // 100 Mbps - 25 MHz, 40 ns - begin - #20 mrx_clk_o = ~mrx_clk_o; - end - else // 10 Mbps - 2.5 MHz, 400 ns - begin - #200 mrx_clk_o = ~mrx_clk_o; - end - end - // DIFFERENT mrx_clk than mtx_clk -/* mrx_clk_diff_than_mtx = 1; - #3; - forever - begin - if (status_bit6_0[2]) // Link is UP - begin - if (eth_speed) // 100 Mbps - 25 MHz, 40 ns - begin - //#(((1/0.025001)/2)) - #19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz - end - else // 10 Mbps - 2.5 MHz, 400 ns - begin - //#(((1/0.0024999)/2)) - #200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz - end - end - else // Link is down - begin - #(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz - end - end*/ -// // set output mrx_clk -// if (set_mrx_equal_mtx) -// mrx_clk_o = mrx_clk_equal_to_mtx; -// else -// mrx_clk_o = mrx_clk_diff_than_mtx; -end - -// set output mrx_clk -//assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ; - -////////////////////////////////////////////////////////////////////// -// -// PHY management (MIIM) interface -// -////////////////////////////////////////////////////////////////////// -reg respond_to_all_phy_addr; // PHY will respond to all phy addresses -reg no_preamble; // PHY responds to frames without preamble - -integer md_transfer_cnt; // counter countes the value of whole data transfer -reg md_transfer_cnt_reset; // for reseting the counter -reg md_io_reg; // registered input -reg md_io_output; // registered output -reg md_io_rd_wr; // op-code latched (read or write) -reg md_io_enable; // output enable -reg [4:0] phy_address; // address of PHY device -reg [4:0] reg_address; // address of a register -reg md_get_phy_address; // for shifting PHY address in -reg md_get_reg_address; // for shifting register address in -reg [15:0] reg_data_in; // data to be written in a register -reg md_get_reg_data_in; // for shifting data in -reg md_put_reg_data_in; // for storing data into a selected register -reg [15:0] reg_data_out; // data to be read from a register -reg md_put_reg_data_out; // for registering data from a selected register - -wire [15:0] register_bus_in; // data bus to a selected register -reg [15:0] register_bus_out; // data bus from a selected register - -initial -begin - md_io_enable = 1'b0; - respond_to_all_phy_addr = 1'b0; - no_preamble = 1'b0; -end - -// tristate output -assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ; - -// registering input -always@(posedge mdc_i or negedge m_rst_n_i) -begin - if (!m_rst_n_i) - md_io_reg <= #1 0; - else - md_io_reg <= #1 md_io; -end - -// getting (shifting) PHY address, Register address and Data in -// putting Data out and shifting -always@(posedge mdc_i or negedge m_rst_n_i) -begin - if (!m_rst_n_i) - begin - phy_address <= 0; - reg_address <= 0; - reg_data_in <= 0; - reg_data_out <= 0; - md_io_output <= 0; - end - else - begin - if (md_get_phy_address) - begin - phy_address[4:1] <= phy_address[3:0]; // correct address is `ETH_PHY_ADDR - phy_address[0] <= md_io; - end - if (md_get_reg_address) - begin - reg_address[4:1] <= reg_address[3:0]; - reg_address[0] <= md_io; - end - if (md_get_reg_data_in) - begin - reg_data_in[15:1] <= reg_data_in[14:0]; - reg_data_in[0] <= md_io; - end - if (md_put_reg_data_out) - begin - reg_data_out <= register_bus_out; - end - if (md_io_enable) - begin - md_io_output <= reg_data_out[15]; - reg_data_out[15:1] <= reg_data_out[14:0]; - reg_data_out[0] <= 1'b0; - end - end -end - -assign #1 register_bus_in = reg_data_in; // md_put_reg_data_in - allows writing to a selected register - -// counter for transfer to and from MIIM -always@(posedge mdc_i or negedge m_rst_n_i) -begin - if (!m_rst_n_i) - begin - if (no_preamble) - md_transfer_cnt <= 33; - else - md_transfer_cnt <= 1; - end - else - begin - if (md_transfer_cnt_reset) - begin - if (no_preamble) - md_transfer_cnt <= 33; - else - md_transfer_cnt <= 1; - end - else if (md_transfer_cnt < 64) - begin - md_transfer_cnt <= md_transfer_cnt + 1'b1; - end - else - begin - if (no_preamble) - md_transfer_cnt <= 33; - else - md_transfer_cnt <= 1; - end - end -end - -// MIIM transfer control -always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or - phy_address or respond_to_all_phy_addr or no_preamble) -begin - #1; - while ((m_rst_n_i) && (md_transfer_cnt <= 64)) - begin - // reset the signal - put registered data in the register (when write) - // check preamble - if (md_transfer_cnt < 33) - begin - #4 md_put_reg_data_in = 1'b0; - if (md_io_reg !== 1'b1) - begin - #1 md_transfer_cnt_reset = 1'b1; - end - else - begin - #1 md_transfer_cnt_reset = 1'b0; - end - end - - // check start bits - else if (md_transfer_cnt == 33) - begin - if (no_preamble) - begin - #4 md_put_reg_data_in = 1'b0; - if (md_io_reg === 1'b0) - begin - #1 md_transfer_cnt_reset = 1'b0; - end - else - begin - #1 md_transfer_cnt_reset = 1'b1; - //if ((md_io_reg !== 1'bz) && (md_io_reg !== 1'b1)) - if (md_io_reg !== 1'bz) - begin - // ERROR - start ! - `ifdef VERBOSE - $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time); - `endif - #10 $stop; - end - end - end - else // with preamble - begin - #4 ; - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time); - `endif - // check start bit only if md_transfer_cnt_reset is inactive, because if - // preamble suppression was changed start bit should not be checked - if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0)) - begin - // ERROR - start ! - `ifdef VERBOSE - $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time); - `endif - #10 $stop; - end - end - end - - else if (md_transfer_cnt == 34) - begin - #4; - if (md_io_reg !== 1'b1) - begin - // ERROR - start ! - #1; - `ifdef VERBOSE - if (no_preamble) - $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time); - else - $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit", $time); - `endif - #10 $stop; - end - else - begin - `ifdef VERBOSE - if (no_preamble) - #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - 2 start bits received (without preamble)", $time); - else - #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - 2 start bits received", $time); - `endif - end - end - - // register the op-code (rd / wr) - else if (md_transfer_cnt == 35) - begin - #4; - if (md_io_reg === 1'b1) - begin - #1 md_io_rd_wr = 1'b1; - end - else - begin - #1 md_io_rd_wr = 1'b0; - end - end - - else if (md_transfer_cnt == 36) - begin - #4; - if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1)) - begin - #1 md_io_rd_wr = 1'b1; // reading from PHY registers - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m)MIIM - op-code for READING from registers", $time); - `endif - end - else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0)) - begin - #1 md_io_rd_wr = 1'b0; // writing to PHY registers - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m)MIIM - op-code for WRITING to registers", $time); - `endif - end - else - begin - // ERROR - wrong opcode ! - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong OP-CODE", $time); - `endif - #10 $stop; - end - // set the signal - get PHY address - begin - #1 md_get_phy_address = 1'b1; - end - end - - // reset the signal - get PHY address - else if (md_transfer_cnt == 41) - begin - #4 md_get_phy_address = 1'b0; - // set the signal - get register address - #1 md_get_reg_address = 1'b1; - end - - // reset the signal - get register address - // set the signal - put register data to output register - else if (md_transfer_cnt == 46) - begin - #4 md_get_reg_address = 1'b0; - #1 md_put_reg_data_out = 1'b1; - end - - // reset the signal - put register data to output register - // set the signal - enable md_io as output when read - else if (md_transfer_cnt == 47) - begin - #4 md_put_reg_data_out = 1'b0; - if (md_io_rd_wr) //read - begin - if (md_io_reg !== 1'bz) - begin - // ERROR - turn around ! - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong turn-around cycle before reading data out", $time); - `endif - #10 $stop; - end - if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address - begin - #1 md_io_enable = 1'b1; - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address); - `endif - end - else - begin - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address); - `endif - end - end - else // write - begin - #1 md_io_enable = 1'b0; - // check turn around cycle when write on clock 47 - if (md_io_reg !== 1'b1) - begin - // ERROR - turn around ! - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 1. turn-around cycle before writing data in", - $time); - `endif - #10 $stop; - end - end - end - - // set the signal - get register data in when write - else if (md_transfer_cnt == 48) - begin - #4; - if (!md_io_rd_wr) // write - begin - #1 md_get_reg_data_in = 1'b1; - // check turn around cycle when write on clock 48 - if (md_io_reg !== 1'b0) - begin - // ERROR - turn around ! - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 2. turn-around cycle before writing data in", - $time); - `endif - #10 $stop; - end - end - else // read - begin - #1 md_get_reg_data_in = 1'b0; - end - end - - // reset the signal - enable md_io as output when read - // reset the signal - get register data in when write - // set the signal - put registered data in the register when write - else if (md_transfer_cnt == 64) - begin - #1 md_io_enable = 1'b0; - #4 md_get_reg_data_in = 1'b0; - if (!md_io_rd_wr) // write - begin - if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address - begin - #1 md_put_reg_data_in = 1'b1; - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address); - $fdisplay(phy_log, " (%0t)(%m)MIIM - WRITING to register %x COMPLETED!", $time, reg_address); - `endif - end - else - begin - `ifdef VERBOSE - #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address); - $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO WRITING to register %x !", $time, reg_address); - `endif - end - end - else // read - begin - `ifdef VERBOSE - if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address - #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - READING from register %x COMPLETED!", - $time, reg_address); - else - #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO READING from register %x !", $time, reg_address); - `endif - end - end - - // wait for one clock period - @(posedge mdc_i) - #1; - end -end - -//==================================================================== -// -// PHY management (MIIM) REGISTERS -// -//==================================================================== -// -// Supported registers (normal operation): -// -// Addr | Register Name -//-------------------------------------------------------------------- -// 0 | Control reg. -// 1 | Status reg. #1 -// 2 | PHY ID reg. 1 -// 3 | PHY ID reg. 2 -//---------------------- -// Addr | Data MEMORY |--> for testing -// -//-------------------------------------------------------------------- -// -// Control register -// reg control_bit15; // self clearing bit -// reg [14:10] control_bit14_10; -// reg control_bit9; // self clearing bit -// reg [8:0] control_bit8_0; -// Status register -// wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT; -// wire status_bit8 = `EXTENDED_STATUS; -// wire status_bit7 = 1'b0; // reserved -// reg [6:0] status_bit6_0 = `DEFAULT_STATUS; -// PHY ID register 1 -// wire [15:0] phy_id1 = `PHY_ID1; -// PHY ID register 2 -// wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM}; -//-------------------------------------------------------------------- -// -// Data MEMORY -// reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width -// -//==================================================================== - -////////////////////////////////////////////////////////////////////// -// -// PHY management (MIIM) REGISTER control -// -////////////////////////////////////////////////////////////////////// - -// wholy writable registers for walking ONE's on data, phy and reg. addresses -reg registers_addr_data_test_operation; - -// Non writable status registers -initial // always -begin - #1 status_bit6_0[6] = no_preamble; - status_bit6_0[5] = 1'b0; - status_bit6_0[3] = 1'b1; - status_bit6_0[0] = 1'b1; -end -always@(posedge mrx_clk_o) -begin - status_bit6_0[4] <= #1 1'b0; - status_bit6_0[1] <= #1 1'b0; -end -initial -begin - status_bit6_0[2] = 1'b1; - registers_addr_data_test_operation = 0; -end - -// Reading from a selected registers -always@(reg_address or registers_addr_data_test_operation or md_put_reg_data_out or - control_bit15 or control_bit14_10 or control_bit9 or control_bit8_0 or - status_bit15_9 or status_bit8 or status_bit7 or status_bit6_0 or - phy_id1 or phy_id2) -begin - if (registers_addr_data_test_operation) // test operation - begin - if (md_put_reg_data_out) // read enable - begin - register_bus_out = #1 data_mem[reg_address]; - end - end - else // normal operation - begin - if (md_put_reg_data_out) // read enable - begin - case (reg_address) - 5'h0: register_bus_out = #1 {control_bit15, control_bit14_10, control_bit9, control_bit8_0}; - 5'h1: register_bus_out = #1 {status_bit15_9, status_bit8, status_bit7, status_bit6_0}; - 5'h2: register_bus_out = #1 phy_id1; - 5'h3: register_bus_out = #1 phy_id2; - default: register_bus_out = #1 16'hDEAD; - endcase - end - end -end - -// Self clear control signals -reg self_clear_d0; -reg self_clear_d1; -reg self_clear_d2; -reg self_clear_d3; -// Self clearing control -always@(posedge mdc_i or negedge m_rst_n_i) -begin - if (!m_rst_n_i) - begin - self_clear_d0 <= #1 0; - self_clear_d1 <= #1 0; - self_clear_d2 <= #1 0; - self_clear_d3 <= #1 0; - end - else - begin - self_clear_d0 <= #1 md_put_reg_data_in; - self_clear_d1 <= #1 self_clear_d0; - self_clear_d2 <= #1 self_clear_d1; - self_clear_d3 <= #1 self_clear_d2; - end -end - -// Writing to a selected register -always@(posedge mdc_i or negedge m_rst_n_i) -begin - if ((!m_rst_n_i) || (control_bit15)) - begin - if (!registers_addr_data_test_operation) // normal operation - begin - control_bit15 <= #1 0; - control_bit14_10 <= #1 {1'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2'b0}; - control_bit9 <= #1 0; - control_bit8_0 <= #1 {`LED_CFG3, 8'b0}; - end - end - else - begin - if (registers_addr_data_test_operation) // test operation - begin - if (md_put_reg_data_in) - begin - data_mem[reg_address] <= #1 register_bus_in[15:0]; - end - end - else // normal operation - begin - // bits that are normaly written - if (md_put_reg_data_in) - begin - case (reg_address) - 5'h0: - begin - control_bit14_10 <= #1 register_bus_in[14:10]; - control_bit8_0 <= #1 register_bus_in[8:0]; - end - default: - begin - end - endcase - end - // self cleared bits written - if ((md_put_reg_data_in) && (reg_address == 5'h0)) - begin - control_bit15 <= #1 register_bus_in[15]; - control_bit9 <= #1 register_bus_in[9]; - end - else if (self_clear_d3) // self cleared bits cleared - begin - control_bit15 <= #1 1'b0; - control_bit9 <= #1 1'b0; - end - end - end -end - -////////////////////////////////////////////////////////////////////// -// -// PHY <-> MAC control (RX and TX clocks are at the begining) -// -////////////////////////////////////////////////////////////////////// - -// CARRIER SENSE & COLLISION - -// MAC common signals -reg mcoll_o; -reg mcrs_o; -// Internal signals controling Carrier sense & Collision - // MAC common signals generated when appropriate transfer -reg mcrs_rx; -reg mcrs_tx; - // delayed mtxen_i signal for generating delayed tx carrier sense -reg mtxen_d1; -reg mtxen_d2; -reg mtxen_d3; -reg mtxen_d4; -reg mtxen_d5; -reg mtxen_d6; - // collision signal set or rest within task for controling collision -reg task_mcoll; - // carrier sense signal set or rest within task for controling carrier sense -reg task_mcrs; -reg task_mcrs_lost; - // do not generate collision in half duplex - not normal operation -reg no_collision_in_half_duplex; - // generate collision in full-duplex mode also - not normal operation -reg collision_in_full_duplex; - // do not generate carrier sense in half duplex mode - not normal operation -reg no_carrier_sense_in_tx_half_duplex; -reg no_carrier_sense_in_rx_half_duplex; - // generate carrier sense during TX in full-duplex mode also - not normal operation -reg carrier_sense_in_tx_full_duplex; - // do not generate carrier sense during RX in full-duplex mode - not normal operation -reg no_carrier_sense_in_rx_full_duplex; - // on RX: delay after carrier sense signal; on TX: carrier sense delayed (delay is one clock period) -reg real_carrier_sense; - -initial -begin - mcrs_rx = 0; - mcrs_tx = 0; - task_mcoll = 0; - task_mcrs = 0; - task_mcrs_lost = 0; - no_collision_in_half_duplex = 0; - collision_in_full_duplex = 0; - no_carrier_sense_in_tx_half_duplex = 0; - no_carrier_sense_in_rx_half_duplex = 0; - carrier_sense_in_tx_full_duplex = 0; - no_carrier_sense_in_rx_full_duplex = 0; - real_carrier_sense = 0; -end - -// Collision -always@(m_rst_n_i or control_bit8_0 or collision_in_full_duplex or - mcrs_rx or mcrs_tx or task_mcoll or no_collision_in_half_duplex - ) -begin - if (!m_rst_n_i) - mcoll_o = 0; - else - begin - if (control_bit8_0[8]) // full duplex - begin - if (collision_in_full_duplex) // collision is usually not asserted in full duplex - begin - mcoll_o = ((mcrs_rx && mcrs_tx) || task_mcoll); - `ifdef VERBOSE - if (mcrs_rx && mcrs_tx) - $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex!", $time); - if (task_mcoll) - $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex from TASK!", $time); - `endif - end - else - begin - mcoll_o = task_mcoll; - `ifdef VERBOSE - if (task_mcoll) - $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex from TASK!", $time); - `endif - end - end - else // half duplex - begin - mcoll_o = ((mcrs_rx && mcrs_tx && !no_collision_in_half_duplex) || - task_mcoll); - `ifdef VERBOSE - if (mcrs_rx && mcrs_tx) - $fdisplay(phy_log, " (%0t)(%m) Collision set in HalfDuplex!", $time); - if (task_mcoll) - $fdisplay(phy_log, " (%0t)(%m) Collision set in HalfDuplex from TASK!", $time); - `endif - end - end -end - -// Carrier sense -always@(m_rst_n_i or control_bit8_0 or carrier_sense_in_tx_full_duplex or - no_carrier_sense_in_rx_full_duplex or - no_carrier_sense_in_tx_half_duplex or - no_carrier_sense_in_rx_half_duplex or - mcrs_rx or mcrs_tx or task_mcrs or task_mcrs_lost - ) -begin - if (!m_rst_n_i) - mcrs_o = 0; - else - begin - if (control_bit8_0[8]) // full duplex - begin - if (carrier_sense_in_tx_full_duplex) // carrier sense is usually not asserted during TX in full duplex - mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || - mcrs_tx || task_mcrs) && !task_mcrs_lost; - else - mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || - task_mcrs) && !task_mcrs_lost; - end - else // half duplex - begin - mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_half_duplex) || - (mcrs_tx && !no_carrier_sense_in_tx_half_duplex) || - task_mcrs) && !task_mcrs_lost; - end - end -end - -// MAC TX CONTROL (RECEIVING AT PHY) - -// storage memory for TX data received from MAC -reg [7:0] tx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width -reg [31:0] tx_mem_addr_in; // address for storing to TX memory -reg [7:0] tx_mem_data_in; // data for storing to TX memory -reg [31:0] tx_cnt; // counts nibbles - -// control data of a TX packet for upper layer of testbench -reg tx_preamble_ok; -reg tx_sfd_ok; -// if there is a drible nibble, then tx packet is not byte aligned! -reg tx_byte_aligned_ok; -// complete length of TX packet (Bytes) received (without preamble and SFD) -reg [31:0] tx_len; -// complete length of TX packet (Bytes) received (without preamble and SFD) untill MTxErr signal was set first -reg [31:0] tx_len_err; - -// TX control -always@(posedge mtx_clk_o) -begin - // storing data and basic checking of frame - if (!m_rst_n_i) - begin - tx_cnt <= 0; - tx_preamble_ok <= 0; - tx_sfd_ok <= 0; - tx_len <= 0; - tx_len_err <= 0; - end - else - begin - if (!mtxen_i) - begin - tx_cnt <= 0; - end - else - begin - // tx nibble counter - tx_cnt <= tx_cnt + 1; - // set initial values and check first preamble nibble - if (tx_cnt == 0) - begin - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m) TX frame started with tx_en set!", $time); - `endif - if (mtxd_i == 4'h5) - tx_preamble_ok <= 1; - else - tx_preamble_ok <= 0; - tx_sfd_ok <= 0; - tx_byte_aligned_ok <= 0; - tx_len <= 0; - tx_len_err <= 0; -// tx_mem_addr_in <= 0; - end - - // check preamble - if ((tx_cnt > 0) && (tx_cnt <= 13)) - begin - if ((tx_preamble_ok != 1) || (mtxd_i != 4'h5)) - tx_preamble_ok <= 0; - end - // check SFD - if (tx_cnt == 14) - begin - `ifdef VERBOSE - if (tx_preamble_ok == 1) - $fdisplay(phy_log, " (%0t)(%m) TX frame preamble OK!", $time); - else - $fdisplay(phy_log, "*E (%0t)(%m) TX frame preamble NOT OK!", $time); - `endif - if (mtxd_i == 4'h5) - tx_sfd_ok <= 1; - else - tx_sfd_ok <= 0; - end - if (tx_cnt == 15) - begin - if ((tx_sfd_ok != 1) || (mtxd_i != 4'hD)) - tx_sfd_ok <= 0; - end - - // control for storing addresses, type/length, data and FCS to TX memory - if (tx_cnt > 15) - begin - if (tx_cnt == 16) - begin - `ifdef VERBOSE - if (tx_sfd_ok == 1) - $fdisplay(phy_log, " (%0t)(%m) TX frame SFD OK!", $time); - else - $fdisplay(phy_log, "*E (%0t)(%m) TX frame SFD NOT OK!", $time); - `endif - end - - if (tx_cnt[0] == 0) - begin - tx_mem_data_in[3:0] <= mtxd_i; // storing LSB nibble - tx_byte_aligned_ok <= 0; // if transfer will stop after this, then there was drible nibble - end - else - begin - tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]}; // storing data into tx memory - tx_len <= tx_len + 1; // enlarge byte length counter - tx_byte_aligned_ok <= 1; // if transfer will stop after this, then transfer is byte alligned - tx_mem_addr_in <= tx_mem_addr_in + 1'b1; - end - - if (mtxerr_i) - tx_len_err <= tx_len; - end - end - end - - // generating CARRIER SENSE for TX with or without delay - if (!m_rst_n_i) - begin - mcrs_tx <= 0; - mtxen_d1 <= 0; - mtxen_d2 <= 0; - mtxen_d3 <= 0; - mtxen_d4 <= 0; - mtxen_d5 <= 0; - mtxen_d6 <= 0; - end - else - begin - mtxen_d1 <= mtxen_i; - mtxen_d2 <= mtxen_d1; - mtxen_d3 <= mtxen_d2; - mtxen_d4 <= mtxen_d3; - mtxen_d5 <= mtxen_d4; - mtxen_d6 <= mtxen_d5; - if (real_carrier_sense) - mcrs_tx <= mtxen_d6; - else - mcrs_tx <= mtxen_i; - end -end - -`ifdef VERBOSE -reg frame_started; - -initial -begin - frame_started = 0; -end -always@(posedge mtxen_i) -begin - frame_started <= 1; -end -always@(negedge mtxen_i) -begin - if (frame_started) - begin - $fdisplay(phy_log, " (%0t)(%m) TX frame ended with tx_en reset!", $time); - frame_started <= 0; - end -end - -always@(posedge mrxerr_o) -begin - $fdisplay(phy_log, " (%0t)(%m) RX frame ERROR signal was set!", $time); -end -`endif - -////////////////////////////////////////////////////////////////////// -// -// Tasks for PHY <-> MAC transactions -// -////////////////////////////////////////////////////////////////////// - -initial -begin - tx_mem_addr_in = 0; -end - -// setting the address of tx_mem, to set the starting point of tx packet -task set_tx_mem_addr; - input [31:0] tx_mem_address; -begin - #1 tx_mem_addr_in = tx_mem_address; -end -endtask // set_tx_mem_addr - -// storage memory for RX data to be transmited to MAC -reg [7:0] rx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width - -// MAC RX signals -reg [3:0] mrxd_o; -reg mrxdv_o; -reg mrxerr_o; - -initial -begin - mrxd_o = 0; - mrxdv_o = 0; - mrxerr_o = 0; - mcrs_rx = 0; -end - -task send_rx_packet; - input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555 - input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 - input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5 - input [31:0] start_addr; // start address - input [31:0] len; // length of frame in Bytes (without preamble and SFD) - input plus_drible_nibble; // if length is longer for one nibble - integer rx_cnt; - reg [31:0] rx_mem_addr_in; // address for reading from RX memory - reg [7:0] rx_mem_data_out; // data for reading from RX memory -begin - @(posedge mrx_clk_o); - // generating CARRIER SENSE for TX with or without delay - if (real_carrier_sense) - #1 mcrs_rx = 1; - else - #1 mcrs_rx = 0; - @(posedge mrx_clk_o); - #1 mcrs_rx = 1; - #1 mrxdv_o = 1; - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m) RX frame started with rx_dv set!", $time); - `endif - // set initial rx memory address - rx_mem_addr_in = start_addr; - - // send preamble - for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1) - begin - #1 mrxd_o = preamble_data[3:0]; - #1 preamble_data = preamble_data >> 4; - @(posedge mrx_clk_o); - end - - // send SFD - for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1) - begin - #1 mrxd_o = sfd_data[3:0]; - #1 sfd_data = sfd_data >> 4; - @(posedge mrx_clk_o); - end - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m) RX frame preamble and SFD sent!", $time); - `endif - // send packet's addresses, type/length, data and FCS - for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1) - begin - #1; - rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]]; - mrxd_o = rx_mem_data_out[3:0]; - @(posedge mrx_clk_o); - #1; - mrxd_o = rx_mem_data_out[7:4]; - rx_mem_addr_in = rx_mem_addr_in + 1; - @(posedge mrx_clk_o); - #1; - end - if (plus_drible_nibble) - begin - rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]]; - mrxd_o = rx_mem_data_out[3:0]; - @(posedge mrx_clk_o); - end - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time); - `endif - #1 mcrs_rx = 0; - #1 mrxdv_o = 0; - @(posedge mrx_clk_o); - `ifdef VERBOSE - $fdisplay(phy_log, " (%0t)(%m) RX frame ended with rx_dv reset!", $time); - `endif -end -endtask // send_rx_packet - - - -task GetDataOnMRxD; - input [15:0] Len; - input [31:0] TransferType; - integer tt; - - begin - @ (posedge mrx_clk_o); - #1 mrxdv_o=1'b1; - - for(tt=0; tt<15; tt=tt+1) - begin - mrxd_o=4'h5; // preamble - @ (posedge mrx_clk_o); - #1; - end - - mrxd_o=4'hd; // SFD - - for(tt=1; tt<(Len+1); tt=tt+1) - begin - @ (posedge mrx_clk_o); - #1; - if(TransferType == `UNICAST_XFR && tt == 1) - mrxd_o = 4'h0; // Unicast transfer - else if(TransferType == `BROADCAST_XFR && tt < 7) - mrxd_o = 4'hf; - else - mrxd_o = tt[3:0]; // Multicast transfer - - @ (posedge mrx_clk_o); - #1; - - if(TransferType == `BROADCAST_XFR && tt == 6) - mrxd_o = 4'he; - else - - if(TransferType == `BROADCAST_XFR && tt < 7) - mrxd_o = 4'hf; - else - mrxd_o = tt[7:4]; - end - - @ (posedge mrx_clk_o); - #1; - mrxdv_o = 1'b0; - end -endtask // GetDataOnMRxD - - -////////////////////////////////////////////////////////////////////// -// -// Tastks for controling PHY statuses and rx error -// -////////////////////////////////////////////////////////////////////// - -// Link control tasks -task link_up_down; - input test_op; -begin - #1 status_bit6_0[2] = test_op; // 1 - link up; 0 - link down -end -endtask - -// RX error -task rx_err; - input test_op; -begin - #1 mrxerr_o = test_op; // 1 - RX error set; 0 - RX error reset -end -endtask - -////////////////////////////////////////////////////////////////////// -// -// Tastks for controling PHY carrier sense and collision -// -////////////////////////////////////////////////////////////////////// - -// Collision -task collision; - input test_op; -begin - #1 task_mcoll = test_op; -end -endtask - -// Carrier sense -task carrier_sense; - input test_op; -begin - #1 task_mcrs = test_op; -end -endtask - -// Carrier sense lost - higher priority than Carrier sense task -task carrier_sense_lost; - input test_op; -begin - #1 task_mcrs_lost = test_op; -end -endtask - -// No collision detection in half duplex -task no_collision_hd_detect; - input test_op; -begin - #1 no_collision_in_half_duplex = test_op; -end -endtask - -// Collision detection in full duplex also -task collision_fd_detect; - input test_op; -begin - #1 collision_in_full_duplex = test_op; -end -endtask - -// No carrier sense detection at TX in half duplex -task no_carrier_sense_tx_hd_detect; - input test_op; -begin - #1 no_carrier_sense_in_tx_half_duplex = test_op; -end -endtask - -// No carrier sense detection at RX in half duplex -task no_carrier_sense_rx_hd_detect; - input test_op; -begin - #1 no_carrier_sense_in_rx_half_duplex = test_op; -end -endtask - -// Carrier sense detection at TX in full duplex also -task carrier_sense_tx_fd_detect; - input test_op; -begin - #1 carrier_sense_in_tx_full_duplex = test_op; -end -endtask - -// No carrier sense detection at RX in full duplex -task no_carrier_sense_rx_fd_detect; - input test_op; -begin - #1 no_carrier_sense_in_rx_full_duplex = test_op; -end -endtask - -// Set real delay on carrier sense signal (and therefor collision signal) -task carrier_sense_real_delay; - input test_op; -begin - #1 real_carrier_sense = test_op; -end -endtask - -////////////////////////////////////////////////////////////////////// -// -// Tastks for controling PHY management test operation -// -////////////////////////////////////////////////////////////////////// - -// Set registers to test operation and respond to all phy addresses -task test_regs; - input test_op; -begin - #1 registers_addr_data_test_operation = test_op; - respond_to_all_phy_addr = test_op; -end -endtask - -// Clears data memory for testing the MII -task clear_test_regs; - integer i; -begin - for (i = 0; i < 32; i = i + 1) - begin - #1 data_mem[i] = 16'h0; - end -end -endtask - -// Accept frames with preamble suppresed -task preamble_suppresed; - input test_op; -begin - #1 no_preamble = test_op; - md_transfer_cnt_reset = 1'b1; - @(posedge mdc_i); - #1 md_transfer_cnt_reset = 1'b0; -end -endtask - - - - - -endmodule - - diff --git a/src/test/scala/gcd/BackPlaneChainTest.scala.bk b/src/test/scala/gcd/BackPlaneChainTest.scala.bk deleted file mode 100644 index d0ee104..0000000 --- a/src/test/scala/gcd/BackPlaneChainTest.scala.bk +++ /dev/null @@ -1,87 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class BackPlaneChainTestIO extends Bundle{ - - val clk400 = Input( Vec(6, Bool() )) - - - - - val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle)) - - val led = Output( Vec( 5, Bool() ) ) - - -} - -class BackPlaneChainTest extends Module{ - val io: BackPlaneChainTestIO = IO(new BackPlaneChainTestIO) - - - val mst = Module(new BackBoardMst) - val slv = for( i <- 0 until 5 ) yield { Module(new BackBoardSlv) } - - - - mst.io.clk4 := io.clk400(5) - - - withClockAndReset( io.clk400(5).asClock, reset.asAsyncReset ){ - io.spi.ready := true.B - val cnt = RegInit(0.U(7.W)) - val spiInfo = Reg( new CDR_Master_Interface_Bundle ) - mst.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 ) - val cs = RegInit(true.B); mst.io.CS := cs - val sckCnt = RegInit(1.U(2.W)); mst.io.SCK := sckCnt.extract(1) === 1.U - - - when( ~cs ){ - sckCnt := sckCnt + 1.U - } - - when( io.spi.fire ){ - cs := false.B - cnt := 0.U - spiInfo := io.spi.bits - } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){ - cnt := cnt + 1.U - spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), mst.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle) - } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){ - cs := true.B - } - } - - - for( i <- 0 until 5 ) { - slv(i).io.localHost := i.U - slv(i).io.clk4 := io.clk400(i) - - slv(i).sw := 0.U - slv(i).qeiA := false.B - slv(i).qeiB := false.B - io.led(i) := slv(i).led.extract(0).asBool - - } - - - slv(0).io.upStreamReqDat := mst.io.downStreamRespdat - mst.io.downStreamReqDat := slv(0).io.upStreamRespdat - - slv(1).io.upStreamReqDat := slv(0).io.downStreamRespdat - slv(0).io.downStreamReqDat := slv(1).io.upStreamRespdat - - slv(2).io.upStreamReqDat := slv(1).io.downStreamRespdat - slv(1).io.downStreamReqDat := slv(2).io.upStreamRespdat - - slv(3).io.upStreamReqDat := slv(2).io.downStreamRespdat - slv(2).io.downStreamReqDat := slv(3).io.upStreamRespdat - - slv(4).io.upStreamReqDat := slv(3).io.downStreamRespdat - slv(3).io.downStreamReqDat := slv(4).io.upStreamRespdat - - - slv(4).io.downStreamReqDat := slv(4).io.downStreamRespdat -} \ No newline at end of file diff --git a/src/test/scala/gcd/BackPlaneMstTest.scala.bk b/src/test/scala/gcd/BackPlaneMstTest.scala.bk deleted file mode 100644 index d517aa6..0000000 --- a/src/test/scala/gcd/BackPlaneMstTest.scala.bk +++ /dev/null @@ -1,87 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class BackPlaneMstTestIO extends Bundle{ - - // val SCK = Input(Bool()) - val interrupt = Output(Bool()) - val clk4 = Input( Bool() ) - val reset = Input(Bool()) - - val downStreamRespdat = Output(Bool()) - - val req = Flipped(Decoupled(new CDRData)) - val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle)) - -} - -class BackPlaneMstTest extends RawModule{ - val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO) - - withClockAndReset( io.clk4.asClock, io.reset.asAsyncReset ){ - val dut = Module(new BackBoardMst) - - io.downStreamRespdat := dut.io.downStreamRespdat - - // dut.io.CS := io.CS - // io.MISO := dut.io.MISO - // dut.io.MOSI := io.MOSI - // dut.io.SCK := io.SCK - - dut.io.clk4 := io.clk4 - io.interrupt := dut.io.interrupt - - - - - - io.spi.ready := true.B - val cnt = RegInit(0.U(7.W)) - val spiInfo = Reg( new CDR_Master_Interface_Bundle ) - dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 ) - val cs = RegInit(true.B); dut.io.CS := cs - val sckCnt = RegInit(1.U(2.W)); dut.io.SCK := sckCnt.extract(1) === 1.U - - when( ~cs ){ - sckCnt := sckCnt + 1.U - } - - when( io.spi.fire ){ - cs := false.B - cnt := 0.U - spiInfo := io.spi.bits - } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){ - cnt := cnt + 1.U - spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle) - } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){ - cs := true.B - } - - - - io.req.ready := true.B - val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat - val reqInfo = RegInit(0.U((new CDRData).getWidth.W)) - val datCnt = RegInit( 0.U(2.W) ) - - datCnt := datCnt + 1.U - - when( datCnt === "b11".U ) { - when( io.req.fire ){ - reqInfo := io.req.bits.asUInt - reqDat := true.B - } .otherwise{ - reqDat := reqInfo.extract( 6+8+32+16-1 ) - reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) - } - } - - - } - - - -} - diff --git a/src/test/scala/gcd/BackPlaneSlvTest.scala.bk b/src/test/scala/gcd/BackPlaneSlvTest.scala.bk deleted file mode 100644 index 84849a0..0000000 --- a/src/test/scala/gcd/BackPlaneSlvTest.scala.bk +++ /dev/null @@ -1,63 +0,0 @@ - -package BACK - -import chisel3._ -import chisel3.util._ - - - - -class BackBoardSlvTestIO extends Bundle{ - val localHost = Input(UInt(6.W)) - - val upStreamRespdat = Output(Bool()) - val downStreamRespdat = Output(Bool()) - - val clk4 = Input( Bool() ) - - - val req = Flipped(Decoupled(new CDRData)) - val rsp = Flipped(Decoupled(new CDRData)) -} - - -class BackBoardSlvTest extends Module{ - val io: BackBoardSlvTestIO = IO(new BackBoardSlvTestIO) - - val dut = Module( new BackBoardSlv) - - dut.io.localHost := "h12".U - dut.io.clk4 := io.clk4 - - io.upStreamRespdat := dut.io.upStreamRespdat - io.downStreamRespdat := dut.io.downStreamRespdat - - io.req.ready := true.B - io.rsp.ready := true.B - - val reqInfo = RegInit(0.U((new CDRData).getWidth.W)) - val rspInfo = RegInit(0.U((new CDRData).getWidth.W)) - val reqDat = RegInit(false.B); dut.io.upStreamReqDat := reqDat - val rspDat = RegInit(false.B); dut.io.downStreamReqDat := rspDat - - when( io.req.fire ){ - reqInfo := io.req.bits.asUInt - reqDat := true.B - } .otherwise{ - reqDat := reqInfo.extract( 6+8+32+16-1 ) - reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) - } - - when( io.rsp.fire ){ - rspInfo := io.rsp.bits.asUInt - rspDat := true.B - } .otherwise{ - rspDat := rspInfo.extract( 6+8+32+16-1 ) - rspInfo := Cat( rspInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) - } - -} - - - - diff --git a/src/test/scala/gcd/MacAXI.scala.bk b/src/test/scala/gcd/MacAXI.scala.bk deleted file mode 100644 index d694d25..0000000 --- a/src/test/scala/gcd/MacAXI.scala.bk +++ /dev/null @@ -1,82 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.devices.tilelink._ - -class MacAXI(implicit p: Parameters) extends Mac{ - - - - val memAXI4SlaveNode = AXI4SlaveNode(Seq( - AXI4SlavePortParameters( - slaves = Seq( - AXI4SlaveParameters( - address = Seq(AddressSet(0x00000000L, 0x7fffffffL)), - regionType = RegionType.UNCACHED, - executable = true, - supportsRead = TransferSizes(32/8, 32/8), - supportsWrite = TransferSizes(32/8, 32/8) - ) - ), - beatBytes = 32 / 8 - ) - )) - - memAXI4SlaveNode := - AXI4Deinterleaver(32/8) := - TLToAXI4() := - tlClientNode - - - - - val axiConfigPort = - AXI4MasterNode( - Seq(AXI4MasterPortParameters( - Seq(AXI4MasterParameters( - name = "Mac Config", - id = IdRange(0, 1), - maxFlight = Some(1), - )) - )) - ) - - val tlError = LazyModule(new TLError( - params = DevNullParams( - address = Seq(AddressSet(0x0, 0x2fffffffL)), - maxAtomic = 0, - maxTransfer = 32/8), - beatBytes = 32 / 8 - )) - - val xbar = TLXbar() - - - tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort - // tlError.node := xbar - - val intSinkNode = IntSinkNode(IntSinkPortSimple()) - intSinkNode := int_node - - val axiCfg = InModuleBody { - axiConfigPort.makeIOs() - } - - val axiMem = InModuleBody { - memAXI4SlaveNode.makeIOs() - } - - val int = InModuleBody { - intSinkNode.makeIOs() - } - - - -} \ No newline at end of file diff --git a/src/test/scala/gcd/Mac_test_top.scala b/src/test/scala/gcd/Mac_test_top.scala deleted file mode 100644 index f0d0578..0000000 --- a/src/test/scala/gcd/Mac_test_top.scala +++ /dev/null @@ -1,41 +0,0 @@ -// package MAC - -// import chisel3._ -// import chisel3.util._ - -// import org.chipsalliance.cde.config._ -// import freechips.rocketchip.diplomacy._ -// import freechips.rocketchip.tilelink._ -// import freechips.rocketchip.interrupts._ - - - -// class MacTest(implicit p: Parameters) extends Mac{ - - - -// val tlClientIONode = -// TLClientNode(Seq(TLMasterPortParameters.v1( -// Seq(TLMasterParameters.v1( -// name = "tlSlvIO", -// sourceId = IdRange(0, 1), -// )) -// ))) - - -// ethReg.configNode := tlClientIONode - -// val intSinkNode = IntSinkNode(IntSinkPortSimple()) -// intSinkNode := ethReg.int_node - -// val tlSlv = InModuleBody { -// tlClientIONode.makeIOs() -// } - -// val int = InModuleBody { -// intSinkNode.makeIOs() -// } - - - -// } \ No newline at end of file diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala deleted file mode 100644 index 3705673..0000000 --- a/src/test/scala/gcd/test.scala +++ /dev/null @@ -1,113 +0,0 @@ -package test - - -import BACK._ - - -import chisel3._ -import chisel3.stage._ - - - - -object testModule extends App { - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new BackBoardMst }), - )) - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO }) - // )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new DIn16 }) - )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new DOut16c }) - )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new DOut16p }) - )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new SpiSlv }) - )) - - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new CDROut }) - // )) - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new CDRIn }) - // )) - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new ShinMst }) - // )) - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new ShinSlvBase }) - // )) - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new picorv32_tl }) - // )) - - - // val cfg = new BackCfg - - // (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( - // ChiselGeneratorAnnotation(() => { - // val soc = LazyModule(new BackSys()(cfg)) - // soc.module - // }) - // )) - - - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new BackPlaneChainTest }) - // )) - - // val cfg = new MacCfg - - // (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-e", "verilog") ++ args, Seq( - // ChiselGeneratorAnnotation(() => { - // val soc = LazyModule(new MacTest()(cfg)) - // soc.module - // }) - // )) - - -// import Wrapeer._ - -// val cfg = new EfConfig - -// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq( -// ChiselGeneratorAnnotation(() => { -// val soc = LazyModule(new EfablessTop()(cfg)) -// soc.module -// }) -// )) - -} - -object testShinModule extends App { - // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq( - // ChiselGeneratorAnnotation(() => { new SlaveParser }), - // )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new ShinTop }), - )) - - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new SimCDR }), - )) - - - -} - diff --git a/tb/ShinBack_tb.v b/tb/ShinBack_tb.v deleted file mode 100644 index 6dad342..0000000 --- a/tb/ShinBack_tb.v +++ /dev/null @@ -1,243 +0,0 @@ - -`timescale 1 ns / 1 ps - - - - - -module ShinBack_tb(); - - - reg clock = 0; - reg overClk = 0; - reg reset = 1; - - reg [15:0] io_FSMC_ADIn; - wire [15:0] io_FSMC_ADOut; - wire io_FSMC_ADOEn; - reg io_FSMC_csn = 1; - reg io_FSMC_rdn = 1; - reg io_FSMC_wrn = 1; - reg io_FSMC_advn; - - - reg io_testIO = 0; - - wire [3:0] downStreamDat; - wire [3:0] upStreamDat; - - - ShinMst s_shinMst( - .clock(clock), - .reset(reset), - - .io_FSMC_ADIn(io_FSMC_ADIn), - .io_FSMC_ADOut(io_FSMC_ADOut), - .io_FSMC_ADOEn(io_FSMC_ADOEn), - .io_FSMC_csn(io_FSMC_csn), - .io_FSMC_rdn(io_FSMC_rdn), - .io_FSMC_wrn(io_FSMC_wrn), - .io_FSMC_advn(io_FSMC_advn), - .io_interrupt(), - .io_testIO(io_testIO), - - .io_serOut(downStreamDat[0]), - .io_serIn(upStreamDat[0]), - .io_overCLK(overClk) - ); - - ShinSlvBase s_ShinSlv0( - .clock(clock), - .reset(reset), - .io_isOnline(), - .io_isLast(1'b0), - .io_DCIn(1'b0), - .io_downSer_out(downStreamDat[1]), - .io_downSer_in(downStreamDat[0]), - .io_upSer_out(upStreamDat[0]), - .io_upSer_in(upStreamDat[1]), - .io_overCLK(overClk), - .led() - ); - - ShinSlvBase s_ShinSlv1( - .clock(clock), - .reset(reset), - .io_isOnline(), - .io_isLast(1'b0), - .io_DCIn(1'b0), - .io_downSer_out(downStreamDat[2]), - .io_downSer_in(downStreamDat[1]), - .io_upSer_out(upStreamDat[1]), - .io_upSer_in(upStreamDat[2]), - .io_overCLK(overClk), - .led() - ); - - ShinSlvBase s_ShinSlv2( - .clock(clock), - .reset(reset), - .io_isOnline(), - .io_isLast(1'b0), - .io_DCIn(1'b0), - .io_downSer_out(downStreamDat[3]), - .io_downSer_in(downStreamDat[2]), - .io_upSer_out(upStreamDat[2]), - .io_upSer_in(upStreamDat[3]), - .io_overCLK(overClk), - .led() - ); - - ShinSlvBase s_ShinSlv3( - .clock(clock), - .reset(reset), - .io_isOnline(), - .io_isLast(1'b1), - .io_DCIn(1'b0), - .io_downSer_out(), - .io_downSer_in(downStreamDat[3]), - .io_upSer_out(upStreamDat[3]), - .io_upSer_in(1'b0), - .io_overCLK(overClk), - .led() - ); - - - - -initial begin - forever #80 clock = ~clock; -end - -initial begin - #10 - forever #20 overClk = ~overClk; -end - -initial begin - # 100 reset = 1; - # 100 reset = 0; -end - - -initial begin - - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 1; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 1; - io_testIO = 0; - - #5005 - - -// @0 <- 512 length | operator - #500 - io_FSMC_ADIn = 16'd0 | (1 << 11); - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 0; - - #500 - io_FSMC_ADIn = (16'd512 << 4) | 16'd0; - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 0; - io_FSMC_advn = 1; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 1; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 1; - -// @1 <- 0 param0 - #500 - io_FSMC_ADIn = 16'd1 | (1 << 11); - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 0; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 0; - io_FSMC_advn = 1; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 1; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 1; - -// @2 <- 0 param1 - #500 - io_FSMC_ADIn = 16'd2 | (1 << 11); - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 0; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 0; - io_FSMC_advn = 1; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 1; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 1; - -// @3 <- 0 param2 - #500 - io_FSMC_ADIn = 16'd3 | (1 << 11); - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 0; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 0; - io_FSMC_rdn = 1; - io_FSMC_wrn = 0; - io_FSMC_advn = 1; - - #500 - io_FSMC_ADIn = 16'd0; - io_FSMC_csn = 1; - io_FSMC_rdn = 1; - io_FSMC_wrn = 1; - io_FSMC_advn = 1; - - - #800 - io_testIO = 1; - #160 - io_testIO = 0; -end - - - - initial begin - # 10000000 - $finish; - end - - initial begin - $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 - $dumpvars(0, ShinBack_tb);//tb模块名称 - end - - -endmodule diff --git a/tb/backSys_tb.v b/tb/backSys_tb.v deleted file mode 100644 index 9f9b74a..0000000 --- a/tb/backSys_tb.v +++ /dev/null @@ -1,191 +0,0 @@ -`timescale 1 ns / 1 ps - - - -module backSys_TB ( - -); - - - reg clock; - reg reset; - - reg overCLK; - - wire [3:0] io_uDat; - wire [3:0] io_dDat; - - wire [3:0] isLast; - - -BackSys s_Mst( - .clock(clock), - .reset(reset), - .io_overCLK(overCLK), - .io_uDatIn(io_uDat[0]), - .io_uDatOut(), - .io_dDatIn(1'b0), - .io_dDatOut(io_dDat[0]), - .io_out(), - .io_in(32'b0), - .io_isOnline(), - .io_isLast(isLast[0]), - .io_DCIn(1'b0) -); - -BackSys s_Slv0( - .clock(clock), - .reset(reset), - .io_overCLK(overCLK), - .io_uDatIn(io_uDat[1]), - .io_uDatOut(io_uDat[0]), - .io_dDatIn(io_dDat[0]), - .io_dDatOut(io_dDat[1]), - .io_out(), - .io_in(32'b0), - .io_isOnline(isLast[0]), - .io_isLast(isLast[1]), - .io_DCIn(1'b0) -); - -BackSys s_Slv1( - .clock(clock), - .reset(reset), - .io_overCLK(overCLK), - .io_uDatIn(io_uDat[2]), - .io_uDatOut(io_uDat[1]), - .io_dDatIn(io_dDat[1]), - .io_dDatOut(io_dDat[2]), - .io_out(), - .io_in(32'b0), - .io_isOnline(isLast[1]), - .io_isLast(isLast[2]), - .io_DCIn(1'b0) -); - - -BackSys s_Slv2( - .clock(clock), - .reset(reset), - .io_overCLK(overCLK), - .io_uDatIn(io_uDat[3]), - .io_uDatOut(io_uDat[2]), - .io_dDatIn(io_dDat[2]), - .io_dDatOut(io_dDat[3]), - .io_out(), - .io_in(32'b0), - .io_isOnline(isLast[2]), - .io_isLast(isLast[3]), - .io_DCIn(1'b0) -); - -BackSys s_Slv3( - .clock(clock), - .reset(reset), - .io_overCLK(overCLK), - .io_uDatIn(1'b0), - .io_uDatOut(io_uDat[3]), - .io_dDatIn(io_dDat[3]), - .io_dDatOut(), - .io_out(), - .io_in(32'b0), - .io_isOnline(isLast[3]), - .io_isLast(1'b1), - .io_DCIn(1'b0) -); - - -initial begin - clock = 0; - reset = 1; - overCLK = 0; - - #200 - - reset <= 0; - - # 5000000 - $display("Time Out !!!"); - $stop; -end - - -initial begin - forever begin #40 clock <= ~clock; end -end - -initial begin - forever begin #10 overCLK <= ~overCLK; end -end - - - `define SRAM s_Mst.sram.mem.mem_ext.ram - - - - localparam DP = 2**14; - integer i; - - reg [7:0] mem [0:200000]; - initial begin - $readmemh("./tb/sw/build/mstTest.verilog", mem); - for ( i = 0; i < DP; i = i + 1 ) begin - `SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0; - `SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0; - `SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0; - `SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0; - - // $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]); - end - end - - - `define SLV0_SRAM s_Slv0.sram.mem.mem_ext.ram - - `define SLV1_SRAM s_Slv1.sram.mem.mem_ext.ram - - `define SLV2_SRAM s_Slv2.sram.mem.mem_ext.ram - - `define SLV3_SRAM s_Slv3.sram.mem.mem_ext.ram - - - localparam DPS = 2**14; - - reg [7:0] mem1 [0:200000]; - initial begin - $readmemh("./tb/sw/build/slvTest.verilog", mem); - for ( i = 0; i < DP; i = i + 1 ) begin - `SLV0_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0; - `SLV0_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0; - `SLV0_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0; - `SLV0_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0; - - `SLV1_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0; - `SLV1_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0; - `SLV1_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0; - `SLV1_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0; - - `SLV2_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0; - `SLV2_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0; - `SLV2_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0; - `SLV2_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0; - - `SLV3_SRAM[i][7:0] = | mem[i*4+0] ? mem[i*4+0]: 8'h0; - `SLV3_SRAM[i][15:8] = | mem[i*4+1] ? mem[i*4+1]: 8'h0; - `SLV3_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0; - `SLV3_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0; - // $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]); - end - end - - - - -initial -begin - $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 - $dumpvars(0, backSys_TB);//tb模块名称 -end - -endmodule - diff --git a/tb/cdrInOut_tb.v b/tb/cdrInOut_tb.v deleted file mode 100644 index f35319a..0000000 --- a/tb/cdrInOut_tb.v +++ /dev/null @@ -1,148 +0,0 @@ -`timescale 1 ns / 1 ps - - -module CDRInOut_tb(); - - - - - reg clock = 0; - reg reset = 1; - - reg overCLK = 0; - - wire serDat; - - wire tx_axis_ready; - - reg tx_axis_valid = 0; - reg [7:0] tx_axis_bits_tdata; - reg tx_axis_bits_tlast; - reg tx_axis_bits_tuser; - - - - reg rx_axis_ready = 1; - wire rx_axis_valid; - wire [7:0] rx_axis_bits_tdata; - wire rx_axis_bits_tlast; - wire rx_axis_bits_tuser; - - - - CDRIn s_CDRIn( - .clock(clock), - .reset(reset), - - .io_axis_ready(rx_axis_ready), - .io_axis_valid(rx_axis_valid), - .io_axis_bits_tdata(rx_axis_bits_tdata), - .io_axis_bits_tlast(rx_axis_bits_tlast), - .io_axis_bits_tuser(rx_axis_bits_tuser), - - .io_serDat(serDat), - .io_overCLK(overCLK) - ); - - - - - - - - - CDROut s_CDROut( - .clock(clock), - .reset(reset), - - .io_axis_ready(tx_axis_ready), - .io_axis_valid(tx_axis_valid), - .io_axis_bits_tdata(tx_axis_bits_tdata), - .io_axis_bits_tlast(tx_axis_bits_tlast), - .io_axis_bits_tuser(tx_axis_bits_tuser), - .io_serDat(serDat) - ); - - - - - -initial begin - forever #80 clock = ~clock; -end - -initial begin - #10 - forever #20 overCLK = ~overCLK; -end - -initial begin - # 100 reset = 1; - # 100 reset = 0; -end - - -// reg [7:0] cnt = 0; - -reg [31:0] rtc_cnt=0; - always @(posedge clock) begin - if( rtc_cnt > 200 ) begin - rtc_cnt <= #2 0; - end else begin - rtc_cnt <= #2 rtc_cnt + 1; - end - end - - - reg [7:0] cnt; - - - always @(posedge clock) begin - if( rtc_cnt == 0 ) begin - cnt <= #2 0; - end else begin - if( cnt == 8'd0 ) begin - tx_axis_valid <= #2 1'b1; - tx_axis_bits_tdata <= #2 0; - tx_axis_bits_tlast <= #2 1'b0; - tx_axis_bits_tuser <= #2 1'b0; - cnt <= #2 cnt + 8'd1; - end else begin - if( tx_axis_valid & tx_axis_ready ) begin - if ( tx_axis_bits_tlast ) begin - tx_axis_valid <= #2 1'b0; - tx_axis_bits_tlast <= #2 1'b0; - end else begin - tx_axis_bits_tdata <= #2 cnt; - tx_axis_bits_tuser <= #2 1'b0; - - if( cnt == 8'd1 ) begin - tx_axis_bits_tdata <= #2 8'h1; - end - - if( cnt == 8'd4 ) begin - tx_axis_bits_tlast <= #2 8'h1; - end else begin - cnt <= #2 cnt + 8'd1; - end - end - end - end - end - end - - - - initial begin - # 100000 - $finish; - - end - - initial begin - $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 - $dumpvars(0, CDRInOut_tb);//tb模块名称 - end - - -endmodule diff --git a/tb/cdrOut_tb.v b/tb/cdrOut_tb.v deleted file mode 100644 index 3047e94..0000000 --- a/tb/cdrOut_tb.v +++ /dev/null @@ -1,113 +0,0 @@ -`timescale 1 ns / 1 ps - - -module CDROut_tb(); - - - - - reg clock = 0; - reg reset = 1; - - wire serDat; - - wire axis_ready; - - reg axis_valid = 0; - reg [7:0] axis_bits_tdata; - reg axis_bits_tlast; - reg axis_bits_tuser; - - - - CDROut s_CDROut( - .clock(clock), - .reset(reset), - - .io_axis_ready(axis_ready), - .io_axis_valid(axis_valid), - .io_axis_bits_tdata(axis_bits_tdata), - .io_axis_bits_tlast(axis_bits_tlast), - .io_axis_bits_tuser(axis_bits_tuser), - .io_serDat(serDat) - ); - - - - - -initial begin - forever #20 clock = ~clock; -end - -initial begin - # 100 reset = 1; - # 100 reset = 0; -end - - -reg [7:0] cnt = 0; - - - // always @(posedge clock) begin - // if( cnt == 8'd0 ) begin - // #2 axis_valid <= 1'b1; - // #2 axis_bits_tdata <= cnt; - // #2 axis_bits_tlast <= 1'b0; - // #2 axis_bits_tuser <= 1'b0; - // #2 cnt <= cnt + 8'd1; - // end else begin - // if( axis_valid & axis_ready ) begin - // axis_valid <= 1'b0; - // end else if( ~axis_valid ) begin - // #2 axis_valid <= 1'b1; - // if ( cnt == 8'd255 ) begin - // #2 axis_bits_tlast <= 1'b1; - // end else begin - // #2 axis_bits_tlast <= 1'b0; - // #2 cnt <= cnt + 8'd1; - // end - // end - // end - // end - - always @(posedge clock) begin - if( cnt == 8'd0 ) begin - #2 axis_valid <= 1'b1; - #2 axis_bits_tdata <= cnt; - #2 axis_bits_tlast <= 1'b0; - #2 axis_bits_tuser <= 1'b0; - #2 cnt <= cnt + 8'd1; - end else begin - if( axis_valid & axis_ready ) begin - if ( axis_bits_tlast ) begin - #2 axis_valid <= 1'b0; - #2 axis_bits_tlast <= 1'b0; - end else begin - #2 axis_bits_tdata <= cnt; - #2 axis_bits_tuser <= 1'b0; - if( cnt == 8'd31 ) begin - #2 axis_bits_tlast <= 1'b1; - end else begin - #2 cnt <= cnt + 8'd1; - end - end - end - end - end - - - - initial begin - # 100000 - $finish; - - end - - initial begin - $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 - $dumpvars(0, CDROut_tb);//tb模块名称 - end - - -endmodule diff --git a/tb/sim_backChain.cpp b/tb/sim_backChain.cpp deleted file mode 100644 index 9a473a4..0000000 --- a/tb/sim_backChain.cpp +++ /dev/null @@ -1,244 +0,0 @@ -/* - Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#include -#include "VBackPlaneChainTest.h" -#include -#include -#include - -#include - - - -#if VM_TRACE -#include "verilated_fst_c.h" -#endif - - -char* img; -VBackPlaneChainTest *top; -#if VM_TRACE -VerilatedFstC* tfp; -#endif -vluint64_t main_time = 0; - -double sc_time_stamp () { - return main_time; -} - - - -static void sim_exit(){ -#if VM_TRACE - tfp->close(); -#endif - - top->final(); - - delete top; -} - - - - - - -int main(int argc, char **argv, char **env) { - - - top = new VBackPlaneChainTest(); - -#if VM_TRACE - tfp = new VerilatedFstC; - Verilated::traceEverOn(true); - top->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("./tb/build/wave.fst"); -#endif - - - - - - top->reset = 1; - top->clock = 0; - top->io_clk400_0 = 0; - top->io_clk400_1 = 0; - top->io_clk400_2 = 0; - top->io_clk400_3 = 0; - top->io_clk400_4 = 0; - top->io_clk400_5 = 0; - - while(!Verilated::gotFinish()) { - - Verilated::timeInc(1); - - if ( main_time != 1000 ){ - } else { - top->reset = 0; - } - - if ( main_time % 400 == 100 ) { - top->clock = 1; - } else if ( main_time % 400 == 300 ) { - top->clock = 0; - } - - - - - - if ( main_time % 100 == 10 ) { - top->io_clk400_0 = 1; - } else if ( main_time % 100 == 60 ) { - top->io_clk400_0 = 0; - } - - if ( main_time % 100 == 20 ) { - top->io_clk400_1 = 1; - } else if ( main_time % 100 == 70 ) { - top->io_clk400_1 = 0; - } - - if ( main_time % 100 == 40 ) { - top->io_clk400_2 = 1; - } else if ( main_time % 100 == 90 ) { - top->io_clk400_2 = 0; - } - - if ( main_time % 100 == 5 ) { - top->io_clk400_3 = 1; - } else if ( main_time % 100 == 55 ) { - top->io_clk400_3 = 0; - } - - if ( main_time % 100 == 0 ) { - top->io_clk400_4 = 1; - } else if ( main_time % 100 == 50 ) { - top->io_clk400_4 = 0; - } - - if ( main_time % 100 == 30 ) { - top->io_clk400_5 = 1; - } else if ( main_time % 100 == 80 ) { - top->io_clk400_5 = 0; - } - - - - if( main_time == 50000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x00 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0xa5; - top->io_spi_bits_op = 0x01; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 50100 ){ - top->io_spi_valid = 0; - } - - - if( main_time == 250000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x01 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 250100 ){ - top->io_spi_valid = 0; - } - - if( main_time == 450000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x02 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 450100 ){ - top->io_spi_valid = 0; - } - - if( main_time == 650000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x03 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 650100 ){ - top->io_spi_valid = 0; - } - - if( main_time == 850000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x04 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 850100 ){ - top->io_spi_valid = 0; - } - - if( main_time == 1050000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x05 << 1 | 0x01; - top->io_spi_bits_register = 0x1; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 1050100 ){ - top->io_spi_valid = 0; - } - - - - top->eval(); -#if VM_TRACE - tfp->dump(Verilated::time()); - -#endif - - - main_time ++; - - if( main_time > 3050000 ){ - break; - } - } - - sim_exit(); - return -1; - - -} - - - - - - - - diff --git a/tb/sim_backMst.cpp b/tb/sim_backMst.cpp deleted file mode 100644 index 1a73f72..0000000 --- a/tb/sim_backMst.cpp +++ /dev/null @@ -1,175 +0,0 @@ -/* - Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#include -#include "VBackPlaneMstTest.h" -#include -#include -#include - -#include - - - -#if VM_TRACE -#include "verilated_fst_c.h" -#endif - - -char* img; -VBackPlaneMstTest *top; -#if VM_TRACE -VerilatedFstC* tfp; -#endif -vluint64_t main_time = 0; - -double sc_time_stamp () { - return main_time; -} - - - -static void sim_exit(){ -#if VM_TRACE - tfp->close(); -#endif - - top->final(); - - delete top; -} - - - - - - -int main(int argc, char **argv, char **env) { - - - top = new VBackPlaneMstTest(); - -#if VM_TRACE - tfp = new VerilatedFstC; - Verilated::traceEverOn(true); - top->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("./tb/build/wave.fst"); -#endif - - - - - - - - - - - - - - - - - top->io_reset = 1; - // top->io_SCK = 0; - top->io_clk4 = 0; - - while(!Verilated::gotFinish()) { - - Verilated::timeInc(1); - - if ( main_time != 1000 ){ - } else { - top->io_reset = 0; - } - - // if ( main_time % 400 == 100 ) { - // top->io_SCK = 1; - // } else if ( main_time % 400 == 300 ) { - // top->io_SCK = 0; - // } - - if ( main_time % 100 == 10 ) { - top->io_clk4 = 1; - } else if ( main_time % 100 == 60 ) { - top->io_clk4 = 0; - } - - - if( main_time == 50000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x11 << 1 | 0x00; - top->io_spi_bits_register = 0x0; - top->io_spi_bits_data = 0xaa; - top->io_spi_bits_op = 0x01; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 50100 ){ - top->io_spi_valid = 0; - } - - if( main_time == 150000 ){ - top->io_req_valid = 1; - top->io_req_bits_address = 0x11 << 1 | 0x00; - top->io_req_bits_register = 0x0; - top->io_req_bits_data = 0xaa; - } else if( main_time == 150400 ){ - top->io_req_valid = 0; - } - - if( main_time == 250000 ){ - top->io_spi_valid = 1; - top->io_spi_bits_address = 0x11 << 1 | 0x01; - top->io_spi_bits_register = 0x0; - top->io_spi_bits_data = 0x55; - top->io_spi_bits_op = 0x00; - top->io_spi_bits_hash = 0x0; - - } else if( main_time == 250100 ){ - top->io_spi_valid = 0; - } - - - - top->eval(); -#if VM_TRACE - tfp->dump(Verilated::time()); - -#endif - - - main_time ++; - - if( main_time > 450000 ){ - break; - } - } - - sim_exit(); - return -1; - - -} - - - - - - - - diff --git a/tb/sim_backSlv.cpp b/tb/sim_backSlv.cpp deleted file mode 100644 index 4e28092..0000000 --- a/tb/sim_backSlv.cpp +++ /dev/null @@ -1,147 +0,0 @@ -/* - Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#include -#include "VBackBoardSlvTest.h" -#include -#include -#include - -#include - - - -#if VM_TRACE -#include "verilated_fst_c.h" -#endif - - -char* img; -VBackBoardSlvTest *top; -#if VM_TRACE -VerilatedFstC* tfp; -#endif -vluint64_t main_time = 0; - -double sc_time_stamp () { - return main_time; -} - - - -static void sim_exit(){ -#if VM_TRACE - tfp->close(); -#endif - - top->final(); - - delete top; -} - - - - - - -int main(int argc, char **argv, char **env) { - - - top = new VBackBoardSlvTest(); - -#if VM_TRACE - tfp = new VerilatedFstC; - Verilated::traceEverOn(true); - top->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("./tb/build/wave.fst"); -#endif - - - - - top->reset = 1; - top->clock = 0; - top->io_clk4 = 0; - - while(!Verilated::gotFinish()) { - - Verilated::timeInc(1); - - if ( main_time != 1000 ){ - } else { - top->reset = 0; - } - - if ( main_time % 400 == 100 ) { - top->clock = 1; - } else if ( main_time % 400 == 300 ) { - top->clock = 0; - } - - if ( main_time % 100 == 10 ) { - top->io_clk4 = 1; - } else if ( main_time % 100 == 60 ) { - top->io_clk4 = 0; - } - - - if( main_time == 50000 ){ - top->io_req_valid = 1; - top->io_req_bits_address = 0x11 << 1 | 0x00; - top->io_req_bits_register = 0x0; - top->io_req_bits_data = 0xaa; - } else if( main_time == 50400 ){ - top->io_req_valid = 0; - } - - if( main_time == 150000 ){ - top->io_rsp_valid = 1; - top->io_rsp_bits_address = 0x11 << 1 | 0x00; - top->io_rsp_bits_register = 0x0; - top->io_rsp_bits_data = 0xaa; - } else if( main_time == 150400 ){ - top->io_rsp_valid = 0; - } - - - top->eval(); -#if VM_TRACE - tfp->dump(Verilated::time()); - -#endif - - - main_time ++; - - if( main_time > 250000 ){ - break; - } - } - - sim_exit(); - return -1; - - -} - - - - - - - - diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v deleted file mode 100644 index 7127dea..0000000 --- a/tb/verilator/SimTop.v +++ /dev/null @@ -1,946 +0,0 @@ - - - - - - - - -module SimTop ( - - // output success, - // output fail, - - input clock, //100MHz - input reset, - input clk800, - - output [7:0] gpio_o, - input [7:0] gpio_i - - -); - - - -wire [3:0] uDatSer; -wire [3:0] dDatSer; - - - - -wire [3:0] dmactive; - -ExampleRocketSystem s_rocket_mst( - .clock(clock), - .reset(reset), - .resetctrl_hartIsInReset_0(reset), - - .debug_clock(clock), - .debug_reset(reset), - .debug_systemjtag_jtag_TCK(1'b0), - .debug_systemjtag_jtag_TMS(1'b0), - .debug_systemjtag_jtag_TDI(1'b0), - .debug_systemjtag_jtag_TDO_data(), - .debug_systemjtag_jtag_TDO_driven(), - .debug_systemjtag_reset(reset), - .debug_systemjtag_mfr_id(11'b0), - .debug_systemjtag_part_number(16'b0), - .debug_systemjtag_version(4'b0), - .debug_ndreset(), - .debug_dmactive(dmactive[0]), - .debug_dmactiveAck(dmactive[0]), - - .mmio_apb_0_psel(), - .mmio_apb_0_penable(), - .mmio_apb_0_pwrite(), - .mmio_apb_0_paddr(), - .mmio_apb_0_pprot(), - .mmio_apb_0_pwdata(), - .mmio_apb_0_pstrb(), - .mmio_apb_0_pready(1'b1), - .mmio_apb_0_pslverr(1'b0), - .mmio_apb_0_prdata(32'b0), - - .mmio_ahb_0_hmastlock(), - .mmio_ahb_0_hsel(), - .mmio_ahb_0_hready(), - .mmio_ahb_0_hreadyout(1'b1), - .mmio_ahb_0_htrans(), - .mmio_ahb_0_hsize(), - .mmio_ahb_0_hburst(), - .mmio_ahb_0_hwrite(), - .mmio_ahb_0_hprot(), - .mmio_ahb_0_haddr(), - .mmio_ahb_0_hwdata(), - .mmio_ahb_0_hresp(2'b0), - .mmio_ahb_0_hrdata(32'b0), - .mmio_ahb_0_hmaster(), - .mmio_ahb_0_hsplit(16'b0), - - .gpio_0_pins_0_i_ival(gpio_i[0]), //输入 - .gpio_0_pins_0_i_po(1'b0), // - .gpio_0_pins_0_o_oval(gpio_o[0]), //输出 - .gpio_0_pins_0_o_oe(), //输出使能 - .gpio_0_pins_0_o_ie(), //输入使能 - .gpio_0_pins_0_o_pue(), //上拉使能 - .gpio_0_pins_0_o_ds(), //驱动强度 - .gpio_0_pins_0_o_ps(), //驱动速率？ - .gpio_0_pins_0_o_ds1(), //驱动强度？ - .gpio_0_pins_0_o_poe(), //Nandtree enable - - .gpio_0_pins_1_i_ival(gpio_i[1]), - .gpio_0_pins_1_i_po(1'b0), - .gpio_0_pins_1_o_oval(gpio_o[1]), - .gpio_0_pins_1_o_oe(), - .gpio_0_pins_1_o_ie(), - .gpio_0_pins_1_o_pue(), - .gpio_0_pins_1_o_ds(), - .gpio_0_pins_1_o_ps(), - .gpio_0_pins_1_o_ds1(), - .gpio_0_pins_1_o_poe(), - - .gpio_0_pins_2_i_ival(gpio_i[2]), - .gpio_0_pins_2_i_po(1'b0), - .gpio_0_pins_2_o_oval(gpio_o[2]), - .gpio_0_pins_2_o_oe(), - .gpio_0_pins_2_o_ie(), - .gpio_0_pins_2_o_pue(), - .gpio_0_pins_2_o_ds(), - .gpio_0_pins_2_o_ps(), - .gpio_0_pins_2_o_ds1(), - .gpio_0_pins_2_o_poe(), - - .gpio_0_pins_3_i_ival(gpio_i[3]), - .gpio_0_pins_3_i_po(1'b0), - .gpio_0_pins_3_o_oval(gpio_o[3]), - .gpio_0_pins_3_o_oe(), - .gpio_0_pins_3_o_ie(), - .gpio_0_pins_3_o_pue(), - .gpio_0_pins_3_o_ds(), - .gpio_0_pins_3_o_ps(), - .gpio_0_pins_3_o_ds1(), - .gpio_0_pins_3_o_poe(), - - .gpio_0_pins_4_i_ival(gpio_i[4]), - .gpio_0_pins_4_i_po(1'b0), - .gpio_0_pins_4_o_oval(gpio_o[4]), - .gpio_0_pins_4_o_oe(), - .gpio_0_pins_4_o_ie(), - .gpio_0_pins_4_o_pue(), - .gpio_0_pins_4_o_ds(), - .gpio_0_pins_4_o_ps(), - .gpio_0_pins_4_o_ds1(), - .gpio_0_pins_4_o_poe(), - - .gpio_0_pins_5_i_ival(gpio_i[5]), - .gpio_0_pins_5_i_po(1'b0), - .gpio_0_pins_5_o_oval(gpio_o[5]), - .gpio_0_pins_5_o_oe(), - .gpio_0_pins_5_o_ie(), - .gpio_0_pins_5_o_pue(), - .gpio_0_pins_5_o_ds(), - .gpio_0_pins_5_o_ps(), - .gpio_0_pins_5_o_ds1(), - .gpio_0_pins_5_o_poe(), - - .gpio_0_pins_6_i_ival(gpio_i[6]), - .gpio_0_pins_6_i_po(1'b0), - .gpio_0_pins_6_o_oval(gpio_o[6]), - .gpio_0_pins_6_o_oe(), - .gpio_0_pins_6_o_ie(), - .gpio_0_pins_6_o_pue(), - .gpio_0_pins_6_o_ds(), - .gpio_0_pins_6_o_ps(), - .gpio_0_pins_6_o_ds1(), - .gpio_0_pins_6_o_poe(), - - .gpio_0_pins_7_i_ival(gpio_i[7]), - .gpio_0_pins_7_i_po(1'b0), - .gpio_0_pins_7_o_oval(gpio_o[7]), - .gpio_0_pins_7_o_oe(), - .gpio_0_pins_7_o_ie(), - .gpio_0_pins_7_o_pue(), - .gpio_0_pins_7_o_ds(), - .gpio_0_pins_7_o_ps(), - .gpio_0_pins_7_o_ds1(), - .gpio_0_pins_7_o_poe(), - - .uart_0_txd(), - .uart_0_rxd(1'b0), - - // .pwm_0_gpio_0(), - // .pwm_0_gpio_1(), - // .pwm_0_gpio_2(), - // .pwm_0_gpio_3(), - - .spi_0_sck(), - .spi_0_dq_0_i(1'b0), - .spi_0_dq_0_o(), - .spi_0_dq_0_ie(), - .spi_0_dq_0_oe(), - .spi_0_dq_1_i(1'b0), - .spi_0_dq_1_o(), - .spi_0_dq_1_ie(), - .spi_0_dq_1_oe(), - .spi_0_dq_2_i(1'b0), - .spi_0_dq_2_o(), - .spi_0_dq_2_ie(), - .spi_0_dq_2_oe(), - .spi_0_dq_3_i(1'b0), - .spi_0_dq_3_o(), - .spi_0_dq_3_ie(), - .spi_0_dq_3_oe(), - .spi_0_cs_0(), - .spi_0_cs_1(), - .spi_0_cs_2(), - .spi_0_cs_3(), - - .i2c_0_scl_in(1'b0), - .i2c_0_scl_out(), - .i2c_0_scl_oe(), - .i2c_0_sda_in(1'b0), - .i2c_0_sda_out(), - .i2c_0_sda_oe(), - - .interrupts(2'b0), - - .cdrInIO_overCLK(clk800), - .cdrInIO_dDatIn(1'b0), - .cdrInIO_uDatIn(uDatSer[0]), - .cdrInIO_isLast(1'b0), - .cdrOutIO_dDatOut(dDatSer[0]), - .cdrOutIO_uDatOut(), - .cdrOutIO_isOnline(), - - .fsmcio_ADIn(16'b0), - .fsmcio_ADOut(), - .fsmcio_ADOEn(), - .fsmcio_csn(1'b1), - .fsmcio_rdn(1'b1), - .fsmcio_wrn(1'b1), - .fsmcio_advn(1'b1) -); - - -ExampleRocketSystem s_rocket_slv0( - .clock(clock), - .reset(reset), - .resetctrl_hartIsInReset_0(reset), - - .debug_clock(clock), - .debug_reset(reset), - .debug_systemjtag_jtag_TCK(1'b0), - .debug_systemjtag_jtag_TMS(1'b0), - .debug_systemjtag_jtag_TDI(1'b0), - .debug_systemjtag_jtag_TDO_data(), - .debug_systemjtag_jtag_TDO_driven(), - .debug_systemjtag_reset(reset), - .debug_systemjtag_mfr_id(11'b0), - .debug_systemjtag_part_number(16'b0), - .debug_systemjtag_version(4'b0), - .debug_ndreset(), - .debug_dmactive(dmactive[1]), - .debug_dmactiveAck(dmactive[1]), - - .mmio_apb_0_psel(), - .mmio_apb_0_penable(), - .mmio_apb_0_pwrite(), - .mmio_apb_0_paddr(), - .mmio_apb_0_pprot(), - .mmio_apb_0_pwdata(), - .mmio_apb_0_pstrb(), - .mmio_apb_0_pready(1'b1), - .mmio_apb_0_pslverr(1'b0), - .mmio_apb_0_prdata(32'b0), - - .mmio_ahb_0_hmastlock(), - .mmio_ahb_0_hsel(), - .mmio_ahb_0_hready(), - .mmio_ahb_0_hreadyout(1'b1), - .mmio_ahb_0_htrans(), - .mmio_ahb_0_hsize(), - .mmio_ahb_0_hburst(), - .mmio_ahb_0_hwrite(), - .mmio_ahb_0_hprot(), - .mmio_ahb_0_haddr(), - .mmio_ahb_0_hwdata(), - .mmio_ahb_0_hresp(2'b0), - .mmio_ahb_0_hrdata(32'b0), - .mmio_ahb_0_hmaster(), - .mmio_ahb_0_hsplit(16'b0), - - - .gpio_0_pins_0_i_ival(gpio_i[0]), //输入 - .gpio_0_pins_0_i_po(1'b0), // - .gpio_0_pins_0_o_oval(gpio_o[0]), //输出 - .gpio_0_pins_0_o_oe(), //输出使能 - .gpio_0_pins_0_o_ie(), //输入使能 - .gpio_0_pins_0_o_pue(), //上拉使能 - .gpio_0_pins_0_o_ds(), //驱动强度 - .gpio_0_pins_0_o_ps(), //驱动速率？ - .gpio_0_pins_0_o_ds1(), //驱动强度？ - .gpio_0_pins_0_o_poe(), //Nandtree enable - - .gpio_0_pins_1_i_ival(gpio_i[1]), - .gpio_0_pins_1_i_po(1'b0), - .gpio_0_pins_1_o_oval(gpio_o[1]), - .gpio_0_pins_1_o_oe(), - .gpio_0_pins_1_o_ie(), - .gpio_0_pins_1_o_pue(), - .gpio_0_pins_1_o_ds(), - .gpio_0_pins_1_o_ps(), - .gpio_0_pins_1_o_ds1(), - .gpio_0_pins_1_o_poe(), - - .gpio_0_pins_2_i_ival(gpio_i[2]), - .gpio_0_pins_2_i_po(1'b0), - .gpio_0_pins_2_o_oval(gpio_o[2]), - .gpio_0_pins_2_o_oe(), - .gpio_0_pins_2_o_ie(), - .gpio_0_pins_2_o_pue(), - .gpio_0_pins_2_o_ds(), - .gpio_0_pins_2_o_ps(), - .gpio_0_pins_2_o_ds1(), - .gpio_0_pins_2_o_poe(), - - .gpio_0_pins_3_i_ival(gpio_i[3]), - .gpio_0_pins_3_i_po(1'b0), - .gpio_0_pins_3_o_oval(gpio_o[3]), - .gpio_0_pins_3_o_oe(), - .gpio_0_pins_3_o_ie(), - .gpio_0_pins_3_o_pue(), - .gpio_0_pins_3_o_ds(), - .gpio_0_pins_3_o_ps(), - .gpio_0_pins_3_o_ds1(), - .gpio_0_pins_3_o_poe(), - - .gpio_0_pins_4_i_ival(gpio_i[4]), - .gpio_0_pins_4_i_po(1'b0), - .gpio_0_pins_4_o_oval(gpio_o[4]), - .gpio_0_pins_4_o_oe(), - .gpio_0_pins_4_o_ie(), - .gpio_0_pins_4_o_pue(), - .gpio_0_pins_4_o_ds(), - .gpio_0_pins_4_o_ps(), - .gpio_0_pins_4_o_ds1(), - .gpio_0_pins_4_o_poe(), - - .gpio_0_pins_5_i_ival(gpio_i[5]), - .gpio_0_pins_5_i_po(1'b0), - .gpio_0_pins_5_o_oval(gpio_o[5]), - .gpio_0_pins_5_o_oe(), - .gpio_0_pins_5_o_ie(), - .gpio_0_pins_5_o_pue(), - .gpio_0_pins_5_o_ds(), - .gpio_0_pins_5_o_ps(), - .gpio_0_pins_5_o_ds1(), - .gpio_0_pins_5_o_poe(), - - .gpio_0_pins_6_i_ival(gpio_i[6]), - .gpio_0_pins_6_i_po(1'b0), - .gpio_0_pins_6_o_oval(gpio_o[6]), - .gpio_0_pins_6_o_oe(), - .gpio_0_pins_6_o_ie(), - .gpio_0_pins_6_o_pue(), - .gpio_0_pins_6_o_ds(), - .gpio_0_pins_6_o_ps(), - .gpio_0_pins_6_o_ds1(), - .gpio_0_pins_6_o_poe(), - - .gpio_0_pins_7_i_ival(gpio_i[7]), - .gpio_0_pins_7_i_po(1'b0), - .gpio_0_pins_7_o_oval(gpio_o[7]), - .gpio_0_pins_7_o_oe(), - .gpio_0_pins_7_o_ie(), - .gpio_0_pins_7_o_pue(), - .gpio_0_pins_7_o_ds(), - .gpio_0_pins_7_o_ps(), - .gpio_0_pins_7_o_ds1(), - .gpio_0_pins_7_o_poe(), - - .uart_0_txd(), - .uart_0_rxd(1'b0), - - // .pwm_0_gpio_0(), - // .pwm_0_gpio_1(), - // .pwm_0_gpio_2(), - // .pwm_0_gpio_3(), - - .spi_0_sck(), - .spi_0_dq_0_i(1'b0), - .spi_0_dq_0_o(), - .spi_0_dq_0_ie(), - .spi_0_dq_0_oe(), - .spi_0_dq_1_i(1'b0), - .spi_0_dq_1_o(), - .spi_0_dq_1_ie(), - .spi_0_dq_1_oe(), - .spi_0_dq_2_i(1'b0), - .spi_0_dq_2_o(), - .spi_0_dq_2_ie(), - .spi_0_dq_2_oe(), - .spi_0_dq_3_i(1'b0), - .spi_0_dq_3_o(), - .spi_0_dq_3_ie(), - .spi_0_dq_3_oe(), - .spi_0_cs_0(), - .spi_0_cs_1(), - .spi_0_cs_2(), - .spi_0_cs_3(), - - .i2c_0_scl_in(1'b0), - .i2c_0_scl_out(), - .i2c_0_scl_oe(), - .i2c_0_sda_in(1'b0), - .i2c_0_sda_out(), - .i2c_0_sda_oe(), - - .interrupts(2'b0), - - .cdrInIO_overCLK(clk800), - .cdrInIO_dDatIn(dDatSer[0]), - .cdrInIO_uDatIn(uDatSer[1]), - .cdrInIO_isLast(1'b0), - .cdrOutIO_dDatOut(dDatSer[1]), - .cdrOutIO_uDatOut(uDatSer[0]), - .cdrOutIO_isOnline(), - - .fsmcio_ADIn(16'b0), - .fsmcio_ADOut(), - .fsmcio_ADOEn(), - .fsmcio_csn(1'b1), - .fsmcio_rdn(1'b1), - .fsmcio_wrn(1'b1), - .fsmcio_advn(1'b1) -); - - -ExampleRocketSystem s_rocket_slv1( - .clock(clock), - .reset(reset), - .resetctrl_hartIsInReset_0(reset), - - .debug_clock(clock), - .debug_reset(reset), - .debug_systemjtag_jtag_TCK(1'b0), - .debug_systemjtag_jtag_TMS(1'b0), - .debug_systemjtag_jtag_TDI(1'b0), - .debug_systemjtag_jtag_TDO_data(), - .debug_systemjtag_jtag_TDO_driven(), - .debug_systemjtag_reset(reset), - .debug_systemjtag_mfr_id(11'b0), - .debug_systemjtag_part_number(16'b0), - .debug_systemjtag_version(4'b0), - .debug_ndreset(), - .debug_dmactive(dmactive[2]), - .debug_dmactiveAck(dmactive[2]), - - .mmio_apb_0_psel(), - .mmio_apb_0_penable(), - .mmio_apb_0_pwrite(), - .mmio_apb_0_paddr(), - .mmio_apb_0_pprot(), - .mmio_apb_0_pwdata(), - .mmio_apb_0_pstrb(), - .mmio_apb_0_pready(1'b1), - .mmio_apb_0_pslverr(1'b0), - .mmio_apb_0_prdata(32'b0), - - .mmio_ahb_0_hmastlock(), - .mmio_ahb_0_hsel(), - .mmio_ahb_0_hready(), - .mmio_ahb_0_hreadyout(1'b1), - .mmio_ahb_0_htrans(), - .mmio_ahb_0_hsize(), - .mmio_ahb_0_hburst(), - .mmio_ahb_0_hwrite(), - .mmio_ahb_0_hprot(), - .mmio_ahb_0_haddr(), - .mmio_ahb_0_hwdata(), - .mmio_ahb_0_hresp(2'b0), - .mmio_ahb_0_hrdata(32'b0), - .mmio_ahb_0_hmaster(), - .mmio_ahb_0_hsplit(16'b0), - - - .gpio_0_pins_0_i_ival(gpio_i[0]), //输入 - .gpio_0_pins_0_i_po(1'b0), // - .gpio_0_pins_0_o_oval(gpio_o[0]), //输出 - .gpio_0_pins_0_o_oe(), //输出使能 - .gpio_0_pins_0_o_ie(), //输入使能 - .gpio_0_pins_0_o_pue(), //上拉使能 - .gpio_0_pins_0_o_ds(), //驱动强度 - .gpio_0_pins_0_o_ps(), //驱动速率？ - .gpio_0_pins_0_o_ds1(), //驱动强度？ - .gpio_0_pins_0_o_poe(), //Nandtree enable - - .gpio_0_pins_1_i_ival(gpio_i[1]), - .gpio_0_pins_1_i_po(1'b0), - .gpio_0_pins_1_o_oval(gpio_o[1]), - .gpio_0_pins_1_o_oe(), - .gpio_0_pins_1_o_ie(), - .gpio_0_pins_1_o_pue(), - .gpio_0_pins_1_o_ds(), - .gpio_0_pins_1_o_ps(), - .gpio_0_pins_1_o_ds1(), - .gpio_0_pins_1_o_poe(), - - .gpio_0_pins_2_i_ival(gpio_i[2]), - .gpio_0_pins_2_i_po(1'b0), - .gpio_0_pins_2_o_oval(gpio_o[2]), - .gpio_0_pins_2_o_oe(), - .gpio_0_pins_2_o_ie(), - .gpio_0_pins_2_o_pue(), - .gpio_0_pins_2_o_ds(), - .gpio_0_pins_2_o_ps(), - .gpio_0_pins_2_o_ds1(), - .gpio_0_pins_2_o_poe(), - - .gpio_0_pins_3_i_ival(gpio_i[3]), - .gpio_0_pins_3_i_po(1'b0), - .gpio_0_pins_3_o_oval(gpio_o[3]), - .gpio_0_pins_3_o_oe(), - .gpio_0_pins_3_o_ie(), - .gpio_0_pins_3_o_pue(), - .gpio_0_pins_3_o_ds(), - .gpio_0_pins_3_o_ps(), - .gpio_0_pins_3_o_ds1(), - .gpio_0_pins_3_o_poe(), - - .gpio_0_pins_4_i_ival(gpio_i[4]), - .gpio_0_pins_4_i_po(1'b0), - .gpio_0_pins_4_o_oval(gpio_o[4]), - .gpio_0_pins_4_o_oe(), - .gpio_0_pins_4_o_ie(), - .gpio_0_pins_4_o_pue(), - .gpio_0_pins_4_o_ds(), - .gpio_0_pins_4_o_ps(), - .gpio_0_pins_4_o_ds1(), - .gpio_0_pins_4_o_poe(), - - .gpio_0_pins_5_i_ival(gpio_i[5]), - .gpio_0_pins_5_i_po(1'b0), - .gpio_0_pins_5_o_oval(gpio_o[5]), - .gpio_0_pins_5_o_oe(), - .gpio_0_pins_5_o_ie(), - .gpio_0_pins_5_o_pue(), - .gpio_0_pins_5_o_ds(), - .gpio_0_pins_5_o_ps(), - .gpio_0_pins_5_o_ds1(), - .gpio_0_pins_5_o_poe(), - - .gpio_0_pins_6_i_ival(gpio_i[6]), - .gpio_0_pins_6_i_po(1'b0), - .gpio_0_pins_6_o_oval(gpio_o[6]), - .gpio_0_pins_6_o_oe(), - .gpio_0_pins_6_o_ie(), - .gpio_0_pins_6_o_pue(), - .gpio_0_pins_6_o_ds(), - .gpio_0_pins_6_o_ps(), - .gpio_0_pins_6_o_ds1(), - .gpio_0_pins_6_o_poe(), - - .gpio_0_pins_7_i_ival(gpio_i[7]), - .gpio_0_pins_7_i_po(1'b0), - .gpio_0_pins_7_o_oval(gpio_o[7]), - .gpio_0_pins_7_o_oe(), - .gpio_0_pins_7_o_ie(), - .gpio_0_pins_7_o_pue(), - .gpio_0_pins_7_o_ds(), - .gpio_0_pins_7_o_ps(), - .gpio_0_pins_7_o_ds1(), - .gpio_0_pins_7_o_poe(), - - .uart_0_txd(), - .uart_0_rxd(1'b0), - - // .pwm_0_gpio_0(), - // .pwm_0_gpio_1(), - // .pwm_0_gpio_2(), - // .pwm_0_gpio_3(), - - .spi_0_sck(), - .spi_0_dq_0_i(1'b0), - .spi_0_dq_0_o(), - .spi_0_dq_0_ie(), - .spi_0_dq_0_oe(), - .spi_0_dq_1_i(1'b0), - .spi_0_dq_1_o(), - .spi_0_dq_1_ie(), - .spi_0_dq_1_oe(), - .spi_0_dq_2_i(1'b0), - .spi_0_dq_2_o(), - .spi_0_dq_2_ie(), - .spi_0_dq_2_oe(), - .spi_0_dq_3_i(1'b0), - .spi_0_dq_3_o(), - .spi_0_dq_3_ie(), - .spi_0_dq_3_oe(), - .spi_0_cs_0(), - .spi_0_cs_1(), - .spi_0_cs_2(), - .spi_0_cs_3(), - - .i2c_0_scl_in(1'b0), - .i2c_0_scl_out(), - .i2c_0_scl_oe(), - .i2c_0_sda_in(1'b0), - .i2c_0_sda_out(), - .i2c_0_sda_oe(), - - .interrupts(2'b0), - - .cdrInIO_overCLK(clk800), - .cdrInIO_dDatIn(dDatSer[1]), - .cdrInIO_uDatIn(uDatSer[2]), - .cdrInIO_isLast(1'b0), - .cdrOutIO_dDatOut(dDatSer[2]), - .cdrOutIO_uDatOut(uDatSer[1]), - .cdrOutIO_isOnline(), - - .fsmcio_ADIn(16'b0), - .fsmcio_ADOut(), - .fsmcio_ADOEn(), - .fsmcio_csn(1'b1), - .fsmcio_rdn(1'b1), - .fsmcio_wrn(1'b1), - .fsmcio_advn(1'b1) -); - - -ExampleRocketSystem s_rocket_slv2( - .clock(clock), - .reset(reset), - .resetctrl_hartIsInReset_0(reset), - - .debug_clock(clock), - .debug_reset(reset), - .debug_systemjtag_jtag_TCK(1'b0), - .debug_systemjtag_jtag_TMS(1'b0), - .debug_systemjtag_jtag_TDI(1'b0), - .debug_systemjtag_jtag_TDO_data(), - .debug_systemjtag_jtag_TDO_driven(), - .debug_systemjtag_reset(reset), - .debug_systemjtag_mfr_id(11'b0), - .debug_systemjtag_part_number(16'b0), - .debug_systemjtag_version(4'b0), - .debug_ndreset(), - .debug_dmactive(dmactive[3]), - .debug_dmactiveAck(dmactive[3]), - - .mmio_apb_0_psel(), - .mmio_apb_0_penable(), - .mmio_apb_0_pwrite(), - .mmio_apb_0_paddr(), - .mmio_apb_0_pprot(), - .mmio_apb_0_pwdata(), - .mmio_apb_0_pstrb(), - .mmio_apb_0_pready(1'b1), - .mmio_apb_0_pslverr(1'b0), - .mmio_apb_0_prdata(32'b0), - - .mmio_ahb_0_hmastlock(), - .mmio_ahb_0_hsel(), - .mmio_ahb_0_hready(), - .mmio_ahb_0_hreadyout(1'b1), - .mmio_ahb_0_htrans(), - .mmio_ahb_0_hsize(), - .mmio_ahb_0_hburst(), - .mmio_ahb_0_hwrite(), - .mmio_ahb_0_hprot(), - .mmio_ahb_0_haddr(), - .mmio_ahb_0_hwdata(), - .mmio_ahb_0_hresp(2'b0), - .mmio_ahb_0_hrdata(32'b0), - .mmio_ahb_0_hmaster(), - .mmio_ahb_0_hsplit(16'b0), - - - .gpio_0_pins_0_i_ival(gpio_i[0]), //输入 - .gpio_0_pins_0_i_po(1'b0), // - .gpio_0_pins_0_o_oval(gpio_o[0]), //输出 - .gpio_0_pins_0_o_oe(), //输出使能 - .gpio_0_pins_0_o_ie(), //输入使能 - .gpio_0_pins_0_o_pue(), //上拉使能 - .gpio_0_pins_0_o_ds(), //驱动强度 - .gpio_0_pins_0_o_ps(), //驱动速率？ - .gpio_0_pins_0_o_ds1(), //驱动强度？ - .gpio_0_pins_0_o_poe(), //Nandtree enable - - .gpio_0_pins_1_i_ival(gpio_i[1]), - .gpio_0_pins_1_i_po(1'b0), - .gpio_0_pins_1_o_oval(gpio_o[1]), - .gpio_0_pins_1_o_oe(), - .gpio_0_pins_1_o_ie(), - .gpio_0_pins_1_o_pue(), - .gpio_0_pins_1_o_ds(), - .gpio_0_pins_1_o_ps(), - .gpio_0_pins_1_o_ds1(), - .gpio_0_pins_1_o_poe(), - - .gpio_0_pins_2_i_ival(gpio_i[2]), - .gpio_0_pins_2_i_po(1'b0), - .gpio_0_pins_2_o_oval(gpio_o[2]), - .gpio_0_pins_2_o_oe(), - .gpio_0_pins_2_o_ie(), - .gpio_0_pins_2_o_pue(), - .gpio_0_pins_2_o_ds(), - .gpio_0_pins_2_o_ps(), - .gpio_0_pins_2_o_ds1(), - .gpio_0_pins_2_o_poe(), - - .gpio_0_pins_3_i_ival(gpio_i[3]), - .gpio_0_pins_3_i_po(1'b0), - .gpio_0_pins_3_o_oval(gpio_o[3]), - .gpio_0_pins_3_o_oe(), - .gpio_0_pins_3_o_ie(), - .gpio_0_pins_3_o_pue(), - .gpio_0_pins_3_o_ds(), - .gpio_0_pins_3_o_ps(), - .gpio_0_pins_3_o_ds1(), - .gpio_0_pins_3_o_poe(), - - .gpio_0_pins_4_i_ival(gpio_i[4]), - .gpio_0_pins_4_i_po(1'b0), - .gpio_0_pins_4_o_oval(gpio_o[4]), - .gpio_0_pins_4_o_oe(), - .gpio_0_pins_4_o_ie(), - .gpio_0_pins_4_o_pue(), - .gpio_0_pins_4_o_ds(), - .gpio_0_pins_4_o_ps(), - .gpio_0_pins_4_o_ds1(), - .gpio_0_pins_4_o_poe(), - - .gpio_0_pins_5_i_ival(gpio_i[5]), - .gpio_0_pins_5_i_po(1'b0), - .gpio_0_pins_5_o_oval(gpio_o[5]), - .gpio_0_pins_5_o_oe(), - .gpio_0_pins_5_o_ie(), - .gpio_0_pins_5_o_pue(), - .gpio_0_pins_5_o_ds(), - .gpio_0_pins_5_o_ps(), - .gpio_0_pins_5_o_ds1(), - .gpio_0_pins_5_o_poe(), - - .gpio_0_pins_6_i_ival(gpio_i[6]), - .gpio_0_pins_6_i_po(1'b0), - .gpio_0_pins_6_o_oval(gpio_o[6]), - .gpio_0_pins_6_o_oe(), - .gpio_0_pins_6_o_ie(), - .gpio_0_pins_6_o_pue(), - .gpio_0_pins_6_o_ds(), - .gpio_0_pins_6_o_ps(), - .gpio_0_pins_6_o_ds1(), - .gpio_0_pins_6_o_poe(), - - .gpio_0_pins_7_i_ival(gpio_i[7]), - .gpio_0_pins_7_i_po(1'b0), - .gpio_0_pins_7_o_oval(gpio_o[7]), - .gpio_0_pins_7_o_oe(), - .gpio_0_pins_7_o_ie(), - .gpio_0_pins_7_o_pue(), - .gpio_0_pins_7_o_ds(), - .gpio_0_pins_7_o_ps(), - .gpio_0_pins_7_o_ds1(), - .gpio_0_pins_7_o_poe(), - - .uart_0_txd(), - .uart_0_rxd(1'b0), - - // .pwm_0_gpio_0(), - // .pwm_0_gpio_1(), - // .pwm_0_gpio_2(), - // .pwm_0_gpio_3(), - - .spi_0_sck(), - .spi_0_dq_0_i(1'b0), - .spi_0_dq_0_o(), - .spi_0_dq_0_ie(), - .spi_0_dq_0_oe(), - .spi_0_dq_1_i(1'b0), - .spi_0_dq_1_o(), - .spi_0_dq_1_ie(), - .spi_0_dq_1_oe(), - .spi_0_dq_2_i(1'b0), - .spi_0_dq_2_o(), - .spi_0_dq_2_ie(), - .spi_0_dq_2_oe(), - .spi_0_dq_3_i(1'b0), - .spi_0_dq_3_o(), - .spi_0_dq_3_ie(), - .spi_0_dq_3_oe(), - .spi_0_cs_0(), - .spi_0_cs_1(), - .spi_0_cs_2(), - .spi_0_cs_3(), - - .i2c_0_scl_in(1'b0), - .i2c_0_scl_out(), - .i2c_0_scl_oe(), - .i2c_0_sda_in(1'b0), - .i2c_0_sda_out(), - .i2c_0_sda_oe(), - - .interrupts(2'b0), - - .cdrInIO_overCLK(clk800), - .cdrInIO_dDatIn(dDatSer[2]), - .cdrInIO_uDatIn(), - .cdrInIO_isLast(1'b1), - .cdrOutIO_dDatOut(), - .cdrOutIO_uDatOut(uDatSer[2]), - .cdrOutIO_isOnline(), - - .fsmcio_ADIn(16'b0), - .fsmcio_ADOut(), - .fsmcio_ADOEn(), - .fsmcio_csn(1'b1), - .fsmcio_rdn(1'b1), - .fsmcio_wrn(1'b1), - .fsmcio_advn(1'b1) -); - - - - - -// wire debugger_success; - -// debuger i_debuger( -// .success(debugger_success), -// .DEBUGER_AWID (mmio_axi4_0_aw_bits_id), -// .DEBUGER_BID (mmio_axi4_0_b_bits_id), -// .DEBUGER_ARID (mmio_axi4_0_ar_bits_id), -// .DEBUGER_RID (mmio_axi4_0_r_bits_id), - -// .DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr), -// .DEBUGER_AWVALID(mmio_axi4_0_aw_valid), -// .DEBUGER_AWREADY(mmio_axi4_0_aw_ready), - -// .DEBUGER_WDATA (mmio_axi4_0_w_bits_data), -// .DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb), -// .DEBUGER_WVALID(mmio_axi4_0_w_valid), -// .DEBUGER_WREADY(mmio_axi4_0_w_ready), - -// .DEBUGER_BRESP (mmio_axi4_0_b_bits_resp), -// .DEBUGER_BVALID(mmio_axi4_0_b_valid), -// .DEBUGER_BREADY(mmio_axi4_0_b_ready), - -// .DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr), -// .DEBUGER_ARVALID(mmio_axi4_0_ar_valid), -// .DEBUGER_ARREADY(mmio_axi4_0_ar_ready), - -// .DEBUGER_RDATA (mmio_axi4_0_r_bits_data), -// .DEBUGER_RRESP (mmio_axi4_0_r_bits_resp), -// .DEBUGER_RVALID(mmio_axi4_0_r_valid), -// .DEBUGER_RREADY(mmio_axi4_0_r_ready), - -// .CLK(CLK), -// .RSTn(RSTn) - -// ); - - - - - - // reg [1023:0] firmware_file; - // initial begin - // if ($value$plusargs("%s", firmware_file)) begin - // $display("%s", firmware_file); - // $readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram); - // end - // end - - - - - - - -// assign success = debugger_success; - - - -initial begin - #1000 - s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 0; - s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 1; - s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 2; - s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 3; -end - -string testName; - -`define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram -`define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram -`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram -`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram - -reg [7:0] mem0 [0:200000]; -reg [7:0] mem1 [0:200000]; -reg [7:0] mem2 [0:200000]; -reg [7:0] mem3 [0:200000]; - -localparam DP = 8192; -integer i; - - -initial begin - -#20 - - $readmemh("./tb/sw/build/mstTest.verilog", mem0); - for ( i = 0; i < DP; i = i + 1 ) begin - if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin - `MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]}; - end - else begin - `MEM0[i] = 32'h0; - end - - // $display("MEM0[%d] = %h", i, `MEM0[i]); - end - - $readmemh("./tb/sw/build/slvTest.verilog", mem1); - for ( i = 0; i < DP; i = i + 1 ) begin - if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin - `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]}; - end - else begin - `MEM1[i] = 32'h0; - end - end - - $readmemh("./tb/sw/build/slvTest.verilog", mem2); - for ( i = 0; i < DP; i = i + 1 ) begin - if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin - `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]}; - end - else begin - `MEM2[i] = 32'h0; - end - end - - $readmemh("./tb/sw/build/slvTest.verilog", mem3); - for ( i = 0; i < DP; i = i + 1 ) begin - if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin - `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]}; - end - else begin - `MEM3[i] = 32'h0; - end - end - -end - - - -endmodule - - - - - - diff --git a/tb/verilator/plusarg_reader.v b/tb/verilator/plusarg_reader.v deleted file mode 100644 index 6d4ad44..0000000 --- a/tb/verilator/plusarg_reader.v +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE.SiFive for license details. - -//VCS coverage exclude_file - -// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment), -// but Incisive demands them. These default values should never be used. -module plusarg_reader #( - parameter FORMAT="borked=%d", - parameter WIDTH=1, - parameter [WIDTH-1:0] DEFAULT=0 -) ( - output [WIDTH-1:0] out -); - -assign out = DEFAULT; - -endmodule diff --git a/tb/verilator/sim_main.cpp b/tb/verilator/sim_main.cpp deleted file mode 100644 index 0857b9d..0000000 --- a/tb/verilator/sim_main.cpp +++ /dev/null @@ -1,183 +0,0 @@ -/* - Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#include -#include "VSimTop.h" -#include -#include -#include - -#include - - - -#if VM_TRACE -#include "verilated_fst_c.h" -#endif - - -char* img; -VSimTop *top; -#if VM_TRACE -VerilatedFstC* tfp; -#endif -vluint64_t main_time = 0; -vluint64_t main_cycle = 0; - -double sc_time_stamp () { - return main_time; -} - - -uint8_t flag_waveEnable = 0; -uint8_t flag_limitEnable = 0; -static void init_and_clock(); - - -int prase_arg(int argc, char **argv) { - int opt; - while( -1 != ( opt = getopt( argc, argv, "pjldwf:" ) ) ) { - switch(opt) { - - case 'l': - flag_limitEnable = 1; - break; - - case 'w': - flag_waveEnable = 1; - std::cout << "Waveform is Enable" << std::endl; - break; - case 'f': - img = strdup(optarg); - // std::cout << "load in image is " << img << std::endl; - break; - case '?': - std::cout << "-w to enable waveform" << std::endl; - std::cout << "-f FILENAME to testfile" << std::endl; - return -1; - break; - default: - std::cout << opt << std::endl; - assert(0); - } - } - return 0; -} - -static void sim_exit(){ -#if VM_TRACE - if ( flag_waveEnable ) { tfp->close(); } -#endif - - top->final(); - delete top; -} - - - - - -int main(int argc, char **argv, char **env) { - - - if ( -1 == prase_arg(argc, argv) ) { - std::cout << "Prase Error." << std::endl; - return -1; - } - - // char * temp[2]; - // char cmd[64] = "+"; - // strcat(cmd, img); - // strcat(cmd, ".verilog"); - // temp[0] = "Verilated"; - // temp[1] = cmd; - // char **argv_temp = temp; - // Verilated::commandArgs(2, argv_temp); - - - - top = new VSimTop(); - -#if VM_TRACE - tfp = new VerilatedFstC; - if (flag_waveEnable) { - Verilated::traceEverOn(true); - top->trace(tfp, 99); // Trace 99 levels of hierarchy - - tfp->open("./tb/build/wave.fst"); - } -#endif - - - top->reset = 1; - top->clock = 0; - top->clk800 = 0; - - while(!Verilated::gotFinish()) { - - Verilated::timeInc(1); - - init_and_clock(); - - top->eval(); - -#if VM_TRACE - if ( flag_waveEnable ) { tfp->dump(Verilated::time()); } -#endif - - if ( flag_limitEnable ) { - if ( main_cycle > 45000 ){ - std::cout << "Timeout!!!!!" << std::endl; - sim_exit(); - return -1; - } - } - - main_time ++; - } - - sim_exit(); - return -1; - -} - - -static void init_and_clock(){ - - //de-assert reset - if ( main_time != 100 ){ - } else { - top->reset = 0; - } - - //main clock - if ( main_time % 40 == 1 ) { - top->clock = 1; - } else if ( main_time % 40 == 21 ) { - top->clock = 0; - main_cycle ++; - } - - uint8_t phase = 1; - if ( main_time % 5 == (0+phase) ) { - top->clk800 = 1; - } else if ( main_time % 5 == (2+phase) ) { - top->clk800 = 0; - } - - -}