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This commit is contained in:
RuigeLee
2025-09-11 14:30:08 +08:00
parent 61d4f6fcf8
commit 26367fd63c
55 changed files with 0 additions and 13145 deletions
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1353
src/test/scala/ethPhy.scala.bk
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87
src/test/scala/gcd/BackPlaneChainTest.scala.bk
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package BACK
import chisel3._
import chisel3.util._
class BackPlaneChainTestIO extends Bundle{
val clk400 = Input( Vec(6, Bool() ))
val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
val led = Output( Vec( 5, Bool() ) )
}
class BackPlaneChainTest extends Module{
val io: BackPlaneChainTestIO = IO(new BackPlaneChainTestIO)
val mst = Module(new BackBoardMst)
val slv = for( i <- 0 until 5 ) yield { Module(new BackBoardSlv) }
mst.io.clk4 := io.clk400(5)
withClockAndReset( io.clk400(5).asClock, reset.asAsyncReset ){
io.spi.ready := true.B
val cnt = RegInit(0.U(7.W))
val spiInfo = Reg( new CDR_Master_Interface_Bundle )
mst.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
val cs = RegInit(true.B); mst.io.CS := cs
val sckCnt = RegInit(1.U(2.W)); mst.io.SCK := sckCnt.extract(1) === 1.U
when( ~cs ){
sckCnt := sckCnt + 1.U
}
when( io.spi.fire ){
cs := false.B
cnt := 0.U
spiInfo := io.spi.bits
} .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
cnt := cnt + 1.U
spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), mst.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
} .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
cs := true.B
}
}
for( i <- 0 until 5 ) {
slv(i).io.localHost := i.U
slv(i).io.clk4 := io.clk400(i)
slv(i).sw := 0.U
slv(i).qeiA := false.B
slv(i).qeiB := false.B
io.led(i) := slv(i).led.extract(0).asBool
}
slv(0).io.upStreamReqDat := mst.io.downStreamRespdat
mst.io.downStreamReqDat := slv(0).io.upStreamRespdat
slv(1).io.upStreamReqDat := slv(0).io.downStreamRespdat
slv(0).io.downStreamReqDat := slv(1).io.upStreamRespdat
slv(2).io.upStreamReqDat := slv(1).io.downStreamRespdat
slv(1).io.downStreamReqDat := slv(2).io.upStreamRespdat
slv(3).io.upStreamReqDat := slv(2).io.downStreamRespdat
slv(2).io.downStreamReqDat := slv(3).io.upStreamRespdat
slv(4).io.upStreamReqDat := slv(3).io.downStreamRespdat
slv(3).io.downStreamReqDat := slv(4).io.upStreamRespdat
slv(4).io.downStreamReqDat := slv(4).io.downStreamRespdat
}

87
src/test/scala/gcd/BackPlaneMstTest.scala.bk
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@@ -1,87 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
class BackPlaneMstTestIO extends Bundle{
// val SCK = Input(Bool())
val interrupt = Output(Bool())
val clk4 = Input( Bool() )
val reset = Input(Bool())
val downStreamRespdat = Output(Bool())
val req = Flipped(Decoupled(new CDRData))
val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
}
class BackPlaneMstTest extends RawModule{
val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO)
withClockAndReset( io.clk4.asClock, io.reset.asAsyncReset ){
val dut = Module(new BackBoardMst)
io.downStreamRespdat := dut.io.downStreamRespdat
// dut.io.CS := io.CS
// io.MISO := dut.io.MISO
// dut.io.MOSI := io.MOSI
// dut.io.SCK := io.SCK
dut.io.clk4 := io.clk4
io.interrupt := dut.io.interrupt
io.spi.ready := true.B
val cnt = RegInit(0.U(7.W))
val spiInfo = Reg( new CDR_Master_Interface_Bundle )
dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
val cs = RegInit(true.B); dut.io.CS := cs
val sckCnt = RegInit(1.U(2.W)); dut.io.SCK := sckCnt.extract(1) === 1.U
when( ~cs ){
sckCnt := sckCnt + 1.U
}
when( io.spi.fire ){
cs := false.B
cnt := 0.U
spiInfo := io.spi.bits
} .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
cnt := cnt + 1.U
spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
} .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
cs := true.B
}
io.req.ready := true.B
val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
val datCnt = RegInit( 0.U(2.W) )
datCnt := datCnt + 1.U
when( datCnt === "b11".U ) {
when( io.req.fire ){
reqInfo := io.req.bits.asUInt
reqDat := true.B
} .otherwise{
reqDat := reqInfo.extract( 6+8+32+16-1 )
reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
}
}
}
}

63
src/test/scala/gcd/BackPlaneSlvTest.scala.bk
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package BACK
import chisel3._
import chisel3.util._
class BackBoardSlvTestIO extends Bundle{
val localHost = Input(UInt(6.W))
val upStreamRespdat = Output(Bool())
val downStreamRespdat = Output(Bool())
val clk4 = Input( Bool() )
val req = Flipped(Decoupled(new CDRData))
val rsp = Flipped(Decoupled(new CDRData))
}
class BackBoardSlvTest extends Module{
val io: BackBoardSlvTestIO = IO(new BackBoardSlvTestIO)
val dut = Module( new BackBoardSlv)
dut.io.localHost := "h12".U
dut.io.clk4 := io.clk4
io.upStreamRespdat := dut.io.upStreamRespdat
io.downStreamRespdat := dut.io.downStreamRespdat
io.req.ready := true.B
io.rsp.ready := true.B
val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
val rspInfo = RegInit(0.U((new CDRData).getWidth.W))
val reqDat = RegInit(false.B); dut.io.upStreamReqDat := reqDat
val rspDat = RegInit(false.B); dut.io.downStreamReqDat := rspDat
when( io.req.fire ){
reqInfo := io.req.bits.asUInt
reqDat := true.B
} .otherwise{
reqDat := reqInfo.extract( 6+8+32+16-1 )
reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
}
when( io.rsp.fire ){
rspInfo := io.rsp.bits.asUInt
rspDat := true.B
} .otherwise{
rspDat := rspInfo.extract( 6+8+32+16-1 )
rspInfo := Cat( rspInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
}
}

82
src/test/scala/gcd/MacAXI.scala.bk
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package MAC
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.devices.tilelink._
class MacAXI(implicit p: Parameters) extends Mac{
val memAXI4SlaveNode = AXI4SlaveNode(Seq(
AXI4SlavePortParameters(
slaves = Seq(
AXI4SlaveParameters(
address = Seq(AddressSet(0x00000000L, 0x7fffffffL)),
regionType = RegionType.UNCACHED,
executable = true,
supportsRead = TransferSizes(32/8, 32/8),
supportsWrite = TransferSizes(32/8, 32/8)
)
),
beatBytes = 32 / 8
)
))
memAXI4SlaveNode :=
AXI4Deinterleaver(32/8) :=
TLToAXI4() :=
tlClientNode
val axiConfigPort =
AXI4MasterNode(
Seq(AXI4MasterPortParameters(
Seq(AXI4MasterParameters(
name = "Mac Config",
id = IdRange(0, 1),
maxFlight = Some(1),
))
))
)
val tlError = LazyModule(new TLError(
params = DevNullParams(
address = Seq(AddressSet(0x0, 0x2fffffffL)),
maxAtomic = 0,
maxTransfer = 32/8),
beatBytes = 32 / 8
))
val xbar = TLXbar()
tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort
// tlError.node := xbar
val intSinkNode = IntSinkNode(IntSinkPortSimple())
intSinkNode := int_node
val axiCfg = InModuleBody {
axiConfigPort.makeIOs()
}
val axiMem = InModuleBody {
memAXI4SlaveNode.makeIOs()
}
val int = InModuleBody {
intSinkNode.makeIOs()
}
}

41
src/test/scala/gcd/Mac_test_top.scala
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// package MAC
// import chisel3._
// import chisel3.util._
// import org.chipsalliance.cde.config._
// import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.tilelink._
// import freechips.rocketchip.interrupts._
// class MacTest(implicit p: Parameters) extends Mac{
// val tlClientIONode =
// TLClientNode(Seq(TLMasterPortParameters.v1(
// Seq(TLMasterParameters.v1(
// name = "tlSlvIO",
// sourceId = IdRange(0, 1),
// ))
// )))
// ethReg.configNode := tlClientIONode
// val intSinkNode = IntSinkNode(IntSinkPortSimple())
// intSinkNode := ethReg.int_node
// val tlSlv = InModuleBody {
// tlClientIONode.makeIOs()
// }
// val int = InModuleBody {
// intSinkNode.makeIOs()
// }
// }

113
src/test/scala/gcd/test.scala
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@@ -1,113 +0,0 @@
package test
import BACK._
import chisel3._
import chisel3.stage._
object testModule extends App {
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardMst }),
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DIn16 })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DOut16c })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DOut16p })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new SpiSlv })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new CDROut })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new CDRIn })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new ShinMst })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new ShinSlvBase })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new picorv32_tl })
// ))
// val cfg = new BackCfg
// (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new BackSys()(cfg))
// soc.module
// })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))
// val cfg = new MacCfg
// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-e", "verilog") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new MacTest()(cfg))
// soc.module
// })
// ))
// import Wrapeer._
// val cfg = new EfConfig
// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new EfablessTop()(cfg))
// soc.module
// })
// ))
}
object testShinModule extends App {
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new SlaveParser }),
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinTop }),
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new SimCDR }),
))
}