spi compile pass

2023-07-31 22:56:09 +08:00
parent 0f79860656
commit 24800cce9d
3 changed files with 143 additions and 1 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
      ChiselGeneratorAnnotation(() => {
-    new BackBoardSlvTest
+    new BackBoardMst
  })
    ))