diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
new file mode 100644
index 0000000..33aebc4
--- /dev/null
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -0,0 +1,57 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class BackBoardMstIO extends Bundle{
+  val downStreamReqDat  = Input( Bool() )
+  val downStreamRespdat = Output(Bool())
+
+  val CS   = Input(Bool())
+  val MISO = Output(Bool())
+  val MOSI = Input(Bool())
+  val SCK  = Input(Bool())
+
+  val interrupt = Output(Bool())
+
+  val clk4            = Input( Bool() )
+
+  val reset = Input(Bool())
+}
+
+
+class BackBoardMst extends RawModule{
+  val io: BackBoardMstIO = IO(new BackBoardMstIO)
+
+  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
+    val spi = Module( new SpiSlv )
+    val in  = Module( new CDR4MultiIn )
+    val out = Module( new CDROutBus )
+
+    spi.io.CS   := io.CS
+    io.MISO     := spi.io.MISO
+    spi.io.MOSI := io.MOSI
+
+    io.interrupt := spi.io.interrupt
+
+    spi.io.CDRIn  <> in.io.latDat
+    spi.io.CDROut <> out.io.pkgDat
+
+    in.io.clk4 := io.clk4
+
+    in.io.dat  := io.downStreamReqDat
+    io.downStreamRespdat := out.io.dat
+
+    spi.clock := io.SCK.asClock
+    in.clock  := io.SCK.asClock
+    out.clock := io.SCK.asClock
+
+    spi.reset := io.reset.asAsyncReset
+    in.reset  := io.reset.asAsyncReset
+    out.reset := io.reset.asAsyncReset
+  }
+}
+
+
+
diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
new file mode 100644
index 0000000..93b7ac0
--- /dev/null
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -0,0 +1,85 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class CDR_Master_Interface_Bundle extends CDRData{
+  val op       = UInt(2.W)
+}
+
+class SpiSlvIO extends Bundle{
+  val CS   = Input(Bool())
+  val MISO = Output(Bool())
+  val MOSI = Input(Bool())
+
+  val CDRIn  = Flipped(Decoupled(new CDRData))
+  val CDROut = Decoupled(new CDRData)
+
+  val interrupt = Output(Bool())
+
+
+}
+
+class SpiSlv extends Module with RequireAsyncReset{
+  val io: SpiSlvIO = IO(new SpiSlvIO)
+
+  // val spiTrans  = Reg( new CDR_Master_Interface_Bundle )
+  val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle))
+
+  io.CDRIn.ready := io.CS
+  io.interrupt   := false.B
+  io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
+
+  when( ~io.CS ){
+    
+    centReg := Cat(centReg.asUInt << 1, io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
+  } .otherwise{
+
+    when( io.CDROut.fire ){
+      centReg.op := OPBUSY
+    }
+    when( io.CDRIn.valid ){
+      when( centReg.op === OPBUSY & centReg.address === io.CDRIn.bits.address ){
+        centReg.address  := io.CDRIn.bits.address
+        centReg.register := io.CDRIn.bits.register
+        centReg.data     := io.CDRIn.bits.data
+        centReg.hash     := 0.U
+        centReg.op       := OPIDLE        
+      } .otherwise{
+        io.interrupt := true.B
+      }
+
+    }
+
+  }
+
+  val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid
+  val CDROutInfo  = Reg(new CDRData); io.CDROut.bits  := CDROutInfo
+
+  when( io.CDROut.fire ){
+    CDROutValid := false.B
+  } .elsewhen( centReg.op === OPMSTT & ~CDROutValid ){
+    CDROutValid := true.B
+
+
+
+    CDROutInfo.address  := centReg.address
+    CDROutInfo.register := centReg.register
+    CDROutInfo.data     := centReg.data
+    CDROutInfo.hash     := 0.U
+  }
+
+
+
+
+  def OPIDLE = 0.U
+  def OPMSTT = 1.U
+  // def OPSLVT = 2.U
+  def OPBUSY = 3.U
+
+
+
+}
+
+
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index 46f0062..61637df 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    new BackBoardSlvTest
+    new BackBoardMst
   })
     ))