优化信号线命名negedge_sck
This commit is contained in:
Ruige Lee (WSL)
706
.gitignore
vendored
706
.gitignore
vendored
@@ -1,353 +1,353 @@
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/project/.*/
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/project/.*/
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### Project Specific stuff
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### Project Specific stuff
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||||||
test_run_dir/*
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test_run_dir/*
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||||||
### XilinxISE template
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### XilinxISE template
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||||||
# intermediate build files
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# intermediate build files
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||||||
*.bgn
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*.bgn
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||||||
*.bit
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*.bit
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||||||
*.bld
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*.bld
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||||||
*.cmd_log
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*.cmd_log
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||||||
*.drc
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*.drc
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||||||
*.ll
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*.ll
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||||||
*.lso
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*.lso
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||||||
*.msd
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*.msd
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||||||
*.msk
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*.msk
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||||||
*.ncd
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*.ncd
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||||||
*.ngc
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*.ngc
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||||||
*.ngd
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*.ngd
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||||||
*.ngr
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*.ngr
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||||||
*.pad
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*.pad
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||||||
*.par
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*.par
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||||||
*.pcf
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*.pcf
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||||||
*.prj
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*.prj
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||||||
*.ptwx
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*.ptwx
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||||||
*.rbb
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*.rbb
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||||||
*.rbd
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*.rbd
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||||||
*.stx
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*.stx
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||||||
*.syr
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*.syr
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*.twr
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*.twr
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||||||
*.twx
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*.twx
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||||||
*.unroutes
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*.unroutes
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*.ut
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*.ut
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||||||
*.xpi
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*.xpi
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||||||
*.xst
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*.xst
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||||||
*_bitgen.xwbt
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*_bitgen.xwbt
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*_envsettings.html
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*_envsettings.html
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||||||
*_map.map
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*_map.map
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||||||
*_map.mrp
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*_map.mrp
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||||||
*_map.ngm
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*_map.ngm
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||||||
*_map.xrpt
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*_map.xrpt
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||||||
*_ngdbuild.xrpt
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*_ngdbuild.xrpt
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||||||
*_pad.csv
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*_pad.csv
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||||||
*_pad.txt
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*_pad.txt
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||||||
*_par.xrpt
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*_par.xrpt
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||||||
*_summary.html
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*_summary.html
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||||||
*_summary.xml
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*_summary.xml
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||||||
*_usage.xml
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*_usage.xml
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||||||
*_xst.xrpt
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*_xst.xrpt
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||||||
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# project-wide generated files
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# project-wide generated files
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*.gise
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*.gise
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par_usage_statistics.html
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par_usage_statistics.html
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||||||
usage_statistics_webtalk.html
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usage_statistics_webtalk.html
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||||||
webtalk.log
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webtalk.log
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||||||
webtalk_pn.xml
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webtalk_pn.xml
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||||||
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||||||
# generated folders
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# generated folders
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||||||
iseconfig/
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iseconfig/
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xlnx_auto_0_xdb/
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xlnx_auto_0_xdb/
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||||||
xst/
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xst/
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||||||
_ngo/
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_ngo/
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||||||
_xmsgs/
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_xmsgs/
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||||||
### Eclipse template
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### Eclipse template
|
||||||
*.pydevproject
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*.pydevproject
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||||||
.metadata
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.metadata
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||||||
.gradle
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.gradle
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||||||
bin/
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bin/
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||||||
tmp/
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tmp/
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||||||
*.tmp
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*.tmp
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||||||
*.bak
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*.bak
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||||||
*.swp
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*.swp
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||||||
*~.nib
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*~.nib
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||||||
local.properties
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local.properties
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||||||
.settings/
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.settings/
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||||||
.loadpath
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.loadpath
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||||||
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||||||
# Eclipse Core
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# Eclipse Core
|
||||||
.project
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.project
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||||||
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||||||
# External tool builders
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# External tool builders
|
||||||
.externalToolBuilders/
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.externalToolBuilders/
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||||||
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||||||
# Locally stored "Eclipse launch configurations"
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# Locally stored "Eclipse launch configurations"
|
||||||
*.launch
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*.launch
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||||||
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||||||
# CDT-specific
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# CDT-specific
|
||||||
.cproject
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.cproject
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||||||
# JDT-specific (Eclipse Java Development Tools)
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# JDT-specific (Eclipse Java Development Tools)
|
||||||
.classpath
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.classpath
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||||||
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||||||
# Java annotation processor (APT)
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# Java annotation processor (APT)
|
||||||
.factorypath
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.factorypath
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||||||
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|
||||||
# PDT-specific
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# PDT-specific
|
||||||
.buildpath
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.buildpath
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||||||
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||||||
# sbteclipse plugin
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# sbteclipse plugin
|
||||||
.target
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.target
|
||||||
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||||||
# TeXlipse plugin
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# TeXlipse plugin
|
||||||
.texlipse
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.texlipse
|
||||||
### C template
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### C template
|
||||||
# Object files
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# Object files
|
||||||
*.o
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*.o
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||||||
*.ko
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*.ko
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||||||
*.obj
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*.obj
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||||||
*.elf
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*.elf
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||||||
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||||||
# Precompiled Headers
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# Precompiled Headers
|
||||||
*.gch
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*.gch
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||||||
*.pch
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*.pch
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||||||
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||||||
# Libraries
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# Libraries
|
||||||
*.lib
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*.lib
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||||||
*.a
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*.a
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||||||
*.la
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*.la
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||||||
*.lo
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*.lo
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||||||
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||||||
# Shared objects (inc. Windows DLLs)
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# Shared objects (inc. Windows DLLs)
|
||||||
*.dll
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*.dll
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||||||
*.so
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*.so
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||||||
*.so.*
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*.so.*
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||||||
*.dylib
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*.dylib
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||||||
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||||||
# Executables
|
# Executables
|
||||||
*.exe
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*.exe
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||||||
*.out
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*.out
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||||||
*.app
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*.app
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||||||
*.i*86
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*.i*86
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||||||
*.x86_64
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*.x86_64
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||||||
*.hex
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*.hex
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||||||
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||||||
# Debug files
|
# Debug files
|
||||||
*.dSYM/
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*.dSYM/
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||||||
### SBT template
|
### SBT template
|
||||||
# Simple Build Tool
|
# Simple Build Tool
|
||||||
# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control
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# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control
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||||||
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||||||
target/
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target/
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||||||
lib_managed/
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lib_managed/
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||||||
src_managed/
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src_managed/
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||||||
project/boot/
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project/boot/
|
||||||
.history
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.history
|
||||||
.cache
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.cache
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||||||
### Emacs template
|
### Emacs template
|
||||||
# -*- mode: gitignore; -*-
|
# -*- mode: gitignore; -*-
|
||||||
*~
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*~
|
||||||
\#*\#
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\#*\#
|
||||||
/.emacs.desktop
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/.emacs.desktop
|
||||||
/.emacs.desktop.lock
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/.emacs.desktop.lock
|
||||||
*.elc
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*.elc
|
||||||
auto-save-list
|
auto-save-list
|
||||||
tramp
|
tramp
|
||||||
.\#*
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.\#*
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||||||
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|
||||||
# Org-mode
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# Org-mode
|
||||||
.org-id-locations
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.org-id-locations
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||||||
*_archive
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*_archive
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||||||
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||||||
# flymake-mode
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# flymake-mode
|
||||||
*_flymake.*
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*_flymake.*
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||||||
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||||||
# eshell files
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# eshell files
|
||||||
/eshell/history
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/eshell/history
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||||||
/eshell/lastdir
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/eshell/lastdir
|
||||||
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||||||
# elpa packages
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# elpa packages
|
||||||
/elpa/
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/elpa/
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||||||
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||||||
# reftex files
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# reftex files
|
||||||
*.rel
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*.rel
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||||||
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||||||
# AUCTeX auto folder
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# AUCTeX auto folder
|
||||||
/auto/
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/auto/
|
||||||
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||||||
# cask packages
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# cask packages
|
||||||
.cask/
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.cask/
|
||||||
### Vim template
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### Vim template
|
||||||
[._]*.s[a-w][a-z]
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[._]*.s[a-w][a-z]
|
||||||
[._]s[a-w][a-z]
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[._]s[a-w][a-z]
|
||||||
*.un~
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*.un~
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||||||
Session.vim
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Session.vim
|
||||||
.netrwhist
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.netrwhist
|
||||||
*~
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*~
|
||||||
### JetBrains template
|
### JetBrains template
|
||||||
# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio
|
# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio
|
||||||
|
|
||||||
*.iml
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*.iml
|
||||||
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|
||||||
## Directory-based project format:
|
## Directory-based project format:
|
||||||
.idea/
|
.idea/
|
||||||
# if you remove the above rule, at least ignore the following:
|
# if you remove the above rule, at least ignore the following:
|
||||||
|
|
||||||
# User-specific stuff:
|
# User-specific stuff:
|
||||||
# .idea/workspace.xml
|
# .idea/workspace.xml
|
||||||
# .idea/tasks.xml
|
# .idea/tasks.xml
|
||||||
# .idea/dictionaries
|
# .idea/dictionaries
|
||||||
|
|
||||||
# Sensitive or high-churn files:
|
# Sensitive or high-churn files:
|
||||||
# .idea/dataSources.ids
|
# .idea/dataSources.ids
|
||||||
# .idea/dataSources.xml
|
# .idea/dataSources.xml
|
||||||
# .idea/sqlDataSources.xml
|
# .idea/sqlDataSources.xml
|
||||||
# .idea/dynamic.xml
|
# .idea/dynamic.xml
|
||||||
# .idea/uiDesigner.xml
|
# .idea/uiDesigner.xml
|
||||||
|
|
||||||
# Gradle:
|
# Gradle:
|
||||||
# .idea/gradle.xml
|
# .idea/gradle.xml
|
||||||
# .idea/libraries
|
# .idea/libraries
|
||||||
|
|
||||||
# Mongo Explorer plugin:
|
# Mongo Explorer plugin:
|
||||||
# .idea/mongoSettings.xml
|
# .idea/mongoSettings.xml
|
||||||
|
|
||||||
## File-based project format:
|
## File-based project format:
|
||||||
*.ipr
|
*.ipr
|
||||||
*.iws
|
*.iws
|
||||||
|
|
||||||
## Plugin-specific files:
|
## Plugin-specific files:
|
||||||
|
|
||||||
# IntelliJ
|
# IntelliJ
|
||||||
/out/
|
/out/
|
||||||
|
|
||||||
# mpeltonen/sbt-idea plugin
|
# mpeltonen/sbt-idea plugin
|
||||||
.idea_modules/
|
.idea_modules/
|
||||||
|
|
||||||
# JIRA plugin
|
# JIRA plugin
|
||||||
atlassian-ide-plugin.xml
|
atlassian-ide-plugin.xml
|
||||||
|
|
||||||
# Crashlytics plugin (for Android Studio and IntelliJ)
|
# Crashlytics plugin (for Android Studio and IntelliJ)
|
||||||
com_crashlytics_export_strings.xml
|
com_crashlytics_export_strings.xml
|
||||||
crashlytics.properties
|
crashlytics.properties
|
||||||
crashlytics-build.properties
|
crashlytics-build.properties
|
||||||
### C++ template
|
### C++ template
|
||||||
# Compiled Object files
|
# Compiled Object files
|
||||||
*.slo
|
*.slo
|
||||||
*.lo
|
*.lo
|
||||||
*.o
|
*.o
|
||||||
*.obj
|
*.obj
|
||||||
|
|
||||||
# Precompiled Headers
|
# Precompiled Headers
|
||||||
*.gch
|
*.gch
|
||||||
*.pch
|
*.pch
|
||||||
|
|
||||||
# Compiled Dynamic libraries
|
# Compiled Dynamic libraries
|
||||||
*.so
|
*.so
|
||||||
*.dylib
|
*.dylib
|
||||||
*.dll
|
*.dll
|
||||||
|
|
||||||
# Fortran module files
|
# Fortran module files
|
||||||
*.mod
|
*.mod
|
||||||
|
|
||||||
# Compiled Static libraries
|
# Compiled Static libraries
|
||||||
*.lai
|
*.lai
|
||||||
*.la
|
*.la
|
||||||
*.a
|
*.a
|
||||||
*.lib
|
*.lib
|
||||||
|
|
||||||
# Executables
|
# Executables
|
||||||
*.exe
|
*.exe
|
||||||
*.out
|
*.out
|
||||||
*.app
|
*.app
|
||||||
### OSX template
|
### OSX template
|
||||||
.DS_Store
|
.DS_Store
|
||||||
.AppleDouble
|
.AppleDouble
|
||||||
.LSOverride
|
.LSOverride
|
||||||
|
|
||||||
# Icon must end with two \r
|
# Icon must end with two \r
|
||||||
Icon
|
Icon
|
||||||
|
|
||||||
# Thumbnails
|
# Thumbnails
|
||||||
._*
|
._*
|
||||||
|
|
||||||
# Files that might appear in the root of a volume
|
# Files that might appear in the root of a volume
|
||||||
.DocumentRevisions-V100
|
.DocumentRevisions-V100
|
||||||
.fseventsd
|
.fseventsd
|
||||||
.Spotlight-V100
|
.Spotlight-V100
|
||||||
.TemporaryItems
|
.TemporaryItems
|
||||||
.Trashes
|
.Trashes
|
||||||
.VolumeIcon.icns
|
.VolumeIcon.icns
|
||||||
|
|
||||||
# Directories potentially created on remote AFP share
|
# Directories potentially created on remote AFP share
|
||||||
.AppleDB
|
.AppleDB
|
||||||
.AppleDesktop
|
.AppleDesktop
|
||||||
Network Trash Folder
|
Network Trash Folder
|
||||||
Temporary Items
|
Temporary Items
|
||||||
.apdisk
|
.apdisk
|
||||||
### Xcode template
|
### Xcode template
|
||||||
# Xcode
|
# Xcode
|
||||||
#
|
#
|
||||||
# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore
|
# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore
|
||||||
|
|
||||||
## Build generated
|
## Build generated
|
||||||
build/
|
build/
|
||||||
DerivedData
|
DerivedData
|
||||||
|
|
||||||
## Various settings
|
## Various settings
|
||||||
*.pbxuser
|
*.pbxuser
|
||||||
!default.pbxuser
|
!default.pbxuser
|
||||||
*.mode1v3
|
*.mode1v3
|
||||||
!default.mode1v3
|
!default.mode1v3
|
||||||
*.mode2v3
|
*.mode2v3
|
||||||
!default.mode2v3
|
!default.mode2v3
|
||||||
*.perspectivev3
|
*.perspectivev3
|
||||||
!default.perspectivev3
|
!default.perspectivev3
|
||||||
xcuserdata
|
xcuserdata
|
||||||
|
|
||||||
## Other
|
## Other
|
||||||
*.xccheckout
|
*.xccheckout
|
||||||
*.moved-aside
|
*.moved-aside
|
||||||
*.xcuserstate
|
*.xcuserstate
|
||||||
### Scala template
|
### Scala template
|
||||||
*.class
|
*.class
|
||||||
*.log
|
*.log
|
||||||
/.bsp
|
/.bsp
|
||||||
|
|
||||||
# sbt specific
|
# sbt specific
|
||||||
.cache
|
.cache
|
||||||
.history
|
.history
|
||||||
.lib/
|
.lib/
|
||||||
dist/*
|
dist/*
|
||||||
target/
|
target/
|
||||||
lib_managed/
|
lib_managed/
|
||||||
src_managed/
|
src_managed/
|
||||||
project/boot/
|
project/boot/
|
||||||
project/plugins/project/
|
project/plugins/project/
|
||||||
|
|
||||||
# Scala-IDE specific
|
# Scala-IDE specific
|
||||||
.scala_dependencies
|
.scala_dependencies
|
||||||
.worksheet
|
.worksheet
|
||||||
### Java template
|
### Java template
|
||||||
*.class
|
*.class
|
||||||
|
|
||||||
# Mobile Tools for Java (J2ME)
|
# Mobile Tools for Java (J2ME)
|
||||||
.mtj.tmp/
|
.mtj.tmp/
|
||||||
|
|
||||||
# Package Files #
|
# Package Files #
|
||||||
*.jar
|
*.jar
|
||||||
*.war
|
*.war
|
||||||
*.ear
|
*.ear
|
||||||
|
|
||||||
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
|
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
|
||||||
hs_err_pid*
|
hs_err_pid*
|
||||||
|
|
||||||
.metals/
|
.metals/
|
||||||
generated/
|
generated/
|
||||||
project/.bloop/riscv-mac-swich-build.json
|
project/.bloop/riscv-mac-swich-build.json
|
||||||
src/main/scala/mac/MacTilelink.scala
|
src/main/scala/mac/MacTilelink.scala
|
||||||
doc/
|
doc/
|
||||||
tb/CDRIn.v
|
tb/CDRIn.v
|
||||||
tb/CDROut.v
|
tb/CDROut.v
|
||||||
tb/crc32_8.v
|
tb/crc32_8.v
|
||||||
*.pyc
|
*.pyc
|
||||||
spi_trans_data.txt
|
spi_trans_data.txt
|
||||||
|
|||||||
184
Makefile
184
Makefile
@@ -1,92 +1,92 @@
|
|||||||
TARGET=riscv64-unknown-elf
|
TARGET=riscv64-unknown-elf
|
||||||
RVCC=$(TARGET)-gcc
|
RVCC=$(TARGET)-gcc
|
||||||
RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
|
RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
|
||||||
ISR_MARCH=-march=rv32i -mabi=ilp32
|
ISR_MARCH=-march=rv32i -mabi=ilp32
|
||||||
APP_MARCH=-march=rv32i -mabi=ilp32
|
APP_MARCH=-march=rv32i -mabi=ilp32
|
||||||
ISR_CFLAGS=-O2
|
ISR_CFLAGS=-O2
|
||||||
APP_CFLAGS=-O2
|
APP_CFLAGS=-O2
|
||||||
|
|
||||||
SPI_TYPE ?= -spi 0
|
SPI_TYPE ?= -spi 0
|
||||||
TRANS_CODE ?=
|
TRANS_CODE ?=
|
||||||
DEVCLK ?= --dev1 0 90 --dev2 0 -90
|
DEVCLK ?= --dev1 0 90 --dev2 0 -90
|
||||||
CDRCLK ?= --clk 0 40
|
CDRCLK ?= --clk 0 40
|
||||||
CDR_TYPE ?= -cdr 0
|
CDR_TYPE ?= -cdr 0
|
||||||
|
|
||||||
ifeq "$(RVCCVERSION)" "12.2.0"
|
ifeq "$(RVCCVERSION)" "12.2.0"
|
||||||
ISR_MARCH=-march=rv32izicsr -mabi=ilp32
|
ISR_MARCH=-march=rv32izicsr -mabi=ilp32
|
||||||
APP_MARCH=-march=rv32izicsr -mabi=ilp32
|
APP_MARCH=-march=rv32izicsr -mabi=ilp32
|
||||||
endif
|
endif
|
||||||
|
|
||||||
.PHONY: compile tb wave
|
.PHONY: compile tb wave
|
||||||
|
|
||||||
shin:
|
shin:
|
||||||
rm -f ./generated/shin/*
|
rm -f ./generated/shin/*
|
||||||
rm -f ./generated/SimCDR/*
|
rm -f ./generated/SimCDR/*
|
||||||
sbt "test:runMain test.testShinModule"
|
sbt "test:runMain test.testShinModule"
|
||||||
|
|
||||||
testShin:
|
testShin:
|
||||||
python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
iverilog -Wall \
|
iverilog -Wall \
|
||||||
-o ./tb/build/shinTest.iverilog \
|
-o ./tb/build/shinTest.iverilog \
|
||||||
-y ./generated/shin \
|
-y ./generated/shin \
|
||||||
-I ./generated/shin \
|
-I ./generated/shin \
|
||||||
-D RANDOMIZE_REG_INIT \
|
-D RANDOMIZE_REG_INIT \
|
||||||
-D IVERILOG_COMPILE \
|
-D IVERILOG_COMPILE \
|
||||||
./tb/shinTest/ShinTopSpiTb.v
|
./tb/shinTest/ShinTopSpiTb.v
|
||||||
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
|
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
|
||||||
python3 ./tb/shinTest/check_testcase.py
|
python3 ./tb/shinTest/check_testcase.py
|
||||||
|
|
||||||
testShinClk:
|
testShinClk:
|
||||||
python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
iverilog -Wall \
|
iverilog -Wall \
|
||||||
-o ./tb/build/shinTest_clk.iverilog \
|
-o ./tb/build/shinTest_clk.iverilog \
|
||||||
-y ./generated/shin \
|
-y ./generated/shin \
|
||||||
-I ./generated/shin \
|
-I ./generated/shin \
|
||||||
-D RANDOMIZE_REG_INIT \
|
-D RANDOMIZE_REG_INIT \
|
||||||
-D IVERILOG_COMPILE \
|
-D IVERILOG_COMPILE \
|
||||||
./tb/shinTest/ShinTopSpiTb_clk.v
|
./tb/shinTest/ShinTopSpiTb_clk.v
|
||||||
vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
|
vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
|
||||||
python3 ./tb/shinTest/check_testcase.py
|
python3 ./tb/shinTest/check_testcase.py
|
||||||
|
|
||||||
testCDR:
|
testCDR:
|
||||||
python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
|
python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
|
||||||
iverilog -Wall \
|
iverilog -Wall \
|
||||||
-o ./tb/build/simCDR.iverilog \
|
-o ./tb/build/simCDR.iverilog \
|
||||||
-y ./generated/SimCDR \
|
-y ./generated/SimCDR \
|
||||||
-I ./generated/SimCDR \
|
-I ./generated/SimCDR \
|
||||||
-D RANDOMIZE_REG_INIT \
|
-D RANDOMIZE_REG_INIT \
|
||||||
-D IVERILOG_COMPILE \
|
-D IVERILOG_COMPILE \
|
||||||
./tb/shinTest/SimCDRTb.v
|
./tb/shinTest/SimCDRTb.v
|
||||||
vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
|
vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
|
||||||
|
|
||||||
|
|
||||||
testFilter:
|
testFilter:
|
||||||
./tb/shinTest/test_filter.py
|
./tb/shinTest/test_filter.py
|
||||||
|
|
||||||
vcdFilter:
|
vcdFilter:
|
||||||
gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
|
gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
fstShin:
|
fstShin:
|
||||||
gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
|
gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
fstShinClk:
|
fstShinClk:
|
||||||
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
|
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
ef:
|
ef:
|
||||||
sbt "test:runMain test.testModule"
|
sbt "test:runMain test.testModule"
|
||||||
|
|
||||||
fst:
|
fst:
|
||||||
gtkwave ./tb/build/wave.fst &
|
gtkwave ./tb/build/wave.fst &
|
||||||
|
|
||||||
debug_hlm:
|
debug_hlm:
|
||||||
gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
|
gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,19 +1,19 @@
|
|||||||
#!/bin/bash
|
#!/bin/bash
|
||||||
DEFAULT_TARGET="../ShinRelease"
|
DEFAULT_TARGET="../ShinRelease"
|
||||||
|
|
||||||
TARGET_DIR="${1:-$DEFAULT_TARGET}"
|
TARGET_DIR="${1:-$DEFAULT_TARGET}"
|
||||||
|
|
||||||
rm -rf ${TARGET_DIR}/generated/ ${TARGET_DIR}/shinTest/ ${TARGET_DIR}/resources/
|
rm -rf ${TARGET_DIR}/generated/ ${TARGET_DIR}/shinTest/ ${TARGET_DIR}/resources/
|
||||||
mkdir -p ${TARGET_DIR}
|
mkdir -p ${TARGET_DIR}
|
||||||
cp -r ./tb/shinTest ${TARGET_DIR}/
|
cp -r ./tb/shinTest ${TARGET_DIR}/
|
||||||
mkdir -p ${TARGET_DIR}/generated/
|
mkdir -p ${TARGET_DIR}/generated/
|
||||||
cp -r ./generated/shin ${TARGET_DIR}/generated/
|
cp -r ./generated/shin ${TARGET_DIR}/generated/
|
||||||
cp -r ./src/main/resources ${TARGET_DIR}/
|
cp -r ./src/main/resources ${TARGET_DIR}/
|
||||||
cp ./tb/shinTest/Makefile_vcs ${TARGET_DIR}/Makefile
|
cp ./tb/shinTest/Makefile_vcs ${TARGET_DIR}/Makefile
|
||||||
cp ./tb/shinTest/shinTest_vcs.f ${TARGET_DIR}/
|
cp ./tb/shinTest/shinTest_vcs.f ${TARGET_DIR}/
|
||||||
cp ./tb/shinTest/shinTestClk_vcs.f ${TARGET_DIR}/
|
cp ./tb/shinTest/shinTestClk_vcs.f ${TARGET_DIR}/
|
||||||
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTest_vcs.f
|
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTest_vcs.f
|
||||||
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTestClk_vcs.f
|
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTestClk_vcs.f
|
||||||
#awk '{gsub(/.\/tb\/build\/wave.vcd/, "./generated/wave.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb.v > ./shinTest/ShinTopSpiTb.v
|
#awk '{gsub(/.\/tb\/build\/wave.vcd/, "./generated/wave.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb.v > ./shinTest/ShinTopSpiTb.v
|
||||||
awk '{gsub(/tb\/shinTest\/testcase_result/, "./shinTest/testcase_result"); print }' ./tb/shinTest/check_testcase.py > ${TARGET_DIR}/shinTest/check_testcase.py
|
awk '{gsub(/tb\/shinTest\/testcase_result/, "./shinTest/testcase_result"); print }' ./tb/shinTest/check_testcase.py > ${TARGET_DIR}/shinTest/check_testcase.py
|
||||||
#awk '{gsub(/.\/tb\/build\/wave_clk.vcd/, "./generated/wave_clk.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb_clk.v > ./shinTest/ShinTopSpiTb_clk.v
|
#awk '{gsub(/.\/tb\/build\/wave_clk.vcd/, "./generated/wave_clk.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb_clk.v > ./shinTest/ShinTopSpiTb_clk.v
|
||||||
122
build.sbt
122
build.sbt
@@ -1,61 +1,61 @@
|
|||||||
// See README.md for license details.
|
// See README.md for license details.
|
||||||
|
|
||||||
ThisBuild / scalaVersion := "2.13.10"
|
ThisBuild / scalaVersion := "2.13.10"
|
||||||
ThisBuild / version := "0.1.0"
|
ThisBuild / version := "0.1.0"
|
||||||
ThisBuild / organization := "%ORGANIZATION%"
|
ThisBuild / organization := "%ORGANIZATION%"
|
||||||
|
|
||||||
val chiselVersion = "3.5.6"
|
val chiselVersion = "3.5.6"
|
||||||
|
|
||||||
lazy val commonSettings = Seq(
|
lazy val commonSettings = Seq(
|
||||||
// organization := "edu.berkeley.cs",
|
// organization := "edu.berkeley.cs",
|
||||||
// version := "1.6",
|
// version := "1.6",
|
||||||
assembly / assemblyMergeStrategy := { _ match {
|
assembly / assemblyMergeStrategy := { _ match {
|
||||||
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
|
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
|
||||||
case _ => MergeStrategy.first}},
|
case _ => MergeStrategy.first}},
|
||||||
scalacOptions ++= Seq(
|
scalacOptions ++= Seq(
|
||||||
"-deprecation",
|
"-deprecation",
|
||||||
"-unchecked",
|
"-unchecked",
|
||||||
"-Ymacro-annotations"), // fix hierarchy API
|
"-Ymacro-annotations"), // fix hierarchy API
|
||||||
)
|
)
|
||||||
|
|
||||||
lazy val chiselSettings = Seq(
|
lazy val chiselSettings = Seq(
|
||||||
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
|
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
|
||||||
"org.apache.commons" % "commons-lang3" % "3.12.0",
|
"org.apache.commons" % "commons-lang3" % "3.12.0",
|
||||||
"org.apache.commons" % "commons-text" % "1.9"),
|
"org.apache.commons" % "commons-text" % "1.9"),
|
||||||
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
|
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* It has been a struggle for us to override settings in subprojects.
|
* It has been a struggle for us to override settings in subprojects.
|
||||||
* An example would be adding a dependency to rocketchip on midas's targetutils library,
|
* An example would be adding a dependency to rocketchip on midas's targetutils library,
|
||||||
* or replacing dsptools's maven dependency on chisel with the local chisel project.
|
* or replacing dsptools's maven dependency on chisel with the local chisel project.
|
||||||
*
|
*
|
||||||
* This function works around this by specifying the project's root at src/ and overriding
|
* This function works around this by specifying the project's root at src/ and overriding
|
||||||
* scalaSource and resourceDirectory.
|
* scalaSource and resourceDirectory.
|
||||||
*/
|
*/
|
||||||
def freshProject(name: String, dir: File): Project = {
|
def freshProject(name: String, dir: File): Project = {
|
||||||
Project(id = name, base = dir / "src")
|
Project(id = name, base = dir / "src")
|
||||||
.settings(
|
.settings(
|
||||||
Compile / scalaSource := baseDirectory.value / "main" / "scala",
|
Compile / scalaSource := baseDirectory.value / "main" / "scala",
|
||||||
Compile / resourceDirectory := baseDirectory.value / "main" / "resources"
|
Compile / resourceDirectory := baseDirectory.value / "main" / "resources"
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
lazy val root = (project in file("."))
|
lazy val root = (project in file("."))
|
||||||
.settings(
|
.settings(
|
||||||
name := "%NAME%",
|
name := "%NAME%",
|
||||||
libraryDependencies ++= Seq(
|
libraryDependencies ++= Seq(
|
||||||
"edu.berkeley.cs" %% "chisel3" % chiselVersion,
|
"edu.berkeley.cs" %% "chisel3" % chiselVersion,
|
||||||
"edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test"
|
"edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test"
|
||||||
),
|
),
|
||||||
scalacOptions ++= Seq(
|
scalacOptions ++= Seq(
|
||||||
"-language:reflectiveCalls",
|
"-language:reflectiveCalls",
|
||||||
"-deprecation",
|
"-deprecation",
|
||||||
"-feature",
|
"-feature",
|
||||||
"-Xcheckinit",
|
"-Xcheckinit",
|
||||||
"-P:chiselplugin:genBundleElements",
|
"-P:chiselplugin:genBundleElements",
|
||||||
),
|
),
|
||||||
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
|
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|||||||
@@ -1,384 +1,384 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class CDRInSampleIO extends Bundle{
|
class CDRInSampleIO extends Bundle{
|
||||||
val serDat = Input(Bool())
|
val serDat = Input(Bool())
|
||||||
val syncSerDat = Output(Bool())
|
val syncSerDat = Output(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class CDRInMultiSample(clkNum: Int) extends Module with RequireAsyncReset{
|
class CDRInMultiSample(clkNum: Int) extends Module with RequireAsyncReset{
|
||||||
require( clkNum == 16 || clkNum == 4 )
|
require( clkNum == 16 || clkNum == 4 )
|
||||||
val io: CDRInSampleIO = IO(new CDRInSampleIO)
|
val io: CDRInSampleIO = IO(new CDRInSampleIO)
|
||||||
|
|
||||||
|
|
||||||
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
|
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
|
||||||
val multiCLK = IO(Input(Vec(clkNum, Bool())))
|
val multiCLK = IO(Input(Vec(clkNum, Bool())))
|
||||||
|
|
||||||
|
|
||||||
val sampleReg = Wire(Vec(clkNum, Bool()))
|
val sampleReg = Wire(Vec(clkNum, Bool()))
|
||||||
dontTouch(sampleReg)
|
dontTouch(sampleReg)
|
||||||
|
|
||||||
for( i <- 0 until clkNum ) {
|
for( i <- 0 until clkNum ) {
|
||||||
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
|
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
|
||||||
}
|
}
|
||||||
|
|
||||||
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
|
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
|
||||||
ShiftRegisters(sampleReg(i), 8, false.B, true.B)
|
ShiftRegisters(sampleReg(i), 8, false.B, true.B)
|
||||||
}
|
}
|
||||||
for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}
|
for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}
|
||||||
|
|
||||||
val sampleReg_Align = Wire(Vec(8*clkNum,Bool()))
|
val sampleReg_Align = Wire(Vec(8*clkNum,Bool()))
|
||||||
dontTouch(sampleReg_Align)
|
dontTouch(sampleReg_Align)
|
||||||
|
|
||||||
( 0 until 8 ).map{ gp =>
|
( 0 until 8 ).map{ gp =>
|
||||||
for( i <- gp*clkNum until (gp+1)*clkNum ){
|
for( i <- gp*clkNum until (gp+1)*clkNum ){
|
||||||
sampleReg_Align(i) := sampleReg_sync(i - gp*clkNum)(8-1-gp)
|
sampleReg_Align(i) := sampleReg_sync(i - gp*clkNum)(8-1-gp)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
val flitReg =
|
val flitReg =
|
||||||
for( i <- 1 until (8*clkNum)-1 ) yield {
|
for( i <- 1 until (8*clkNum)-1 ) yield {
|
||||||
(sampleReg_Align(i-1) & sampleReg_Align(i+0)) |
|
(sampleReg_Align(i-1) & sampleReg_Align(i+0)) |
|
||||||
(sampleReg_Align(i-1) & sampleReg_Align(i+1)) |
|
(sampleReg_Align(i-1) & sampleReg_Align(i+1)) |
|
||||||
(sampleReg_Align(i+0) & sampleReg_Align(i+1))
|
(sampleReg_Align(i+0) & sampleReg_Align(i+1))
|
||||||
}
|
}
|
||||||
for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
|
for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
|
||||||
|
|
||||||
val clearCnt = RegInit(0.U(4.W))
|
val clearCnt = RegInit(0.U(4.W))
|
||||||
val checkCnt = RegInit(0.U(4.W))
|
val checkCnt = RegInit(0.U(4.W))
|
||||||
val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W ))
|
val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W ))
|
||||||
val isLock = RegInit(false.B)
|
val isLock = RegInit(false.B)
|
||||||
|
|
||||||
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
|
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
|
||||||
when( clearCnt =/= 10.U ){
|
when( clearCnt =/= 10.U ){
|
||||||
clearCnt := clearCnt + 1.U
|
clearCnt := clearCnt + 1.U
|
||||||
}
|
}
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
clearCnt := 0.U
|
clearCnt := 0.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
checkCnt := 0.U
|
checkCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
checkCnt := checkCnt + 1.U
|
checkCnt := checkCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
|
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
|
||||||
val checkWindow = Wire( Vec(6, Bool()) )
|
val checkWindow = Wire( Vec(6, Bool()) )
|
||||||
dontTouch(checkWindow)
|
dontTouch(checkWindow)
|
||||||
|
|
||||||
val lastPhase = 8*clkNum -2 - clkNum/2
|
val lastPhase = 8*clkNum -2 - clkNum/2
|
||||||
|
|
||||||
checkWindow(0) :=
|
checkWindow(0) :=
|
||||||
Mux1H( (0 until lastPhase-2).map{ i =>
|
Mux1H( (0 until lastPhase-2).map{ i =>
|
||||||
(arbCali === (i+2).U) -> flitReg(i)
|
(arbCali === (i+2).U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
|
|
||||||
checkWindow(1) :=
|
checkWindow(1) :=
|
||||||
Mux1H( (1 until lastPhase-1).map{ i =>
|
Mux1H( (1 until lastPhase-1).map{ i =>
|
||||||
(arbCali === (i+1).U) -> flitReg(i)
|
(arbCali === (i+1).U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
|
|
||||||
checkWindow(2) :=
|
checkWindow(2) :=
|
||||||
Mux1H( (2 until lastPhase).map{ i =>
|
Mux1H( (2 until lastPhase).map{ i =>
|
||||||
(arbCali === i.U) -> flitReg(i)
|
(arbCali === i.U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
|
|
||||||
checkWindow(3) :=
|
checkWindow(3) :=
|
||||||
Mux1H( (3 until lastPhase+1).map{ i =>
|
Mux1H( (3 until lastPhase+1).map{ i =>
|
||||||
(arbCali === (i-1).U) -> flitReg(i)
|
(arbCali === (i-1).U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
|
|
||||||
checkWindow(4) :=
|
checkWindow(4) :=
|
||||||
Mux1H( (4 until lastPhase+2).map{ i =>
|
Mux1H( (4 until lastPhase+2).map{ i =>
|
||||||
(arbCali === (i-2).U) -> flitReg(i)
|
(arbCali === (i-2).U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
|
|
||||||
checkWindow(5) := (
|
checkWindow(5) := (
|
||||||
if( clkNum == 16 ){
|
if( clkNum == 16 ){
|
||||||
Mux1H( (5 until lastPhase+3).map{ i =>
|
Mux1H( (5 until lastPhase+3).map{ i =>
|
||||||
(arbCali === (i-3).U) -> flitReg(i)
|
(arbCali === (i-3).U) -> flitReg(i)
|
||||||
})
|
})
|
||||||
} else{
|
} else{
|
||||||
false.B
|
false.B
|
||||||
}
|
}
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
for( i <- 0 until clkNum ){
|
for( i <- 0 until clkNum ){
|
||||||
val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
|
val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
|
||||||
when( flitReg(j) ^ flitReg(j+1) ){
|
when( flitReg(j) ^ flitReg(j+1) ){
|
||||||
arbCali := j.U
|
arbCali := j.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
|
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
|
||||||
assert( arbCali >= 2.U && arbCali < lastPhase.U )
|
assert( arbCali >= 2.U && arbCali < lastPhase.U )
|
||||||
|
|
||||||
when(
|
when(
|
||||||
(if( clkNum == 16 ) { (checkWindow(0) ^ checkWindow(1)) } else {false.B}) |
|
(if( clkNum == 16 ) { (checkWindow(0) ^ checkWindow(1)) } else {false.B}) |
|
||||||
(checkWindow(1) ^ checkWindow(2))
|
(checkWindow(1) ^ checkWindow(2))
|
||||||
){
|
){
|
||||||
when( arbCali =/= 2.U ){
|
when( arbCali =/= 2.U ){
|
||||||
arbCali := arbCali - 1.U
|
arbCali := arbCali - 1.U
|
||||||
}
|
}
|
||||||
} .elsewhen(
|
} .elsewhen(
|
||||||
(checkWindow(3) ^ checkWindow(4)) |
|
(checkWindow(3) ^ checkWindow(4)) |
|
||||||
(if( clkNum == 16 ) { (checkWindow(4) ^ checkWindow(5)) } else {false.B})
|
(if( clkNum == 16 ) { (checkWindow(4) ^ checkWindow(5)) } else {false.B})
|
||||||
){
|
){
|
||||||
when( arbCali =/= (lastPhase-1).U ){
|
when( arbCali =/= (lastPhase-1).U ){
|
||||||
arbCali := arbCali + 1.U
|
arbCali := arbCali + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
for( i <- 0 until clkNum ){
|
for( i <- 0 until clkNum ){
|
||||||
val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
|
val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
|
||||||
when( flitReg(j) ^ flitReg(j+1) ){
|
when( flitReg(j) ^ flitReg(j+1) ){
|
||||||
isLock := true.B
|
isLock := true.B
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} .elsewhen( clearCnt === 10.U ){
|
} .elsewhen( clearCnt === 10.U ){
|
||||||
isLock := false.B
|
isLock := false.B
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
val asyncSerDat =
|
val asyncSerDat =
|
||||||
Mux1H(
|
Mux1H(
|
||||||
(for { i <- 2 until lastPhase } yield {
|
(for { i <- 2 until lastPhase } yield {
|
||||||
(arbCali === i.U) -> flitReg(i+(clkNum/2))
|
(arbCali === i.U) -> flitReg(i+(clkNum/2))
|
||||||
})
|
})
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
io.syncSerDat := asyncSerDat
|
io.syncSerDat := asyncSerDat
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class CDRInAxisIO extends Bundle{
|
class CDRInAxisIO extends Bundle{
|
||||||
val axis = Decoupled(new AXIS_Bundle(8))
|
val axis = Decoupled(new AXIS_Bundle(8))
|
||||||
val decode = Flipped(new Decode_Bundle)
|
val decode = Flipped(new Decode_Bundle)
|
||||||
val syncSerDat = Input(Bool())
|
val syncSerDat = Input(Bool())
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
class CDRInAxis extends Module with RequireAsyncReset{
|
class CDRInAxis extends Module with RequireAsyncReset{
|
||||||
val io: CDRInAxisIO = IO(new CDRInAxisIO)
|
val io: CDRInAxisIO = IO(new CDRInAxisIO)
|
||||||
|
|
||||||
io.decode.dataIn := 0.U
|
io.decode.dataIn := 0.U
|
||||||
def HeaderByte: Int = 4
|
def HeaderByte: Int = 4
|
||||||
|
|
||||||
val ETH_PRE = "h68".U(8.W)
|
val ETH_PRE = "h68".U(8.W)
|
||||||
val ETH_SFD = "h25".U(8.W)
|
val ETH_SFD = "h25".U(8.W)
|
||||||
|
|
||||||
val STATE_IDLE = 0.U
|
val STATE_IDLE = 0.U
|
||||||
val STATE_HEADER = 1.U
|
val STATE_HEADER = 1.U
|
||||||
val STATE_PAYLOAD = 2.U
|
val STATE_PAYLOAD = 2.U
|
||||||
|
|
||||||
val stateNext = Wire(UInt(2.W))
|
val stateNext = Wire(UInt(2.W))
|
||||||
val stateCurr = RegNext( stateNext, STATE_IDLE )
|
val stateCurr = RegNext( stateNext, STATE_IDLE )
|
||||||
|
|
||||||
val bitCnt = RegInit(0.U(4.W))
|
val bitCnt = RegInit(0.U(4.W))
|
||||||
val byteCnt = RegInit(0.U((12+1).W))
|
val byteCnt = RegInit(0.U((12+1).W))
|
||||||
|
|
||||||
val checkSFD = RegInit( 0.U(10.W) )
|
val checkSFD = RegInit( 0.U(10.W) )
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
checkSFD := 0.U
|
checkSFD := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
checkSFD := Cat( checkSFD(8,0), io.syncSerDat )
|
checkSFD := Cat( checkSFD(8,0), io.syncSerDat )
|
||||||
}
|
}
|
||||||
|
|
||||||
io.decode.dataIn := checkSFD(9,0)
|
io.decode.dataIn := checkSFD(9,0)
|
||||||
val shiftData = io.decode.dataOut
|
val shiftData = io.decode.dataOut
|
||||||
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
|
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
|
||||||
|
|
||||||
val payloadLen = RegInit(0.U(12.W))
|
val payloadLen = RegInit(0.U(12.W))
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
payloadLen := 0.U
|
payloadLen := 0.U
|
||||||
} .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
|
} .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
|
||||||
payloadLen := Cat( shiftData, 0.U(4.W) )
|
payloadLen := Cat( shiftData, 0.U(4.W) )
|
||||||
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
|
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
|
||||||
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
|
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
|
||||||
}
|
}
|
||||||
|
|
||||||
stateNext :=
|
stateNext :=
|
||||||
Mux( io.flush, STATE_IDLE,
|
Mux( io.flush, STATE_IDLE,
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
|
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
|
||||||
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
|
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
|
||||||
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
|
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
|
||||||
)) //crc
|
)) //crc
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
|
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
when( bitCnt === 9.U ){
|
when( bitCnt === 9.U ){
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
bitCnt := bitCnt + 1.U
|
bitCnt := bitCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
byteCnt := 0.U
|
byteCnt := 0.U
|
||||||
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
|
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
|
||||||
byteCnt := 0.U
|
byteCnt := 0.U
|
||||||
} .elsewhen( bitCnt === 9.U ){
|
} .elsewhen( bitCnt === 9.U ){
|
||||||
when( stateCurr === STATE_HEADER ){
|
when( stateCurr === STATE_HEADER ){
|
||||||
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
|
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
|
||||||
assert( byteCnt <= (HeaderByte-1).U )
|
assert( byteCnt <= (HeaderByte-1).U )
|
||||||
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
||||||
byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
|
byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
|
||||||
assert( byteCnt <= ( payloadLen+ (4-1).U ) )
|
assert( byteCnt <= ( payloadLen+ (4-1).U ) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val axis_valid = RegInit(false.B)
|
val axis_valid = RegInit(false.B)
|
||||||
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
|
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
|
||||||
val axis_tuser = false.B
|
val axis_tuser = false.B
|
||||||
val axis_tlast = RegInit( false.B )
|
val axis_tlast = RegInit( false.B )
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
io.axis.valid := axis_valid
|
io.axis.valid := axis_valid
|
||||||
io.axis.bits.tdata := axis_tdata
|
io.axis.bits.tdata := axis_tdata
|
||||||
io.axis.bits.tuser := axis_tuser
|
io.axis.bits.tuser := axis_tuser
|
||||||
io.axis.bits.tlast := axis_tlast
|
io.axis.bits.tlast := axis_tlast
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
axis_valid := false.B
|
axis_valid := false.B
|
||||||
} .elsewhen( io.axis.fire ){
|
} .elsewhen( io.axis.fire ){
|
||||||
axis_valid := false.B
|
axis_valid := false.B
|
||||||
} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
|
} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
|
||||||
axis_valid := true.B
|
axis_valid := true.B
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
axis_tlast := false.B
|
axis_tlast := false.B
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE)
|
axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE)
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class CDRInOriSample extends Module with RequireAsyncReset{
|
class CDRInOriSample extends Module with RequireAsyncReset{
|
||||||
val io: CDRInSampleIO = IO(new CDRInSampleIO)
|
val io: CDRInSampleIO = IO(new CDRInSampleIO)
|
||||||
val clkNum: Int = 16
|
val clkNum: Int = 16
|
||||||
require( clkNum == 16 )
|
require( clkNum == 16 )
|
||||||
|
|
||||||
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
|
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
|
||||||
val multiCLK = IO(Input(Vec(clkNum, Bool())))
|
val multiCLK = IO(Input(Vec(clkNum, Bool())))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val sampleReg = Wire(Vec(clkNum, Bool()))
|
val sampleReg = Wire(Vec(clkNum, Bool()))
|
||||||
|
|
||||||
for( i <- 0 until clkNum ) {
|
for( i <- 0 until clkNum ) {
|
||||||
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
|
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
|
||||||
}
|
}
|
||||||
|
|
||||||
val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
|
val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
for( i <- 0 until clkNum ){
|
for( i <- 0 until clkNum ){
|
||||||
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2, false.B, true.B)
|
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2, false.B, true.B)
|
||||||
}
|
}
|
||||||
|
|
||||||
for( i <- clkNum until 2*clkNum ){
|
for( i <- clkNum until 2*clkNum ){
|
||||||
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1, false.B, true.B)
|
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1, false.B, true.B)
|
||||||
}
|
}
|
||||||
|
|
||||||
val flitReg =
|
val flitReg =
|
||||||
for( i <- 1 until (2*clkNum)-1 ) yield {
|
for( i <- 1 until (2*clkNum)-1 ) yield {
|
||||||
(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
|
(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
|
||||||
(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
|
(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
|
||||||
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
|
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
|
||||||
}
|
}
|
||||||
|
|
||||||
val clearCnt = RegInit(0.U(4.W))
|
val clearCnt = RegInit(0.U(4.W))
|
||||||
val checkCnt = RegInit(0.U(4.W))
|
val checkCnt = RegInit(0.U(4.W))
|
||||||
val arbLock = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
|
val arbLock = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
|
||||||
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
|
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
|
||||||
val isLock = RegInit(false.B)
|
val isLock = RegInit(false.B)
|
||||||
|
|
||||||
when( sampleReg_sync.reduce(_|_) === false.B ){
|
when( sampleReg_sync.reduce(_|_) === false.B ){
|
||||||
when( clearCnt =/= 10.U ){
|
when( clearCnt =/= 10.U ){
|
||||||
clearCnt := clearCnt + 1.U
|
clearCnt := clearCnt + 1.U
|
||||||
}
|
}
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
clearCnt := 0.U
|
clearCnt := 0.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
checkCnt := 0.U
|
checkCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
checkCnt := checkCnt + 1.U
|
checkCnt := checkCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
|
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
for( i <- 3 until 19 ){
|
for( i <- 3 until 19 ){
|
||||||
val j = 19 - i - 1
|
val j = 19 - i - 1
|
||||||
when( flitReg(j) ^ flitReg(j+1) ){
|
when( flitReg(j) ^ flitReg(j+1) ){
|
||||||
arbLock := j.U
|
arbLock := j.U
|
||||||
arbCali := j.U
|
arbCali := j.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
|
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
|
||||||
for( i <- 0 until 22 ){
|
for( i <- 0 until 22 ){
|
||||||
val j = 22 - i -1
|
val j = 22 - i -1
|
||||||
when( flitReg(j) ^ flitReg(j+1) ){
|
when( flitReg(j) ^ flitReg(j+1) ){
|
||||||
when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
|
when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
|
||||||
arbCali := arbCali - 1.U
|
arbCali := arbCali - 1.U
|
||||||
} .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
|
} .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
|
||||||
arbCali := arbCali + 1.U
|
arbCali := arbCali + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( ~isLock ){
|
when( ~isLock ){
|
||||||
for( i <- 3 until 19 ){
|
for( i <- 3 until 19 ){
|
||||||
val j = 19 - i - 1
|
val j = 19 - i - 1
|
||||||
when( flitReg(j) ^ flitReg(j+1) ){
|
when( flitReg(j) ^ flitReg(j+1) ){
|
||||||
isLock := true.B
|
isLock := true.B
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} .elsewhen( clearCnt === 10.U ){
|
} .elsewhen( clearCnt === 10.U ){
|
||||||
isLock := false.B
|
isLock := false.B
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
val asyncSerDat =
|
val asyncSerDat =
|
||||||
Mux1H(
|
Mux1H(
|
||||||
(for { i <- 0 until 22 } yield {
|
(for { i <- 0 until 22 } yield {
|
||||||
(arbCali === i.U) -> flitReg(i+(8))
|
(arbCali === i.U) -> flitReg(i+(8))
|
||||||
})
|
})
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
io.syncSerDat := asyncSerDat
|
io.syncSerDat := asyncSerDat
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1,117 +1,117 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class AXIS_Bundle(dw: Int) extends Bundle{
|
class AXIS_Bundle(dw: Int) extends Bundle{
|
||||||
val tdata = UInt(dw.W)
|
val tdata = UInt(dw.W)
|
||||||
val tlast = Bool()
|
val tlast = Bool()
|
||||||
val tuser = Bool()
|
val tuser = Bool()
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//work in 100MHZ
|
//work in 100MHZ
|
||||||
class CDROutIO extends Bundle{
|
class CDROutIO extends Bundle{
|
||||||
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
|
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
|
||||||
val encode = Flipped(new Encode_Bundle)
|
val encode = Flipped(new Encode_Bundle)
|
||||||
val serDat = Output(Bool())
|
val serDat = Output(Bool())
|
||||||
|
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class CDROut extends Module with RequireAsyncReset{
|
class CDROut extends Module with RequireAsyncReset{
|
||||||
val io: CDROutIO = IO(new CDROutIO)
|
val io: CDROutIO = IO(new CDROutIO)
|
||||||
def PRE_NUM = 3 //PRE_NUM should >= 3
|
def PRE_NUM = 3 //PRE_NUM should >= 3
|
||||||
|
|
||||||
|
|
||||||
def STATE_IDLE = 0.U
|
def STATE_IDLE = 0.U
|
||||||
def STATE_PREAMBLE = 1.U
|
def STATE_PREAMBLE = 1.U
|
||||||
def STATE_PAYLOAD = 2.U
|
def STATE_PAYLOAD = 2.U
|
||||||
|
|
||||||
val ETH_PRE = "h68".U(8.W)
|
val ETH_PRE = "h68".U(8.W)
|
||||||
val ETH_SFD = "h25".U(8.W)
|
val ETH_SFD = "h25".U(8.W)
|
||||||
|
|
||||||
val stateNext = Wire(UInt(2.W))
|
val stateNext = Wire(UInt(2.W))
|
||||||
val stateCurr = RegNext( stateNext, 0.U )
|
val stateCurr = RegNext( stateNext, 0.U )
|
||||||
|
|
||||||
|
|
||||||
val bitCnt = RegInit(0.U(4.W))
|
val bitCnt = RegInit(0.U(4.W))
|
||||||
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
|
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
|
||||||
|
|
||||||
val shiftData = RegInit(0.U(10.W))
|
val shiftData = RegInit(0.U(10.W))
|
||||||
io.encode.isEnable := false.B //组合逻辑
|
io.encode.isEnable := false.B //组合逻辑
|
||||||
io.encode.dataIn := 0.U //组合逻辑
|
io.encode.dataIn := 0.U //组合逻辑
|
||||||
|
|
||||||
stateNext :=
|
stateNext :=
|
||||||
Mux( io.flush, STATE_IDLE,
|
Mux( io.flush, STATE_IDLE,
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
|
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
|
||||||
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
|
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
|
||||||
(stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
|
(stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
|
||||||
))
|
))
|
||||||
)
|
)
|
||||||
io.serDat := shiftData.extract(9)
|
io.serDat := shiftData.extract(9)
|
||||||
io.axis.ready :=
|
io.axis.ready :=
|
||||||
bitCnt === 9.U & (
|
bitCnt === 9.U & (
|
||||||
(stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
|
(stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
|
||||||
(stateCurr === STATE_PAYLOAD)
|
(stateCurr === STATE_PAYLOAD)
|
||||||
)
|
)
|
||||||
|
|
||||||
// assert( ~(~io.axis.valid & io.axis.ready) )
|
// assert( ~(~io.axis.valid & io.axis.ready) )
|
||||||
when( ~io.axis.valid & io.axis.ready ){
|
when( ~io.axis.valid & io.axis.ready ){
|
||||||
printf( "Error, CDROut axis overflow!\n" )
|
printf( "Error, CDROut axis overflow!\n" )
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
shiftData := 0.U
|
shiftData := 0.U
|
||||||
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
|
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
|
||||||
shiftData := io.encode.dataOut
|
shiftData := io.encode.dataOut
|
||||||
io.encode.dataIn := ETH_PRE //组合逻辑
|
io.encode.dataIn := ETH_PRE //组合逻辑
|
||||||
io.encode.isEnable := true.B //组合逻辑
|
io.encode.isEnable := true.B //组合逻辑
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
when( bitCnt =/= 9.U ){
|
when( bitCnt =/= 9.U ){
|
||||||
shiftData := shiftData << 1
|
shiftData := shiftData << 1
|
||||||
} .otherwise{ //bitCnt === 9.U
|
} .otherwise{ //bitCnt === 9.U
|
||||||
when( stateCurr === STATE_PREAMBLE ){
|
when( stateCurr === STATE_PREAMBLE ){
|
||||||
shiftData := io.encode.dataOut
|
shiftData := io.encode.dataOut
|
||||||
io.encode.dataIn := MuxCase( ETH_PRE, Array(
|
io.encode.dataIn := MuxCase( ETH_PRE, Array(
|
||||||
( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
|
( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
|
||||||
( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
|
( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
|
||||||
)) //组合逻辑
|
)) //组合逻辑
|
||||||
io.encode.isEnable := true.B //组合逻辑
|
io.encode.isEnable := true.B //组合逻辑
|
||||||
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
||||||
io.encode.dataIn := io.axis.bits.tdata //组合逻辑
|
io.encode.dataIn := io.axis.bits.tdata //组合逻辑
|
||||||
shiftData := io.encode.dataOut
|
shiftData := io.encode.dataOut
|
||||||
io.encode.isEnable := true.B //组合逻辑
|
io.encode.isEnable := true.B //组合逻辑
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( stateCurr === STATE_IDLE ){ //PRE
|
when( stateCurr === STATE_IDLE ){ //PRE
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
when( bitCnt === 9.U ){
|
when( bitCnt === 9.U ){
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
bitCnt := bitCnt + 1.U
|
bitCnt := bitCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
|
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
|
||||||
byteCnt := 0.U
|
byteCnt := 0.U
|
||||||
} .elsewhen( bitCnt === 9.U ){
|
} .elsewhen( bitCnt === 9.U ){
|
||||||
byteCnt := byteCnt + 1.U
|
byteCnt := byteCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -1,33 +1,33 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
class Encryptor_IO_Bundle extends Bundle{
|
class Encryptor_IO_Bundle extends Bundle{
|
||||||
val init = Flipped(Valid(UInt(128.W)))
|
val init = Flipped(Valid(UInt(128.W)))
|
||||||
|
|
||||||
val op = Decoupled(UInt(8.W))
|
val op = Decoupled(UInt(8.W))
|
||||||
}
|
}
|
||||||
|
|
||||||
class Encryptor extends Module{
|
class Encryptor extends Module{
|
||||||
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
|
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
|
||||||
|
|
||||||
val encryptReg = RegInit(0.U(128.W))
|
val encryptReg = RegInit(0.U(128.W))
|
||||||
|
|
||||||
when( io.init.valid ){
|
when( io.init.valid ){
|
||||||
encryptReg := io.init.bits
|
encryptReg := io.init.bits
|
||||||
} .elsewhen( io.op.fire ){
|
} .elsewhen( io.op.fire ){
|
||||||
encryptReg := Cat(encryptReg(119,0), io.op.bits)
|
encryptReg := Cat(encryptReg(119,0), io.op.bits)
|
||||||
}
|
}
|
||||||
|
|
||||||
val opValid = RegInit(false.B)
|
val opValid = RegInit(false.B)
|
||||||
when( io.init.fire ){
|
when( io.init.fire ){
|
||||||
opValid := true.B
|
opValid := true.B
|
||||||
}
|
}
|
||||||
|
|
||||||
io.op.valid := opValid
|
io.op.valid := opValid
|
||||||
io.op.bits := encryptReg(127, 120)
|
io.op.bits := encryptReg(127, 120)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,210 +1,210 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class MasterParserIO extends Bundle{
|
class MasterParserIO extends Bundle{
|
||||||
val downOut = Decoupled(new AXIS_Bundle(8))
|
val downOut = Decoupled(new AXIS_Bundle(8))
|
||||||
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
|
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
|
||||||
|
|
||||||
val sram_w = Flipped(new SRAM2kWRIO)
|
val sram_w = Flipped(new SRAM2kWRIO)
|
||||||
val sram_r = Flipped(new SRAM2kRDIO)
|
val sram_r = Flipped(new SRAM2kRDIO)
|
||||||
|
|
||||||
val req = Input(Bool())
|
val req = Input(Bool())
|
||||||
val rsp = Valid(new Bundle{
|
val rsp = Valid(new Bundle{
|
||||||
val isError = Bool()
|
val isError = Bool()
|
||||||
})
|
})
|
||||||
|
|
||||||
val rxEnq = Output( Bool())
|
val rxEnq = Output( Bool())
|
||||||
val txDeq = Output( Bool())
|
val txDeq = Output( Bool())
|
||||||
|
|
||||||
val cReg = Input(new CommonRegisterBundle)
|
val cReg = Input(new CommonRegisterBundle)
|
||||||
val mReg = Input(new MasterRegisterBundle)
|
val mReg = Input(new MasterRegisterBundle)
|
||||||
|
|
||||||
val deltaTimeStamp = Output(UInt(32.W))
|
val deltaTimeStamp = Output(UInt(32.W))
|
||||||
|
|
||||||
val upRecStat = Output(new Stat_IO_Bundle)
|
val upRecStat = Output(new Stat_IO_Bundle)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
abstract class MasterParserBase extends Module with RequireAsyncReset{
|
abstract class MasterParserBase extends Module with RequireAsyncReset{
|
||||||
val io: MasterParserIO = IO(new MasterParserIO)
|
val io: MasterParserIO = IO(new MasterParserIO)
|
||||||
|
|
||||||
val txCnt = RegInit(0.U(12.W))
|
val txCnt = RegInit(0.U(12.W))
|
||||||
val txLen = RegInit(0.U(11.W))
|
val txLen = RegInit(0.U(11.W))
|
||||||
val txAddr = RegInit(0.U(15.W))
|
val txAddr = RegInit(0.U(15.W))
|
||||||
val rxCnt = RegInit(0.U(12.W))
|
val rxCnt = RegInit(0.U(12.W))
|
||||||
val rxLen = RegInit(0.U(11.W))
|
val rxLen = RegInit(0.U(11.W))
|
||||||
val rxAddr = RegInit(0.U(15.W))
|
val rxAddr = RegInit(0.U(15.W))
|
||||||
|
|
||||||
val reqReady = RegInit(true.B)
|
val reqReady = RegInit(true.B)
|
||||||
|
|
||||||
|
|
||||||
val txcrc = Module(new crc32_8)
|
val txcrc = Module(new crc32_8)
|
||||||
val rxcrc = Module(new crc32_8)
|
val rxcrc = Module(new crc32_8)
|
||||||
|
|
||||||
when( io.req ){
|
when( io.req ){
|
||||||
reqReady := false.B
|
reqReady := false.B
|
||||||
} .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
|
} .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
|
||||||
reqReady := true.B
|
reqReady := true.B
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.req ){
|
when( io.req ){
|
||||||
txLen := Mux1H(Seq(
|
txLen := Mux1H(Seq(
|
||||||
( io.mReg.txSM === 0.U ) -> io.cReg.smTrigLen(1),
|
( io.mReg.txSM === 0.U ) -> io.cReg.smTrigLen(1),
|
||||||
( io.mReg.txSM === 1.U ) -> io.cReg.smTrigLen(3),
|
( io.mReg.txSM === 1.U ) -> io.cReg.smTrigLen(3),
|
||||||
( io.mReg.txSM === 2.U ) -> io.cReg.smTrigLen(5),
|
( io.mReg.txSM === 2.U ) -> io.cReg.smTrigLen(5),
|
||||||
( io.mReg.txSM === 3.U ) -> io.cReg.smTrigLen(7),
|
( io.mReg.txSM === 3.U ) -> io.cReg.smTrigLen(7),
|
||||||
))
|
))
|
||||||
rxLen := Mux1H(Seq(
|
rxLen := Mux1H(Seq(
|
||||||
( io.mReg.rxSM === 0.U ) -> io.cReg.smTrigLen(0),
|
( io.mReg.rxSM === 0.U ) -> io.cReg.smTrigLen(0),
|
||||||
( io.mReg.rxSM === 1.U ) -> io.cReg.smTrigLen(2),
|
( io.mReg.rxSM === 1.U ) -> io.cReg.smTrigLen(2),
|
||||||
( io.mReg.rxSM === 2.U ) -> io.cReg.smTrigLen(4),
|
( io.mReg.rxSM === 2.U ) -> io.cReg.smTrigLen(4),
|
||||||
( io.mReg.rxSM === 3.U ) -> io.cReg.smTrigLen(6),
|
( io.mReg.rxSM === 3.U ) -> io.cReg.smTrigLen(6),
|
||||||
))
|
))
|
||||||
txCnt := 0.U
|
txCnt := 0.U
|
||||||
} .elsewhen( io.downOut.fire ){
|
} .elsewhen( io.downOut.fire ){
|
||||||
txCnt := txCnt + 1.U
|
txCnt := txCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.req ){
|
when( io.req ){
|
||||||
txAddr := 0.U
|
txAddr := 0.U
|
||||||
} .elsewhen( io.downOut.fire ){
|
} .elsewhen( io.downOut.fire ){
|
||||||
txAddr := txAddr + 1.U
|
txAddr := txAddr + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.req ){
|
when( io.req ){
|
||||||
rxAddr := 0.U
|
rxAddr := 0.U
|
||||||
} .elsewhen( io.upIn.fire ){
|
} .elsewhen( io.upIn.fire ){
|
||||||
rxAddr := rxAddr + 1.U
|
rxAddr := rxAddr + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
io.sram_r.enr :=
|
io.sram_r.enr :=
|
||||||
io.req | io.downOut.fire
|
io.req | io.downOut.fire
|
||||||
|
|
||||||
io.sram_r.addrr := Mux( io.req, 0.U, txAddr + 1.U )
|
io.sram_r.addrr := Mux( io.req, 0.U, txAddr + 1.U )
|
||||||
|
|
||||||
io.downOut.valid := ~reqReady
|
io.downOut.valid := ~reqReady
|
||||||
|
|
||||||
|
|
||||||
val isRplTimeStamp = io.mReg.rplTimeStampTx.extract(15)
|
val isRplTimeStamp = io.mReg.rplTimeStampTx.extract(15)
|
||||||
val isRplDeltaStamp = io.mReg.rplTimeStampTx.extract(14)
|
val isRplDeltaStamp = io.mReg.rplTimeStampTx.extract(14)
|
||||||
val rplCnt0 = io.mReg.rplTimeStampTx(10,0) + 0.U
|
val rplCnt0 = io.mReg.rplTimeStampTx(10,0) + 0.U
|
||||||
val rplCnt1 = io.mReg.rplTimeStampTx(10,0) + 1.U
|
val rplCnt1 = io.mReg.rplTimeStampTx(10,0) + 1.U
|
||||||
val rplCnt2 = io.mReg.rplTimeStampTx(10,0) + 2.U
|
val rplCnt2 = io.mReg.rplTimeStampTx(10,0) + 2.U
|
||||||
val rplCnt3 = io.mReg.rplTimeStampTx(10,0) + 3.U
|
val rplCnt3 = io.mReg.rplTimeStampTx(10,0) + 3.U
|
||||||
val rplCnt4 = io.mReg.rplTimeStampTx(10,0) + 4.U
|
val rplCnt4 = io.mReg.rplTimeStampTx(10,0) + 4.U
|
||||||
val rplCnt5 = io.mReg.rplTimeStampTx(10,0) + 5.U
|
val rplCnt5 = io.mReg.rplTimeStampTx(10,0) + 5.U
|
||||||
val rplCnt6 = io.mReg.rplTimeStampTx(10,0) + 6.U
|
val rplCnt6 = io.mReg.rplTimeStampTx(10,0) + 6.U
|
||||||
val rplCnt7 = io.mReg.rplTimeStampTx(10,0) + 7.U
|
val rplCnt7 = io.mReg.rplTimeStampTx(10,0) + 7.U
|
||||||
val rplCnt8 = io.mReg.rplTimeStampTx(10,0) + 8.U
|
val rplCnt8 = io.mReg.rplTimeStampTx(10,0) + 8.U
|
||||||
val rplCnt9 = io.mReg.rplTimeStampTx(10,0) + 9.U
|
val rplCnt9 = io.mReg.rplTimeStampTx(10,0) + 9.U
|
||||||
val rplCnt10 = io.mReg.rplTimeStampTx(10,0) + 10.U
|
val rplCnt10 = io.mReg.rplTimeStampTx(10,0) + 10.U
|
||||||
val rplCnt11 = io.mReg.rplTimeStampTx(10,0) + 11.U
|
val rplCnt11 = io.mReg.rplTimeStampTx(10,0) + 11.U
|
||||||
|
|
||||||
|
|
||||||
io.downOut.bits.tdata := Mux1H(Seq(
|
io.downOut.bits.tdata := Mux1H(Seq(
|
||||||
( txCnt < txLen ) ->
|
( txCnt < txLen ) ->
|
||||||
MuxCase( io.sram_r.datar, Array(
|
MuxCase( io.sram_r.datar, Array(
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||||
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
|
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
|
||||||
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
|
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
|
||||||
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
|
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
|
||||||
( isRplDeltaStamp & ( txCnt === rplCnt11 ) ) -> io.cReg.mstDeltaTime(31,24),
|
( isRplDeltaStamp & ( txCnt === rplCnt11 ) ) -> io.cReg.mstDeltaTime(31,24),
|
||||||
)),
|
)),
|
||||||
( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
|
( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
|
||||||
( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
|
( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
|
||||||
( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
|
( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
|
||||||
( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0),
|
( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0),
|
||||||
))
|
))
|
||||||
io.downOut.bits.tuser := false.B
|
io.downOut.bits.tuser := false.B
|
||||||
io.downOut.bits.tlast := txCnt === (txLen + 3.U)
|
io.downOut.bits.tlast := txCnt === (txLen + 3.U)
|
||||||
|
|
||||||
val recCrcCheck = RegInit(0.U(32.W))
|
val recCrcCheck = RegInit(0.U(32.W))
|
||||||
|
|
||||||
when( io.req ){
|
when( io.req ){
|
||||||
rxCnt := 0.U
|
rxCnt := 0.U
|
||||||
} .elsewhen( io.upIn.fire ){
|
} .elsewhen( io.upIn.fire ){
|
||||||
rxCnt := rxCnt + 1.U
|
rxCnt := rxCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
io.upIn.ready := true.B
|
io.upIn.ready := true.B
|
||||||
|
|
||||||
io.sram_w.enw := io.upIn.fire
|
io.sram_w.enw := io.upIn.fire
|
||||||
io.sram_w.addrw := rxAddr
|
io.sram_w.addrw := rxAddr
|
||||||
io.sram_w.dataw := io.upIn.bits.tdata
|
io.sram_w.dataw := io.upIn.bits.tdata
|
||||||
|
|
||||||
|
|
||||||
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
|
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
|
||||||
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & (Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) =/= rxcrc.io.crc)
|
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & (Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) =/= rxcrc.io.crc)
|
||||||
|
|
||||||
io.rxEnq := io.upIn.fire & io.upIn.bits.tlast
|
io.rxEnq := io.upIn.fire & io.upIn.bits.tlast
|
||||||
io.txDeq := io.downOut.fire & io.downOut.bits.tlast
|
io.txDeq := io.downOut.fire & io.downOut.bits.tlast
|
||||||
|
|
||||||
txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
|
txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
|
||||||
txcrc.io.dataIn := io.downOut.bits.tdata
|
txcrc.io.dataIn := io.downOut.bits.tdata
|
||||||
txcrc.io.flush := reqReady
|
txcrc.io.flush := reqReady
|
||||||
|
|
||||||
rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
|
rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
|
||||||
rxcrc.io.dataIn := io.upIn.bits.tdata
|
rxcrc.io.dataIn := io.upIn.bits.tdata
|
||||||
rxcrc.io.flush := io.rsp.fire
|
rxcrc.io.flush := io.rsp.fire
|
||||||
|
|
||||||
when( io.upIn.fire ){
|
when( io.upIn.fire ){
|
||||||
when( rxCnt === rxLen ){
|
when( rxCnt === rxLen ){
|
||||||
recCrcCheck := io.upIn.bits.tdata << 24
|
recCrcCheck := io.upIn.bits.tdata << 24
|
||||||
} .elsewhen( rxCnt === (rxLen + 1.U) ){
|
} .elsewhen( rxCnt === (rxLen + 1.U) ){
|
||||||
recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) )
|
recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) )
|
||||||
} .elsewhen( rxCnt === (rxLen + 2.U) ){
|
} .elsewhen( rxCnt === (rxLen + 2.U) ){
|
||||||
recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) )
|
recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) )
|
||||||
} .elsewhen( rxCnt === (rxLen + 3.U) ){
|
} .elsewhen( rxCnt === (rxLen + 3.U) ){
|
||||||
recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata )
|
recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
trait MasterParserStat{ this: MasterParserBase =>
|
trait MasterParserStat{ this: MasterParserBase =>
|
||||||
io.upRecStat.isHeaderError := false.B
|
io.upRecStat.isHeaderError := false.B
|
||||||
io.upRecStat.isSubHeaderError := false.B
|
io.upRecStat.isSubHeaderError := false.B
|
||||||
io.upRecStat.isPayloadError := false.B
|
io.upRecStat.isPayloadError := false.B
|
||||||
io.upRecStat.isSubTailError := false.B
|
io.upRecStat.isSubTailError := false.B
|
||||||
io.upRecStat.isCRCError := io.rsp.valid & io.rsp.bits.isError
|
io.upRecStat.isCRCError := io.rsp.valid & io.rsp.bits.isError
|
||||||
io.upRecStat.isFinish := io.rsp.valid & ~io.rsp.bits.isError
|
io.upRecStat.isFinish := io.rsp.valid & ~io.rsp.bits.isError
|
||||||
io.upRecStat.isRecByteAck := io.upIn.fire
|
io.upRecStat.isRecByteAck := io.upIn.fire
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class MasterParser extends MasterParserBase
|
class MasterParser extends MasterParserBase
|
||||||
with MasterParserStat{
|
with MasterParserStat{
|
||||||
val deltaTimeStamp = RegInit(0.U(32.W))
|
val deltaTimeStamp = RegInit(0.U(32.W))
|
||||||
// dontTouch(deltaTimeStamp)
|
// dontTouch(deltaTimeStamp)
|
||||||
io.deltaTimeStamp := deltaTimeStamp
|
io.deltaTimeStamp := deltaTimeStamp
|
||||||
|
|
||||||
val txStamps = RegInit(0.U(32.W))
|
val txStamps = RegInit(0.U(32.W))
|
||||||
val pkgChkCnt = RegInit(0.U(4.W))
|
val pkgChkCnt = RegInit(0.U(4.W))
|
||||||
|
|
||||||
when( io.upIn.fire & io.upIn.bits.tlast ){
|
when( io.upIn.fire & io.upIn.bits.tlast ){
|
||||||
pkgChkCnt := 0.U
|
pkgChkCnt := 0.U
|
||||||
} .elsewhen( io.downOut.fire & pkgChkCnt =/= 9.U ){
|
} .elsewhen( io.downOut.fire & pkgChkCnt =/= 9.U ){
|
||||||
pkgChkCnt := pkgChkCnt + 1.U
|
pkgChkCnt := pkgChkCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( io.downOut.fire & io.downOut.bits.tlast ){
|
when( io.downOut.fire & io.downOut.bits.tlast ){
|
||||||
txStamps := io.cReg.timeStamp(31,0)
|
txStamps := io.cReg.timeStamp(31,0)
|
||||||
} .elsewhen( io.upIn.fire & io.upIn.bits.tlast & ~io.upIn.bits.tuser & pkgChkCnt === 9.U ){
|
} .elsewhen( io.upIn.fire & io.upIn.bits.tlast & ~io.upIn.bits.tuser & pkgChkCnt === 9.U ){
|
||||||
deltaTimeStamp := io.cReg.timeStamp(31,0) - txStamps
|
deltaTimeStamp := io.cReg.timeStamp(31,0) - txStamps
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,225 +1,227 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
|
abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
|
||||||
val io = IO(new RegAccessInterfaceIO)
|
val io = IO(new RegAccessInterfaceIO)
|
||||||
val qspi = IO(new QSPIInterfaceIO)
|
val qspi = IO(new QSPIInterfaceIO)
|
||||||
|
|
||||||
val bitSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
|
val negedge_sck = (~qspi.sck).asClock
|
||||||
val byteSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
|
|
||||||
val exRego = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
|
val bitSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
|
||||||
val exRegi = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
|
val byteSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
|
||||||
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
|
val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
|
||||||
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
|
val exRegi = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
|
||||||
val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } }
|
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
|
||||||
val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } }
|
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
|
||||||
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } }
|
val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } }
|
||||||
|
val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
|
||||||
val spiLen = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
|
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
|
||||||
val spiLenTemp = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
|
|
||||||
val spiCnt = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
|
val spiLen = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
|
||||||
val isSpiWrite = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
val spiLenTemp = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
|
||||||
val isSpiRead = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
val spiCnt = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
|
||||||
val isPing_async = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
val isSpiWrite = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
||||||
|
val isSpiRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
||||||
|
val isPing_async = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val isPong_sync = RegInit(false.B)
|
|
||||||
val isEnW_sync = for( i <- 0 until 2 ) yield { ShiftRegisters( isEnW_async(i), 3, false.B, true.B ) }
|
|
||||||
val isEnR_sync = for( i <- 0 until 2 ) yield { ShiftRegisters( isEnR_async(i), 3, false.B, true.B ) }
|
val isPong_sync = RegInit(false.B)
|
||||||
val datar_sync = for( _ <- 0 until 2 ) yield { RegInit(0.U(8.W)) }
|
val isEnW_sync = for( i <- 0 until 2 ) yield { ShiftRegisters( isEnW_async(i), 3, false.B, true.B ) }
|
||||||
val isEnW = for( i <- 0 until 2 ) yield { ~isEnW_sync(i)(2) & isEnW_sync(i)(1) }
|
val isEnR_sync = for( i <- 0 until 2 ) yield { ShiftRegisters( isEnR_async(i), 3, false.B, true.B ) }
|
||||||
val isEnR = for( i <- 0 until 2 ) yield { ~isEnR_sync(i)(2) & isEnR_sync(i)(1) }
|
val datar_sync = for( _ <- 0 until 2 ) yield { RegInit(0.U(8.W)) }
|
||||||
|
val isEnW = for( i <- 0 until 2 ) yield { ~isEnW_sync(i)(2) & isEnW_sync(i)(1) }
|
||||||
}
|
val isEnR = for( i <- 0 until 2 ) yield { ~isEnR_sync(i)(2) & isEnR_sync(i)(1) }
|
||||||
|
|
||||||
trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
|
}
|
||||||
|
|
||||||
|
trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
|
||||||
|
|
||||||
qspi.miso := exRego(7, 4)
|
|
||||||
qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
|
|
||||||
|
qspi.miso := exRego(7, 4)
|
||||||
when( true.B ){
|
qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
|
||||||
bitSel := ~bitSel
|
|
||||||
}
|
when( true.B ){
|
||||||
|
bitSel := ~bitSel
|
||||||
when( bitSel.andR ){
|
}
|
||||||
byteSel := byteSel + 1.U
|
|
||||||
}
|
when( bitSel.andR ){
|
||||||
|
byteSel := byteSel + 1.U
|
||||||
when( bitSel === 0.U ){
|
}
|
||||||
exRegi := Cat( 0.U, qspi.mosi )
|
|
||||||
}.otherwise{
|
when( bitSel === 0.U ){
|
||||||
exRegi := Cat( exRegi(3,0), qspi.mosi )
|
exRegi := Cat( 0.U, qspi.mosi )
|
||||||
}
|
}.otherwise{
|
||||||
|
exRegi := Cat( exRegi(3,0), qspi.mosi )
|
||||||
when( bitSel.andR ){
|
}
|
||||||
when((byteSel === 1.U || byteSel === 2.U ) ){
|
|
||||||
exRego := 0.U //地址1，cmd
|
when( bitSel.andR ){
|
||||||
} .elsewhen( isSpiRead ){
|
when((byteSel === 1.U || byteSel === 2.U ) ){
|
||||||
when( isPing_async ){ //取巧
|
exRego := 0.U //地址1，cmd
|
||||||
exRego := datar_sync(0)
|
} .elsewhen( isSpiRead ){
|
||||||
} .otherwise{
|
when( isPing_async ){ //取巧
|
||||||
exRego := datar_sync(1)
|
exRego := datar_sync(0)
|
||||||
}
|
} .otherwise{
|
||||||
}
|
exRego := datar_sync(1)
|
||||||
} .otherwise{
|
}
|
||||||
exRego := exRego << 4
|
}
|
||||||
}
|
} .otherwise{
|
||||||
|
exRego := exRego << 4
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
when( isEnR_async(0) | isEnW_async(0) | isEnR_async(1) | isEnW_async(1) ){
|
|
||||||
spiCnt := spiCnt + 1.U
|
|
||||||
}
|
when( isEnR_async(0) | isEnW_async(0) | isEnR_async(1) | isEnW_async(1) ){
|
||||||
|
spiCnt := spiCnt + 1.U
|
||||||
|
}
|
||||||
when( byteSel === 2.U & bitSel.andR ){
|
|
||||||
spiLenTemp := Cat( qspi.mosi, 0.U(8.W) )
|
|
||||||
} .elsewhen( byteSel === 3.U & bitSel === 0.U ){
|
when( byteSel === 2.U & bitSel.andR ){
|
||||||
spiLenTemp := Cat( spiLenTemp(11, 8), qspi.mosi, 0.U(4.W) )
|
spiLenTemp := Cat( qspi.mosi, 0.U(8.W) )
|
||||||
} .elsewhen( byteSel === 3.U & bitSel.andR ){
|
} .elsewhen( byteSel === 3.U & bitSel === 0.U ){
|
||||||
spiLen := Cat( spiLenTemp(11, 4), qspi.mosi )
|
spiLenTemp := Cat( spiLenTemp(11, 8), qspi.mosi, 0.U(4.W) )
|
||||||
}
|
} .elsewhen( byteSel === 3.U & bitSel.andR ){
|
||||||
|
spiLen := Cat( spiLenTemp(11, 4), qspi.mosi )
|
||||||
|
}
|
||||||
when( isEnW_async(0) ){
|
|
||||||
addrw_async(0) := addrw_async(0) + 2.U
|
|
||||||
} .elsewhen( isEnW_async(1) ){
|
when( isEnW_async(0) ){
|
||||||
addrw_async(1) := addrw_async(1) + 2.U
|
addrw_async(0) := addrw_async(0) + 2.U
|
||||||
} .elsewhen( bitSel === 0.U ){
|
} .elsewhen( isEnW_async(1) ){
|
||||||
when( byteSel === 1.U ){
|
addrw_async(1) := addrw_async(1) + 2.U
|
||||||
addrw_async(0) := exRegi
|
} .elsewhen( bitSel === 0.U ){
|
||||||
addrw_async(1) := exRegi
|
when( byteSel === 1.U ){
|
||||||
} .elsewhen( byteSel === 2.U ) {
|
addrw_async(0) := exRegi
|
||||||
addrw_async(0) := Cat(addrw_async(0)(7,0), exRegi)
|
addrw_async(1) := exRegi
|
||||||
addrw_async(1) := Cat(addrw_async(1)(7,0), exRegi) + 1.U
|
} .elsewhen( byteSel === 2.U ) {
|
||||||
}
|
addrw_async(0) := Cat(addrw_async(0)(7,0), exRegi)
|
||||||
}
|
addrw_async(1) := Cat(addrw_async(1)(7,0), exRegi) + 1.U
|
||||||
|
}
|
||||||
|
}
|
||||||
when( isEnR_async(0) ){
|
|
||||||
addrr_async(0) := addrr_async(0) + 2.U
|
|
||||||
} .elsewhen( isEnR_async(1) ){
|
when( isEnR_async(0) ){
|
||||||
addrr_async(1) := addrr_async(1) + 2.U
|
addrr_async(0) := addrr_async(0) + 2.U
|
||||||
} .elsewhen( bitSel === 0.U ){
|
} .elsewhen( isEnR_async(1) ){
|
||||||
when( byteSel === 1.U ){
|
addrr_async(1) := addrr_async(1) + 2.U
|
||||||
addrr_async(0) := exRegi
|
} .elsewhen( bitSel === 0.U ){
|
||||||
addrr_async(1) := exRegi
|
when( byteSel === 1.U ){
|
||||||
} .elsewhen( byteSel === 2.U ) {
|
addrr_async(0) := exRegi
|
||||||
addrr_async(0) := Cat(addrr_async(0)(7,0), exRegi)
|
addrr_async(1) := exRegi
|
||||||
addrr_async(1) := Cat(addrr_async(1)(7,0), exRegi) + 1.U
|
} .elsewhen( byteSel === 2.U ) {
|
||||||
}
|
addrr_async(0) := Cat(addrr_async(0)(7,0), exRegi)
|
||||||
}
|
addrr_async(1) := Cat(addrr_async(1)(7,0), exRegi) + 1.U
|
||||||
|
}
|
||||||
when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
}
|
||||||
when( qspi.mosi.extract(3) ){
|
|
||||||
isSpiRead := true.B
|
when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
||||||
} .otherwise{
|
when( qspi.mosi.extract(3) ){
|
||||||
isSpiWrite := true.B
|
isSpiRead := true.B
|
||||||
}
|
} .otherwise{
|
||||||
}
|
isSpiWrite := true.B
|
||||||
|
}
|
||||||
when( bitSel.andR ){
|
}
|
||||||
when( byteSel >= 4.U & isSpiWrite ){
|
|
||||||
when( ~isPing_async ){
|
when( bitSel.andR ){
|
||||||
dataw_async(0) := Cat( exRegi(3,0), qspi.mosi )
|
when( byteSel >= 4.U & isSpiWrite ){
|
||||||
} .otherwise{
|
when( ~isPing_async ){
|
||||||
dataw_async(1) := Cat( exRegi(3,0), qspi.mosi )
|
dataw_async(0) := Cat( exRegi(3,0), qspi.mosi )
|
||||||
}
|
} .otherwise{
|
||||||
}
|
dataw_async(1) := Cat( exRegi(3,0), qspi.mosi )
|
||||||
}
|
}
|
||||||
|
}
|
||||||
when(
|
}
|
||||||
(byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi === "h8".U) ||
|
|
||||||
(byteSel > 2.U & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead)
|
when(
|
||||||
){
|
(byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi === "h8".U) ||
|
||||||
when( ~isPing_async ){
|
(byteSel > 2.U & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead)
|
||||||
isEnR_async(0) := true.B
|
){
|
||||||
} .otherwise{
|
when( ~isPing_async ){
|
||||||
isEnR_async(1) := true.B
|
isEnR_async(0) := true.B
|
||||||
}
|
} .otherwise{
|
||||||
} .elsewhen( bitSel.andR ){
|
isEnR_async(1) := true.B
|
||||||
isEnR_async(0) := false.B
|
}
|
||||||
isEnR_async(1) := false.B
|
} .elsewhen( bitSel.andR ){
|
||||||
}
|
isEnR_async(0) := false.B
|
||||||
|
isEnR_async(1) := false.B
|
||||||
when( byteSel >= 4.U & bitSel.andR & (spiCnt < spiLen) & isSpiWrite ){
|
}
|
||||||
when( ~isPing_async ){
|
|
||||||
isEnW_async(0) := true.B
|
when( byteSel >= 4.U & bitSel.andR & (spiCnt < spiLen) & isSpiWrite ){
|
||||||
} .otherwise{
|
when( ~isPing_async ){
|
||||||
isEnW_async(1) := true.B
|
isEnW_async(0) := true.B
|
||||||
}
|
} .otherwise{
|
||||||
} .elsewhen( bitSel === 0.U ){
|
isEnW_async(1) := true.B
|
||||||
isEnW_async(0) := false.B
|
}
|
||||||
isEnW_async(1) := false.B
|
} .elsewhen( bitSel === 0.U ){
|
||||||
}
|
isEnW_async(0) := false.B
|
||||||
|
isEnW_async(1) := false.B
|
||||||
when( isEnR_async(0) | isEnW_async(0) ){
|
}
|
||||||
assert( ~isPing_async )
|
|
||||||
isPing_async := true.B
|
when( isEnR_async(0) | isEnW_async(0) ){
|
||||||
} .elsewhen( isEnR_async(1) | isEnW_async(1) ){
|
assert( ~isPing_async )
|
||||||
assert( isPing_async )
|
isPing_async := true.B
|
||||||
isPing_async := false.B
|
} .elsewhen( isEnR_async(1) | isEnW_async(1) ){
|
||||||
}
|
assert( isPing_async )
|
||||||
|
isPing_async := false.B
|
||||||
|
}
|
||||||
}
|
|
||||||
|
|
||||||
trait SyncSpiSync{ this: SyncSpiInterfaceBase =>
|
}
|
||||||
|
|
||||||
io.isEnW :=
|
trait SyncSpiSync{ this: SyncSpiInterfaceBase =>
|
||||||
( ~isPong_sync & isEnW(0) ) |
|
|
||||||
( isPong_sync & isEnW(1) )
|
io.isEnW :=
|
||||||
|
( ~isPong_sync & isEnW(0) ) |
|
||||||
io.isEnR :=
|
( isPong_sync & isEnW(1) )
|
||||||
( ~isPong_sync & isEnR(0) ) |
|
|
||||||
( isPong_sync & isEnR(1) )
|
io.isEnR :=
|
||||||
|
( ~isPong_sync & isEnR(0) ) |
|
||||||
|
( isPong_sync & isEnR(1) )
|
||||||
io.addrw := Mux1H(Seq(
|
|
||||||
~isPong_sync -> addrw_async(0),
|
|
||||||
isPong_sync -> addrw_async(1),
|
io.addrw := Mux1H(Seq(
|
||||||
))
|
~isPong_sync -> addrw_async(0),
|
||||||
|
isPong_sync -> addrw_async(1),
|
||||||
io.addrr := Mux1H(Seq(
|
))
|
||||||
~isPong_sync -> addrr_async(0),
|
|
||||||
isPong_sync -> addrr_async(1),
|
io.addrr := Mux1H(Seq(
|
||||||
))
|
~isPong_sync -> addrr_async(0),
|
||||||
|
isPong_sync -> addrr_async(1),
|
||||||
io.dataw := Mux1H(Seq(
|
))
|
||||||
~isPong_sync -> dataw_async(0),
|
|
||||||
isPong_sync -> dataw_async(1),
|
io.dataw := Mux1H(Seq(
|
||||||
))
|
~isPong_sync -> dataw_async(0),
|
||||||
|
isPong_sync -> dataw_async(1),
|
||||||
when( RegNext(io.isEnR, false.B) ){
|
))
|
||||||
when( RegNext(~isPong_sync, false.B) ){
|
|
||||||
datar_sync(0) := io.datar
|
when( RegNext(io.isEnR, false.B) ){
|
||||||
} .otherwise{
|
when( RegNext(~isPong_sync, false.B) ){
|
||||||
datar_sync(1) := io.datar
|
datar_sync(0) := io.datar
|
||||||
}
|
} .otherwise{
|
||||||
}
|
datar_sync(1) := io.datar
|
||||||
|
}
|
||||||
when( ShiftRegister( qspi.csn, 2, false.B, true.B ) ){
|
}
|
||||||
isPong_sync := false.B
|
|
||||||
} .elsewhen( io.isEnR | io.isEnW ){
|
when( ShiftRegister( qspi.csn, 2, false.B, true.B ) ){
|
||||||
isPong_sync := ~isPong_sync
|
isPong_sync := false.B
|
||||||
}
|
} .elsewhen( io.isEnR | io.isEnW ){
|
||||||
|
isPong_sync := ~isPong_sync
|
||||||
|
}
|
||||||
}
|
|
||||||
|
|
||||||
class SyncQSpiInterface extends SyncSpiInterfaceBase
|
}
|
||||||
with SyncSpiAsync
|
|
||||||
with SyncSpiSync{
|
class SyncQSpiInterface extends SyncSpiInterfaceBase
|
||||||
}
|
with SyncSpiAsync
|
||||||
|
with SyncSpiSync{
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,110 +1,110 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
class SRAM2kWRIO extends Bundle {
|
class SRAM2kWRIO extends Bundle {
|
||||||
val addrw = Input(UInt(11.W))
|
val addrw = Input(UInt(11.W))
|
||||||
val dataw = Input( UInt(8.W) )
|
val dataw = Input( UInt(8.W) )
|
||||||
val enw = Input(Bool())
|
val enw = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
class SRAM2kRDIO extends Bundle {
|
class SRAM2kRDIO extends Bundle {
|
||||||
val addrr = Input(UInt(11.W))
|
val addrr = Input(UInt(11.W))
|
||||||
val datar = Output( UInt(8.W) )
|
val datar = Output( UInt(8.W) )
|
||||||
val enr = Input(Bool())
|
val enr = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class SRAM2kIO extends Bundle {
|
class SRAM2kIO extends Bundle {
|
||||||
val rd = new SRAM2kRDIO
|
val rd = new SRAM2kRDIO
|
||||||
val wr = new SRAM2kWRIO
|
val wr = new SRAM2kWRIO
|
||||||
}
|
}
|
||||||
|
|
||||||
class SMUnitIO(depth: Int) extends Bundle {
|
class SMUnitIO(depth: Int) extends Bundle {
|
||||||
|
|
||||||
val sram_w = new SRAM2kWRIO
|
val sram_w = new SRAM2kWRIO
|
||||||
val sram_r = new SRAM2kRDIO
|
val sram_r = new SRAM2kRDIO
|
||||||
|
|
||||||
val enq = Input(Bool())
|
val enq = Input(Bool())
|
||||||
val deq = Input(Bool())
|
val deq = Input(Bool())
|
||||||
|
|
||||||
val sram = Flipped(Vec(depth, new SRAM2kIO))
|
val sram = Flipped(Vec(depth, new SRAM2kIO))
|
||||||
val cnt = Output(UInt(8.W))
|
val cnt = Output(UInt(8.W))
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
val isComf = Input(Bool())
|
val isComf = Input(Bool())
|
||||||
val isAbrt = Input(Bool())
|
val isAbrt = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
|
abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
|
||||||
val io: SMUnitIO = IO(new SMUnitIO(depth))
|
val io: SMUnitIO = IO(new SMUnitIO(depth))
|
||||||
|
|
||||||
|
|
||||||
val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||||
val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||||
val cPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
val cPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||||
|
|
||||||
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
|
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
|
||||||
val isEmpty = ( cPtr === rPtr )
|
val isEmpty = ( cPtr === rPtr )
|
||||||
|
|
||||||
when(io.flush){
|
when(io.flush){
|
||||||
wPtr := 0.U
|
wPtr := 0.U
|
||||||
} .elsewhen( io.enq & ~isFull ){
|
} .elsewhen( io.enq & ~isFull ){
|
||||||
wPtr := wPtr + 1.U
|
wPtr := wPtr + 1.U
|
||||||
// assert( ~isFull)
|
// assert( ~isFull)
|
||||||
} .elsewhen( io.isAbrt ){
|
} .elsewhen( io.isAbrt ){
|
||||||
wPtr := cPtr
|
wPtr := cPtr
|
||||||
}
|
}
|
||||||
|
|
||||||
when(io.flush){
|
when(io.flush){
|
||||||
rPtr := 0.U
|
rPtr := 0.U
|
||||||
} .elsewhen( io.deq & ~isEmpty ){
|
} .elsewhen( io.deq & ~isEmpty ){
|
||||||
rPtr := rPtr + 1.U
|
rPtr := rPtr + 1.U
|
||||||
// assert( ~isEmpty )
|
// assert( ~isEmpty )
|
||||||
}
|
}
|
||||||
|
|
||||||
for( i <- 0 until depth ){
|
for( i <- 0 until depth ){
|
||||||
io.sram(i).wr.addrw := 0.U
|
io.sram(i).wr.addrw := 0.U
|
||||||
io.sram(i).wr.dataw := 0.U
|
io.sram(i).wr.dataw := 0.U
|
||||||
io.sram(i).wr.enw := false.B
|
io.sram(i).wr.enw := false.B
|
||||||
|
|
||||||
io.sram(i).rd.addrr := 0.U
|
io.sram(i).rd.addrr := 0.U
|
||||||
io.sram(i).rd.enr := false.B
|
io.sram(i).rd.enr := false.B
|
||||||
}
|
}
|
||||||
|
|
||||||
for( i <- 0 until depth ){
|
for( i <- 0 until depth ){
|
||||||
when( (wPtr(log2Ceil(depth)-1, 0)) === i.U & ~isFull ){
|
when( (wPtr(log2Ceil(depth)-1, 0)) === i.U & ~isFull ){
|
||||||
io.sram(i).wr <> io.sram_w
|
io.sram(i).wr <> io.sram_w
|
||||||
}
|
}
|
||||||
|
|
||||||
when( (rPtr(log2Ceil(depth)-1, 0)) === i.U & ~isEmpty){
|
when( (rPtr(log2Ceil(depth)-1, 0)) === i.U & ~isEmpty){
|
||||||
io.sram(i).rd.addrr := io.sram_r.addrr
|
io.sram(i).rd.addrr := io.sram_r.addrr
|
||||||
io.sram(i).rd.enr := io.sram_r.enr
|
io.sram(i).rd.enr := io.sram_r.enr
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
|
io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
|
||||||
( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
|
( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
|
||||||
})
|
})
|
||||||
|
|
||||||
io.cnt := cPtr - rPtr
|
io.cnt := cPtr - rPtr
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
cPtr := 0.U
|
cPtr := 0.U
|
||||||
} .elsewhen( io.isComf ){
|
} .elsewhen( io.isComf ){
|
||||||
cPtr := wPtr
|
cPtr := wPtr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
|
class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,66 +1,66 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
|
class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
|
||||||
|
|
||||||
class ShareSRAM2kIO extends Bundle{
|
class ShareSRAM2kIO extends Bundle{
|
||||||
val dataw = Input( UInt(8.W) )
|
val dataw = Input( UInt(8.W) )
|
||||||
val addrw = Input(UInt(15.W))
|
val addrw = Input(UInt(15.W))
|
||||||
val enw = Input(Bool())
|
val enw = Input(Bool())
|
||||||
|
|
||||||
val datar = Output( UInt(8.W) )
|
val datar = Output( UInt(8.W) )
|
||||||
val addrr = Input(UInt(15.W))
|
val addrr = Input(UInt(15.W))
|
||||||
val enr = Input(Bool())
|
val enr = Input(Bool())
|
||||||
|
|
||||||
val clockr = Input(Bool())
|
val clockr = Input(Bool())
|
||||||
val clockw = Input(Bool())
|
val clockw = Input(Bool())
|
||||||
|
|
||||||
}
|
}
|
||||||
val io: ShareSRAM2kIO = IO(new ShareSRAM2kIO)
|
val io: ShareSRAM2kIO = IO(new ShareSRAM2kIO)
|
||||||
|
|
||||||
setInline("ShareSRAM2k.v",
|
setInline("ShareSRAM2k.v",
|
||||||
"""
|
"""
|
||||||
|
|
||||||
| module ShareSRAM2k(
|
| module ShareSRAM2k(
|
||||||
| input [7:0] dataw,
|
| input [7:0] dataw,
|
||||||
| input [14:0] addrw,
|
| input [14:0] addrw,
|
||||||
| input enw,
|
| input enw,
|
||||||
|
|
|
|
||||||
| output [7:0] datar,
|
| output [7:0] datar,
|
||||||
| input [14:0] addrr,
|
| input [14:0] addrr,
|
||||||
| input enr,
|
| input enr,
|
||||||
|
|
|
|
||||||
| input clockr,
|
| input clockr,
|
||||||
| input clockw
|
| input clockw
|
||||||
| );
|
| );
|
||||||
|
|
|
|
||||||
| reg [7:0] ram[0:2047];
|
| reg [7:0] ram[0:2047];
|
||||||
| reg [7:0] data_r_reg;
|
| reg [7:0] data_r_reg;
|
||||||
|
|
|
|
||||||
| always @(posedge clockw) begin
|
| always @(posedge clockw) begin
|
||||||
| if(enw) begin
|
| if(enw) begin
|
||||||
| ram[addrw] <= #1 dataw;
|
| ram[addrw] <= #1 dataw;
|
||||||
| end
|
| end
|
||||||
| end
|
| end
|
||||||
|
|
|
|
||||||
| always @(posedge clockr) begin
|
| always @(posedge clockr) begin
|
||||||
| if(enr) begin
|
| if(enr) begin
|
||||||
| data_r_reg <= #1 ram[addrr];
|
| data_r_reg <= #1 ram[addrr];
|
||||||
| end
|
| end
|
||||||
| end
|
| end
|
||||||
|
|
|
|
||||||
| assign datar = data_r_reg;
|
| assign datar = data_r_reg;
|
||||||
|
|
|
|
||||||
| initial begin
|
| initial begin
|
||||||
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
|
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
|
||||||
| ram[i] = $random;
|
| ram[i] = $random;
|
||||||
| end
|
| end
|
||||||
|
|
|
|
||||||
| data_r_reg = $random;
|
| data_r_reg = $random;
|
||||||
| end
|
| end
|
||||||
|
|
|
|
||||||
| endmodule
|
| endmodule
|
||||||
""".stripMargin)
|
""".stripMargin)
|
||||||
}
|
}
|
||||||
@@ -1,64 +1,64 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
import chisel3.experimental.dataview._
|
import chisel3.experimental.dataview._
|
||||||
|
|
||||||
class ShinTopIO extends TopBase_IO_Bundle{
|
class ShinTopIO extends TopBase_IO_Bundle{
|
||||||
val multiCLK = Input(Vec(16, Bool()))
|
val multiCLK = Input(Vec(16, Bool()))
|
||||||
val multiCLKDiv4 = Input(Vec(4, Bool()))
|
val multiCLKDiv4 = Input(Vec(4, Bool()))
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class ShinTop extends Module with RequireAsyncReset{
|
class ShinTop extends Module with RequireAsyncReset{
|
||||||
val io: ShinTopIO = IO(new ShinTopIO)
|
val io: ShinTopIO = IO(new ShinTopIO)
|
||||||
|
|
||||||
val mstSlvSwitch = Module(new MstSlvSwitch)
|
val mstSlvSwitch = Module(new MstSlvSwitch)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
{
|
{
|
||||||
val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
|
val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
|
||||||
val upCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
|
val upCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
|
||||||
|
|
||||||
downCDRInSampleA.multiCLK := io.multiCLK
|
downCDRInSampleA.multiCLK := io.multiCLK
|
||||||
upCDRInSampleA.multiCLK := io.multiCLK
|
upCDRInSampleA.multiCLK := io.multiCLK
|
||||||
|
|
||||||
downCDRInSampleA.io <> mstSlvSwitch.io.downCDRSampleIn(0)
|
downCDRInSampleA.io <> mstSlvSwitch.io.downCDRSampleIn(0)
|
||||||
upCDRInSampleA.io <> mstSlvSwitch.io.upCDRSampleIn(0)
|
upCDRInSampleA.io <> mstSlvSwitch.io.upCDRSampleIn(0)
|
||||||
}
|
}
|
||||||
|
|
||||||
{
|
{
|
||||||
val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
|
val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
|
||||||
val upCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
|
val upCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
|
||||||
|
|
||||||
downCDRInSampleB.multiCLK := io.multiCLKDiv4
|
downCDRInSampleB.multiCLK := io.multiCLKDiv4
|
||||||
upCDRInSampleB.multiCLK := io.multiCLKDiv4
|
upCDRInSampleB.multiCLK := io.multiCLKDiv4
|
||||||
|
|
||||||
downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
|
downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
|
||||||
upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
|
upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
|
||||||
}
|
}
|
||||||
|
|
||||||
{
|
{
|
||||||
val downCDRInSampleC = Module(new CDRInOriSample)
|
val downCDRInSampleC = Module(new CDRInOriSample)
|
||||||
val upCDRInSampleC = Module(new CDRInOriSample)
|
val upCDRInSampleC = Module(new CDRInOriSample)
|
||||||
|
|
||||||
downCDRInSampleC.multiCLK := io.multiCLK
|
downCDRInSampleC.multiCLK := io.multiCLK
|
||||||
upCDRInSampleC.multiCLK := io.multiCLK
|
upCDRInSampleC.multiCLK := io.multiCLK
|
||||||
|
|
||||||
downCDRInSampleC.io <> mstSlvSwitch.io.downCDRSampleIn(2)
|
downCDRInSampleC.io <> mstSlvSwitch.io.downCDRSampleIn(2)
|
||||||
upCDRInSampleC.io <> mstSlvSwitch.io.upCDRSampleIn(2)
|
upCDRInSampleC.io <> mstSlvSwitch.io.upCDRSampleIn(2)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
|
io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,211 +1,211 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
class SlaveRecParserIO extends Bundle{
|
class SlaveRecParserIO extends Bundle{
|
||||||
val rec = Flipped( Decoupled(new AXIS_Bundle(8)) )
|
val rec = Flipped( Decoupled(new AXIS_Bundle(8)) )
|
||||||
|
|
||||||
val data = Decoupled(UInt(8.W))
|
val data = Decoupled(UInt(8.W))
|
||||||
|
|
||||||
val stateNext = Output(UInt(4.W))
|
val stateNext = Output(UInt(4.W))
|
||||||
val stateCurr = Output(UInt(4.W))
|
val stateCurr = Output(UInt(4.W))
|
||||||
|
|
||||||
val frameReq = Valid( new FrameHeader )
|
val frameReq = Valid( new FrameHeader )
|
||||||
val subMsgHeadReq = Valid( new SubMsgHeader )
|
val subMsgHeadReq = Valid( new SubMsgHeader )
|
||||||
val subMsgTailReq = Valid( new SubMsgTail )
|
val subMsgTailReq = Valid( new SubMsgTail )
|
||||||
|
|
||||||
val isError = Output(Bool())
|
val isError = Output(Bool())
|
||||||
|
|
||||||
val stat = Output(new Stat_IO_Bundle)
|
val stat = Output(new Stat_IO_Bundle)
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
class SlaveRecParser extends Module with RequireAsyncReset{
|
class SlaveRecParser extends Module with RequireAsyncReset{
|
||||||
val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
|
val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
|
||||||
|
|
||||||
val crc = Module(new crc32_8)
|
val crc = Module(new crc32_8)
|
||||||
|
|
||||||
val STATE_IDLE = 0.U //空闲
|
val STATE_IDLE = 0.U //空闲
|
||||||
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
|
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
|
||||||
val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
|
val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
|
||||||
val STATE_PAYLOAD_DATA = 3.U //子报文数据
|
val STATE_PAYLOAD_DATA = 3.U //子报文数据
|
||||||
val STATE_SUBMSG_TAIL = 4.U
|
val STATE_SUBMSG_TAIL = 4.U
|
||||||
val STATE_CRC = 5.U //CRC校验
|
val STATE_CRC = 5.U //CRC校验
|
||||||
val STATE_ERROR = 6.U //
|
val STATE_ERROR = 6.U //
|
||||||
|
|
||||||
|
|
||||||
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
|
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
|
||||||
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
|
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
|
||||||
|
|
||||||
io.isError := stateCurr === STATE_ERROR
|
io.isError := stateCurr === STATE_ERROR
|
||||||
io.rec.ready := stateCurr =/= STATE_IDLE
|
io.rec.ready := stateCurr =/= STATE_IDLE
|
||||||
|
|
||||||
crc.io.isEnable := io.rec.fire & (
|
crc.io.isEnable := io.rec.fire & (
|
||||||
stateCurr === STATE_HEADER |
|
stateCurr === STATE_HEADER |
|
||||||
stateCurr === STATE_SUBMSG_HEADER |
|
stateCurr === STATE_SUBMSG_HEADER |
|
||||||
stateCurr === STATE_PAYLOAD_DATA |
|
stateCurr === STATE_PAYLOAD_DATA |
|
||||||
stateCurr === STATE_SUBMSG_TAIL
|
stateCurr === STATE_SUBMSG_TAIL
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
crc.io.dataIn := io.rec.bits.tdata
|
crc.io.dataIn := io.rec.bits.tdata
|
||||||
|
|
||||||
crc.io.flush := stateCurr === STATE_IDLE | io.flush
|
crc.io.flush := stateCurr === STATE_IDLE | io.flush
|
||||||
|
|
||||||
val crcData = RegInit(0.U(32.W))
|
val crcData = RegInit(0.U(32.W))
|
||||||
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
|
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
|
||||||
|
|
||||||
when( io.rec.fire & stateCurr === STATE_CRC ){
|
when( io.rec.fire & stateCurr === STATE_CRC ){
|
||||||
crcData := Cat( crcData(23,0), io.rec.bits.tdata )
|
crcData := Cat( crcData(23,0), io.rec.bits.tdata )
|
||||||
}
|
}
|
||||||
|
|
||||||
val FRAME_STYLE_COMMON = 0.U
|
val FRAME_STYLE_COMMON = 0.U
|
||||||
val FRAME_STYLE_PROBE = 1.U
|
val FRAME_STYLE_PROBE = 1.U
|
||||||
|
|
||||||
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
|
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
|
||||||
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
|
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
|
||||||
|
|
||||||
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
|
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
|
||||||
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
|
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
|
||||||
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
|
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
|
||||||
io.frameReq.bits.frameStyle := frameHeader.frameStyle
|
io.frameReq.bits.frameStyle := frameHeader.frameStyle
|
||||||
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
|
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
|
||||||
|
|
||||||
io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
|
io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
|
||||||
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
|
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
|
||||||
|
|
||||||
val subMsgHeader = RegInit(0.U.asTypeOf(new SubMsgHeader))
|
val subMsgHeader = RegInit(0.U.asTypeOf(new SubMsgHeader))
|
||||||
val subMsgTail = RegInit(0.U.asTypeOf(new SubMsgTail))
|
val subMsgTail = RegInit(0.U.asTypeOf(new SubMsgTail))
|
||||||
|
|
||||||
io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
|
io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
|
||||||
io.subMsgHeadReq.bits.style := subMsgHeader.style
|
io.subMsgHeadReq.bits.style := subMsgHeader.style
|
||||||
io.subMsgHeadReq.bits.address := subMsgHeader.address
|
io.subMsgHeadReq.bits.address := subMsgHeader.address
|
||||||
io.subMsgHeadReq.bits.operator := subMsgHeader.operator
|
io.subMsgHeadReq.bits.operator := subMsgHeader.operator
|
||||||
io.subMsgHeadReq.bits.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
|
io.subMsgHeadReq.bits.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
|
||||||
|
|
||||||
io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
|
io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
|
||||||
|
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
lengthCnt := 0.U
|
lengthCnt := 0.U
|
||||||
} .elsewhen( io.rec.fire ){
|
} .elsewhen( io.rec.fire ){
|
||||||
when( stateCurr =/= stateNext ){
|
when( stateCurr =/= stateNext ){
|
||||||
lengthCnt := 0.U
|
lengthCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
lengthCnt := lengthCnt + 1.U
|
lengthCnt := lengthCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( io.rec.fire ){
|
when( io.rec.fire ){
|
||||||
when( stateCurr === STATE_HEADER ){
|
when( stateCurr === STATE_HEADER ){
|
||||||
frameLenCnt := 0.U
|
frameLenCnt := 0.U
|
||||||
} .elsewhen(
|
} .elsewhen(
|
||||||
( stateCurr === STATE_SUBMSG_HEADER ) ||
|
( stateCurr === STATE_SUBMSG_HEADER ) ||
|
||||||
( stateCurr === STATE_PAYLOAD_DATA ) ||
|
( stateCurr === STATE_PAYLOAD_DATA ) ||
|
||||||
( stateCurr === STATE_SUBMSG_TAIL )
|
( stateCurr === STATE_SUBMSG_TAIL )
|
||||||
){
|
){
|
||||||
frameLenCnt := frameLenCnt + 1.U
|
frameLenCnt := frameLenCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
io.data.valid := io.rec.fire & stateCurr === STATE_PAYLOAD_DATA
|
io.data.valid := io.rec.fire & stateCurr === STATE_PAYLOAD_DATA
|
||||||
io.data.bits := io.rec.bits.tdata
|
io.data.bits := io.rec.bits.tdata
|
||||||
|
|
||||||
// assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
|
// assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
|
||||||
val isDataRejErr = io.data.valid & ~io.data.ready
|
val isDataRejErr = io.data.valid & ~io.data.ready
|
||||||
|
|
||||||
when( (io.data.valid & ~io.data.ready) ){
|
when( (io.data.valid & ~io.data.ready) ){
|
||||||
printf( "Error! Receive Data was rejected by fifo!\n")
|
printf( "Error! Receive Data was rejected by fifo!\n")
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( io.rec.fire ){
|
when( io.rec.fire ){
|
||||||
when( stateCurr === STATE_HEADER ){
|
when( stateCurr === STATE_HEADER ){
|
||||||
when( lengthCnt === 0.U ){
|
when( lengthCnt === 0.U ){
|
||||||
frameHeader.frameLenAim := io.rec.bits.tdata << 4
|
frameHeader.frameLenAim := io.rec.bits.tdata << 4
|
||||||
} .elsewhen( lengthCnt === 1.U ){
|
} .elsewhen( lengthCnt === 1.U ){
|
||||||
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
|
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
|
||||||
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
|
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
|
||||||
} .elsewhen( lengthCnt === 2.U ){
|
} .elsewhen( lengthCnt === 2.U ){
|
||||||
frameHeader.frameInfo := io.rec.bits.tdata << 8
|
frameHeader.frameInfo := io.rec.bits.tdata << 8
|
||||||
} .elsewhen( lengthCnt === 3.U ){
|
} .elsewhen( lengthCnt === 3.U ){
|
||||||
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
|
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( stateCurr === STATE_SUBMSG_HEADER ){
|
when( stateCurr === STATE_SUBMSG_HEADER ){
|
||||||
when(lengthCnt === 0.U ){
|
when(lengthCnt === 0.U ){
|
||||||
subMsgHeader.devIndex := io.rec.bits.tdata << 6
|
subMsgHeader.devIndex := io.rec.bits.tdata << 6
|
||||||
} .elsewhen( lengthCnt === 1.U ){
|
} .elsewhen( lengthCnt === 1.U ){
|
||||||
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
|
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
|
||||||
subMsgHeader.style := io.rec.bits.tdata(1,0)
|
subMsgHeader.style := io.rec.bits.tdata(1,0)
|
||||||
} .elsewhen( lengthCnt === 2.U ){
|
} .elsewhen( lengthCnt === 2.U ){
|
||||||
subMsgHeader.address := io.rec.bits.tdata << 8
|
subMsgHeader.address := io.rec.bits.tdata << 8
|
||||||
} .elsewhen( lengthCnt === 3.U ){
|
} .elsewhen( lengthCnt === 3.U ){
|
||||||
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
|
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
|
||||||
} .elsewhen( lengthCnt === 4.U ){
|
} .elsewhen( lengthCnt === 4.U ){
|
||||||
subMsgHeader.operator := io.rec.bits.tdata(7,4)
|
subMsgHeader.operator := io.rec.bits.tdata(7,4)
|
||||||
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
|
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
|
||||||
} .elsewhen( lengthCnt === 5.U ){
|
} .elsewhen( lengthCnt === 5.U ){
|
||||||
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
|
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( stateCurr === STATE_SUBMSG_TAIL ){
|
when( stateCurr === STATE_SUBMSG_TAIL ){
|
||||||
when(lengthCnt === 0.U ){
|
when(lengthCnt === 0.U ){
|
||||||
subMsgTail.workCnt := io.rec.bits.tdata << 8
|
subMsgTail.workCnt := io.rec.bits.tdata << 8
|
||||||
} .elsewhen( lengthCnt === 1.U ){
|
} .elsewhen( lengthCnt === 1.U ){
|
||||||
subMsgTail.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
|
subMsgTail.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
stateNext :=
|
stateNext :=
|
||||||
Mux( io.flush, STATE_IDLE,
|
Mux( io.flush, STATE_IDLE,
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
//必须使用上升沿触发，以避免前一帧长度超过预期
|
//必须使用上升沿触发，以避免前一帧长度超过预期
|
||||||
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid, false.B) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
|
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid, false.B) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
|
||||||
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
||||||
Mux( lengthCnt === (4-1).U,
|
Mux( lengthCnt === (4-1).U,
|
||||||
MuxCase( STATE_ERROR, Array(
|
MuxCase( STATE_ERROR, Array(
|
||||||
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
|
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
|
||||||
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
|
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
|
||||||
)), STATE_HEADER
|
)), STATE_HEADER
|
||||||
)), STATE_HEADER
|
)), STATE_HEADER
|
||||||
),
|
),
|
||||||
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
||||||
Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
|
Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
|
||||||
), STATE_SUBMSG_HEADER),
|
), STATE_SUBMSG_HEADER),
|
||||||
|
|
||||||
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
|
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
|
||||||
Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA )
|
Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA )
|
||||||
), STATE_PAYLOAD_DATA),
|
), STATE_PAYLOAD_DATA),
|
||||||
|
|
||||||
( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
||||||
Mux( lengthCnt === ( (2 - 1).U),
|
Mux( lengthCnt === ( (2 - 1).U),
|
||||||
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
|
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
|
||||||
),STATE_SUBMSG_TAIL )
|
),STATE_SUBMSG_TAIL )
|
||||||
), STATE_SUBMSG_TAIL),
|
), STATE_SUBMSG_TAIL),
|
||||||
|
|
||||||
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
|
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
|
||||||
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
|
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
|
||||||
),
|
),
|
||||||
( stateCurr === STATE_ERROR ) -> STATE_ERROR,
|
( stateCurr === STATE_ERROR ) -> STATE_ERROR,
|
||||||
))
|
))
|
||||||
)
|
)
|
||||||
|
|
||||||
io.stat.isHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_HEADER
|
io.stat.isHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_HEADER
|
||||||
io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER
|
io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER
|
||||||
io.stat.isPayloadError := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA
|
io.stat.isPayloadError := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA
|
||||||
io.stat.isSubTailError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_TAIL
|
io.stat.isSubTailError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_TAIL
|
||||||
io.stat.isCRCError := stateNext === STATE_ERROR & stateCurr === STATE_CRC
|
io.stat.isCRCError := stateNext === STATE_ERROR & stateCurr === STATE_CRC
|
||||||
io.stat.isFinish := stateNext === STATE_IDLE & stateCurr === STATE_CRC
|
io.stat.isFinish := stateNext === STATE_IDLE & stateCurr === STATE_CRC
|
||||||
io.stat.isRecByteAck := io.rec.fire
|
io.stat.isRecByteAck := io.rec.fire
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,190 +1,190 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
class SubMsgTxInfo extends SubMsgHeader{
|
class SubMsgTxInfo extends SubMsgHeader{
|
||||||
val source = UInt(2.W)
|
val source = UInt(2.W)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class SlaveSendGenIO extends Bundle{
|
class SlaveSendGenIO extends Bundle{
|
||||||
val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) )
|
val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) )
|
||||||
|
|
||||||
val frameReq = Flipped(Decoupled( new FrameHeader ))
|
val frameReq = Flipped(Decoupled( new FrameHeader ))
|
||||||
val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
|
val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
|
||||||
val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
|
val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
|
||||||
|
|
||||||
val send = Decoupled(new AXIS_Bundle(8))
|
val send = Decoupled(new AXIS_Bundle(8))
|
||||||
|
|
||||||
val stateCurr = Output(UInt(3.W))
|
val stateCurr = Output(UInt(3.W))
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class SlaveSendGen extends Module with RequireAsyncReset{
|
class SlaveSendGen extends Module with RequireAsyncReset{
|
||||||
val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
|
val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
|
||||||
|
|
||||||
val crc = Module(new crc32_8)
|
val crc = Module(new crc32_8)
|
||||||
|
|
||||||
val FRAME_STYLE_COMMON = 0.U
|
val FRAME_STYLE_COMMON = 0.U
|
||||||
val FRAME_STYLE_PROBE = 1.U
|
val FRAME_STYLE_PROBE = 1.U
|
||||||
|
|
||||||
val STATE_IDLE = 0.U //空闲
|
val STATE_IDLE = 0.U //空闲
|
||||||
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
|
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
|
||||||
val STATE_SUBMSG_HEADER = 2.U
|
val STATE_SUBMSG_HEADER = 2.U
|
||||||
val STATE_SUBMSG_DATA = 3.U
|
val STATE_SUBMSG_DATA = 3.U
|
||||||
val STATE_SUBMSG_TAIL = 4.U
|
val STATE_SUBMSG_TAIL = 4.U
|
||||||
val STATE_CRC = 5.U //CRC校验
|
val STATE_CRC = 5.U //CRC校验
|
||||||
val STATE_WAIT = 6.U
|
val STATE_WAIT = 6.U
|
||||||
|
|
||||||
|
|
||||||
val stateNext = Wire(UInt(3.W))
|
val stateNext = Wire(UInt(3.W))
|
||||||
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
|
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
|
||||||
|
|
||||||
crc.io.isEnable := io.send.fire & (
|
crc.io.isEnable := io.send.fire & (
|
||||||
stateCurr === STATE_FRAME_HEADER |
|
stateCurr === STATE_FRAME_HEADER |
|
||||||
stateCurr === STATE_SUBMSG_HEADER |
|
stateCurr === STATE_SUBMSG_HEADER |
|
||||||
stateCurr === STATE_SUBMSG_DATA |
|
stateCurr === STATE_SUBMSG_DATA |
|
||||||
stateCurr === STATE_SUBMSG_TAIL
|
stateCurr === STATE_SUBMSG_TAIL
|
||||||
)
|
)
|
||||||
crc.io.flush := stateCurr === STATE_IDLE | io.flush
|
crc.io.flush := stateCurr === STATE_IDLE | io.flush
|
||||||
|
|
||||||
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
|
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
|
||||||
|
|
||||||
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
|
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
|
||||||
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
|
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
|
||||||
|
|
||||||
when( io.frameReq.fire ){
|
when( io.frameReq.fire ){
|
||||||
frameInfo := io.frameReq.bits
|
frameInfo := io.frameReq.bits
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.subMsgHeadReq.fire ){
|
when( io.subMsgHeadReq.fire ){
|
||||||
subMsgHeadInfo := io.subMsgHeadReq.bits
|
subMsgHeadInfo := io.subMsgHeadReq.bits
|
||||||
}
|
}
|
||||||
|
|
||||||
when( io.subMsgTailReq.fire ){
|
when( io.subMsgTailReq.fire ){
|
||||||
subMsgTailInfo := io.subMsgTailReq.bits
|
subMsgTailInfo := io.subMsgTailReq.bits
|
||||||
}
|
}
|
||||||
|
|
||||||
val lengthCnt = RegInit(0.U(12.W))
|
val lengthCnt = RegInit(0.U(12.W))
|
||||||
val frameLenCnt = RegInit(0.U(12.W))
|
val frameLenCnt = RegInit(0.U(12.W))
|
||||||
|
|
||||||
when( io.send.fire ){
|
when( io.send.fire ){
|
||||||
when( stateCurr === STATE_FRAME_HEADER ){
|
when( stateCurr === STATE_FRAME_HEADER ){
|
||||||
frameLenCnt := 0.U
|
frameLenCnt := 0.U
|
||||||
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){
|
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){
|
||||||
frameLenCnt := frameLenCnt + 1.U
|
frameLenCnt := frameLenCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( stateCurr =/= stateNext ){
|
when( stateCurr =/= stateNext ){
|
||||||
lengthCnt := 0.U
|
lengthCnt := 0.U
|
||||||
} .elsewhen(io.send.fire){
|
} .elsewhen(io.send.fire){
|
||||||
lengthCnt := lengthCnt + 1.U
|
lengthCnt := lengthCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
io.frameReq.ready := true.B
|
io.frameReq.ready := true.B
|
||||||
io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
|
io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
|
||||||
io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL
|
io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL
|
||||||
assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) )
|
assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) )
|
||||||
|
|
||||||
|
|
||||||
stateNext :=
|
stateNext :=
|
||||||
Mux( io.flush, STATE_IDLE,
|
Mux( io.flush, STATE_IDLE,
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
|
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
|
||||||
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
|
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
|
||||||
frameInfo.frameStyle === FRAME_STYLE_COMMON,
|
frameInfo.frameStyle === FRAME_STYLE_COMMON,
|
||||||
Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
|
Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
|
||||||
STATE_CRC ),
|
STATE_CRC ),
|
||||||
STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
|
STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
|
||||||
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
|
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
|
||||||
|
|
||||||
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
|
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
|
||||||
Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
|
Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
|
||||||
STATE_SUBMSG_DATA ),
|
STATE_SUBMSG_DATA ),
|
||||||
|
|
||||||
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
|
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
|
||||||
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
|
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
|
||||||
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
|
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
|
||||||
Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
|
Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
|
||||||
STATE_SUBMSG_TAIL
|
STATE_SUBMSG_TAIL
|
||||||
), STATE_SUBMSG_TAIL ),
|
), STATE_SUBMSG_TAIL ),
|
||||||
|
|
||||||
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
|
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
|
||||||
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
|
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
|
||||||
))
|
))
|
||||||
)
|
)
|
||||||
|
|
||||||
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U)
|
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U)
|
||||||
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U)
|
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U)
|
||||||
|
|
||||||
assert( ~(io.data(0).ready & ~io.data(0).valid) )
|
assert( ~(io.data(0).ready & ~io.data(0).valid) )
|
||||||
assert( ~(io.data(1).ready & ~io.data(1).valid) )
|
assert( ~(io.data(1).ready & ~io.data(1).valid) )
|
||||||
|
|
||||||
|
|
||||||
io.send.valid :=
|
io.send.valid :=
|
||||||
(stateCurr === STATE_FRAME_HEADER) |
|
(stateCurr === STATE_FRAME_HEADER) |
|
||||||
(stateCurr === STATE_SUBMSG_HEADER) |
|
(stateCurr === STATE_SUBMSG_HEADER) |
|
||||||
(stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) |
|
(stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) |
|
||||||
(stateCurr === STATE_SUBMSG_TAIL) |
|
(stateCurr === STATE_SUBMSG_TAIL) |
|
||||||
(stateCurr === STATE_CRC)
|
(stateCurr === STATE_CRC)
|
||||||
|
|
||||||
val tdata_frame_header = Mux1H(Seq(
|
val tdata_frame_header = Mux1H(Seq(
|
||||||
(lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
|
(lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
|
||||||
(lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
|
(lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
|
||||||
(lengthCnt === 2.U) -> frameInfo.frameInfo(15,8),
|
(lengthCnt === 2.U) -> frameInfo.frameInfo(15,8),
|
||||||
(lengthCnt === 3.U) -> frameInfo.frameInfo( 7,0),
|
(lengthCnt === 3.U) -> frameInfo.frameInfo( 7,0),
|
||||||
))
|
))
|
||||||
|
|
||||||
val tdata_submsg_header = Mux1H(Seq(
|
val tdata_submsg_header = Mux1H(Seq(
|
||||||
(lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6),
|
(lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6),
|
||||||
(lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style),
|
(lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style),
|
||||||
(lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8),
|
(lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8),
|
||||||
(lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0),
|
(lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0),
|
||||||
(lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)),
|
(lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)),
|
||||||
(lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0),
|
(lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0),
|
||||||
))
|
))
|
||||||
|
|
||||||
val tdata_submsg_data = Mux1H(Seq(
|
val tdata_submsg_data = Mux1H(Seq(
|
||||||
(subMsgHeadInfo.source === 0.U) -> io.data(0).bits,
|
(subMsgHeadInfo.source === 0.U) -> io.data(0).bits,
|
||||||
(subMsgHeadInfo.source === 1.U) -> io.data(1).bits,
|
(subMsgHeadInfo.source === 1.U) -> io.data(1).bits,
|
||||||
))
|
))
|
||||||
|
|
||||||
val tdata_submsg_tail = Mux1H(Seq(
|
val tdata_submsg_tail = Mux1H(Seq(
|
||||||
(lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8),
|
(lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8),
|
||||||
(lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0),
|
(lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0),
|
||||||
))
|
))
|
||||||
|
|
||||||
crc.io.dataIn := Mux1H(Seq(
|
crc.io.dataIn := Mux1H(Seq(
|
||||||
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
|
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
|
||||||
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
|
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
|
||||||
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
|
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
|
||||||
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
|
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
|
||||||
))
|
))
|
||||||
|
|
||||||
|
|
||||||
val tdata_crc = Mux1H(Seq(
|
val tdata_crc = Mux1H(Seq(
|
||||||
(lengthCnt === 0.U) -> crc.io.crc(31,24),
|
(lengthCnt === 0.U) -> crc.io.crc(31,24),
|
||||||
(lengthCnt === 1.U) -> crc.io.crc(23,16),
|
(lengthCnt === 1.U) -> crc.io.crc(23,16),
|
||||||
(lengthCnt === 2.U) -> crc.io.crc(15, 8),
|
(lengthCnt === 2.U) -> crc.io.crc(15, 8),
|
||||||
(lengthCnt === 3.U) -> crc.io.crc( 7, 0),
|
(lengthCnt === 3.U) -> crc.io.crc( 7, 0),
|
||||||
))
|
))
|
||||||
|
|
||||||
io.send.bits.tdata := Mux1H(Seq(
|
io.send.bits.tdata := Mux1H(Seq(
|
||||||
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
|
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
|
||||||
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
|
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
|
||||||
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
|
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
|
||||||
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
|
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
|
||||||
(stateCurr === STATE_CRC) -> tdata_crc,
|
(stateCurr === STATE_CRC) -> tdata_crc,
|
||||||
))
|
))
|
||||||
|
|
||||||
io.send.bits.tuser := false.B
|
io.send.bits.tuser := false.B
|
||||||
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE)
|
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE)
|
||||||
|
|
||||||
}
|
}
|
||||||
@@ -1,239 +1,239 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class QSPIInterfaceIO extends Bundle{
|
class QSPIInterfaceIO extends Bundle{
|
||||||
val sck = Input(Bool())
|
val sck = Input(Bool())
|
||||||
val mosi = Input(UInt(4.W))
|
val mosi = Input(UInt(4.W))
|
||||||
val miso = Output(UInt(4.W))
|
val miso = Output(UInt(4.W))
|
||||||
val isDirIn = Output(Bool())
|
val isDirIn = Output(Bool())
|
||||||
val csn = Input(Bool())
|
val csn = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class SSPIInterfaceIO extends Bundle{
|
class SSPIInterfaceIO extends Bundle{
|
||||||
val sck = Input(Bool())
|
val sck = Input(Bool())
|
||||||
val mosi = Input(Bool())
|
val mosi = Input(Bool())
|
||||||
val miso = Output(Bool())
|
val miso = Output(Bool())
|
||||||
val csn = Input(Bool())
|
val csn = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
class RegAccessInterfaceIO extends Bundle{
|
class RegAccessInterfaceIO extends Bundle{
|
||||||
val addrw = Output(UInt(16.W))
|
val addrw = Output(UInt(16.W))
|
||||||
val addrr = Output(UInt(16.W))
|
val addrr = Output(UInt(16.W))
|
||||||
val dataw = Output( UInt(8.W) )
|
val dataw = Output( UInt(8.W) )
|
||||||
val datar = Input( UInt(8.W) )
|
val datar = Input( UInt(8.W) )
|
||||||
val isEnW = Output(Bool())
|
val isEnW = Output(Bool())
|
||||||
val isEnR = Output(Bool())
|
val isEnR = Output(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
|
abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
|
||||||
val io = IO(new RegAccessInterfaceIO)
|
val io = IO(new RegAccessInterfaceIO)
|
||||||
|
|
||||||
val sck = Wire(Bool())
|
val sck = Wire(Bool())
|
||||||
val csn = Wire(Bool())
|
val csn = Wire(Bool())
|
||||||
|
|
||||||
|
|
||||||
//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
|
//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
|
||||||
val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
|
val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
|
||||||
val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
|
val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
|
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
|
||||||
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
|
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
|
||||||
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
|
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
|
||||||
|
|
||||||
val exRego = RegInit(0.U(8.W))
|
val exRego = RegInit(0.U(8.W))
|
||||||
val exRegi = RegInit(0.U(8.W))
|
val exRegi = RegInit(0.U(8.W))
|
||||||
|
|
||||||
val addrw = RegInit(0.U(16.W))
|
val addrw = RegInit(0.U(16.W))
|
||||||
val addrr = RegInit(0.U(16.W))
|
val addrr = RegInit(0.U(16.W))
|
||||||
val spiCmd = RegInit(0.U(1.W))
|
val spiCmd = RegInit(0.U(1.W))
|
||||||
|
|
||||||
val isSpiWrite = spiCmd === 0.U
|
val isSpiWrite = spiCmd === 0.U
|
||||||
val isSpiRead = spiCmd === 1.U
|
val isSpiRead = spiCmd === 1.U
|
||||||
|
|
||||||
val bitSel = RegInit(0.U(3.W))
|
val bitSel = RegInit(0.U(3.W))
|
||||||
val bitSelNext = RegNext(bitSel, 0.U(3.W))
|
val bitSelNext = RegNext(bitSel, 0.U(3.W))
|
||||||
val byteSel = RegInit(0.U(12.W))
|
val byteSel = RegInit(0.U(12.W))
|
||||||
val byteSelNext = RegNext(byteSel, 0.U(12.W))
|
val byteSelNext = RegNext(byteSel, 0.U(12.W))
|
||||||
|
|
||||||
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
|
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
|
||||||
|
|
||||||
io.dataw := exRegi
|
io.dataw := exRegi
|
||||||
io.addrr := addrr
|
io.addrr := addrr
|
||||||
io.addrw := addrw
|
io.addrw := addrw
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){
|
when( shiftCSn(2) & ~shiftCSn(1) ){
|
||||||
byteSel := 0.U
|
byteSel := 0.U
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
||||||
when( bitSel.andR ){
|
when( bitSel.andR ){
|
||||||
byteSel := byteSel + 1.U
|
byteSel := byteSel + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class SSpiInterface extends SpiInterfaceBase{
|
class SSpiInterface extends SpiInterfaceBase{
|
||||||
val spi = IO(new SSPIInterfaceIO)
|
val spi = IO(new SSPIInterfaceIO)
|
||||||
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
|
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
|
||||||
|
|
||||||
sck := spi.sck
|
sck := spi.sck
|
||||||
csn := spi.csn
|
csn := spi.csn
|
||||||
|
|
||||||
io.isEnR :=
|
io.isEnR :=
|
||||||
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === 1.U & byteSel === 2.U ) |
|
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === 1.U & byteSel === 2.U ) |
|
||||||
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U )
|
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U )
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
|
when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
|
||||||
spiCmd := 0.U
|
spiCmd := 0.U
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
||||||
spiCmd := shiftMOSI(1)
|
spiCmd := shiftMOSI(1)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
spi.miso := exRego.extract(7)
|
spi.miso := exRego.extract(7)
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){
|
when( shiftCSn(2) & ~shiftCSn(1) ){
|
||||||
bitSel := 0.U
|
bitSel := 0.U
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
||||||
bitSel := bitSel + 1.U
|
bitSel := bitSel + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
//输入看SCK上升沿
|
//输入看SCK上升沿
|
||||||
when( isSckPosedge & ~shiftCSn(1) ){
|
when( isSckPosedge & ~shiftCSn(1) ){
|
||||||
when( bitSel === 0.U ){
|
when( bitSel === 0.U ){
|
||||||
exRegi := Cat( 0.U, shiftMOSI(1) )
|
exRegi := Cat( 0.U, shiftMOSI(1) )
|
||||||
}.otherwise{
|
}.otherwise{
|
||||||
exRegi := Cat( exRegi(6,0), shiftMOSI(1) )
|
exRegi := Cat( exRegi(6,0), shiftMOSI(1) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
//输出在SCK上升沿准备数据
|
//输出在SCK上升沿准备数据
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
exRego := 0.U //第一个byte 地址0
|
exRego := 0.U //第一个byte 地址0
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
||||||
when( bitSel.andR ){
|
when( bitSel.andR ){
|
||||||
when((byteSel === 0.U || byteSel === 1.U) ){
|
when((byteSel === 0.U || byteSel === 1.U) ){
|
||||||
exRego := 0.U //地址1，cmd
|
exRego := 0.U //地址1，cmd
|
||||||
} .elsewhen( isSpiRead ){
|
} .elsewhen( isSpiRead ){
|
||||||
exRego := io.datar
|
exRego := io.datar
|
||||||
}
|
}
|
||||||
}.otherwise{
|
}.otherwise{
|
||||||
exRego := exRego << 1
|
exRego := exRego << 1
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
addrr := 0.U
|
addrr := 0.U
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
||||||
addrr := Cat( exRegi(6,0), shiftMOSI(1) )
|
addrr := Cat( exRegi(6,0), shiftMOSI(1) )
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
||||||
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
|
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
|
||||||
} .otherwise{ // byteSel > 1.U
|
} .otherwise{ // byteSel > 1.U
|
||||||
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
|
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
|
||||||
addrr := addrr + 1.U
|
addrr := addrr + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
addrw := 0.U
|
addrw := 0.U
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
||||||
addrw := Cat( exRegi(6,0), shiftMOSI(1) )
|
addrw := Cat( exRegi(6,0), shiftMOSI(1) )
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
||||||
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI(1) )
|
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI(1) )
|
||||||
} .otherwise{ // byteSel > 1.U
|
} .otherwise{ // byteSel > 1.U
|
||||||
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
|
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
|
||||||
addrw := addrw + 1.U
|
addrw := addrw + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
|
class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
|
||||||
val qspi = IO(new QSPIInterfaceIO)
|
val qspi = IO(new QSPIInterfaceIO)
|
||||||
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
|
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
|
||||||
|
|
||||||
sck := qspi.sck
|
sck := qspi.sck
|
||||||
csn := qspi.csn
|
csn := qspi.csn
|
||||||
qspi.miso := exRego(7, 4)
|
qspi.miso := exRego(7, 4)
|
||||||
qspi.isDirIn := ~isSpiRead
|
qspi.isDirIn := ~isSpiRead
|
||||||
|
|
||||||
|
|
||||||
io.isEnR :=
|
io.isEnR :=
|
||||||
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
|
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
|
||||||
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
|
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
|
when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
|
||||||
spiCmd := 0.U
|
spiCmd := 0.U
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
|
||||||
spiCmd := shiftMOSI(1).extract(3)
|
spiCmd := shiftMOSI(1).extract(3)
|
||||||
}
|
}
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){
|
when( shiftCSn(2) & ~shiftCSn(1) ){
|
||||||
bitSel := 0.U
|
bitSel := 0.U
|
||||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
||||||
bitSel := ~bitSel
|
bitSel := ~bitSel
|
||||||
}
|
}
|
||||||
|
|
||||||
//输入看SCK上升沿
|
//输入看SCK上升沿
|
||||||
when( isSckPosedge & ~shiftCSn(1) ){
|
when( isSckPosedge & ~shiftCSn(1) ){
|
||||||
when( bitSel === 0.U ){
|
when( bitSel === 0.U ){
|
||||||
exRegi := Cat( 0.U, shiftMOSI(1) )
|
exRegi := Cat( 0.U, shiftMOSI(1) )
|
||||||
}.otherwise{
|
}.otherwise{
|
||||||
exRegi := Cat( exRegi(3,0), shiftMOSI(1) )
|
exRegi := Cat( exRegi(3,0), shiftMOSI(1) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
//输出在SCK XX沿准备数据
|
//输出在SCK XX沿准备数据
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
exRego := 0.U //第一个byte 地址0
|
exRego := 0.U //第一个byte 地址0
|
||||||
} .elsewhen(
|
} .elsewhen(
|
||||||
(if( edge ) {isSckPosedge} else {isSckNegedge})
|
(if( edge ) {isSckPosedge} else {isSckNegedge})
|
||||||
& ~shiftCSn(1)
|
& ~shiftCSn(1)
|
||||||
){
|
){
|
||||||
when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
|
when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
|
||||||
when( byteSel === 0.U || byteSel === 1.U || ( if( edge ) { false.B } else { byteSel === 2.U } ) ){
|
when( byteSel === 0.U || byteSel === 1.U || ( if( edge ) { false.B } else { byteSel === 2.U } ) ){
|
||||||
exRego := 0.U //地址1，cmd
|
exRego := 0.U //地址1，cmd
|
||||||
} .elsewhen( isSpiRead ){
|
} .elsewhen( isSpiRead ){
|
||||||
exRego := io.datar
|
exRego := io.datar
|
||||||
}
|
}
|
||||||
}.otherwise{
|
}.otherwise{
|
||||||
exRego := exRego << 4
|
exRego := exRego << 4
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
addrr := 0.U
|
addrr := 0.U
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
||||||
addrr := Cat( exRegi(3,0), shiftMOSI(1) )
|
addrr := Cat( exRegi(3,0), shiftMOSI(1) )
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
||||||
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
|
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
|
||||||
} .otherwise{ // byteSel > 1.U
|
} .otherwise{ // byteSel > 1.U
|
||||||
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
|
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
|
||||||
addrr := addrr + 1.U
|
addrr := addrr + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
|
||||||
addrw := 0.U
|
addrw := 0.U
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
|
||||||
addrw := Cat( exRegi(3,0), shiftMOSI(1) )
|
addrw := Cat( exRegi(3,0), shiftMOSI(1) )
|
||||||
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
|
||||||
addrw := Cat(addrw(7,0), exRegi(3,0), shiftMOSI(1) )
|
addrw := Cat(addrw(7,0), exRegi(3,0), shiftMOSI(1) )
|
||||||
} .otherwise{ // byteSel > 1.U
|
} .otherwise{ // byteSel > 1.U
|
||||||
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
|
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
|
||||||
addrw := addrw + 1.U
|
addrw := addrw + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,78 +1,78 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
object b4b5Encoder{
|
object b4b5Encoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(enq === "b0000".U) -> "b11110".U(5.W),
|
(enq === "b0000".U) -> "b11110".U(5.W),
|
||||||
(enq === "b0001".U) -> "b01001".U(5.W),
|
(enq === "b0001".U) -> "b01001".U(5.W),
|
||||||
(enq === "b0010".U) -> "b10100".U(5.W),
|
(enq === "b0010".U) -> "b10100".U(5.W),
|
||||||
(enq === "b0011".U) -> "b10101".U(5.W),
|
(enq === "b0011".U) -> "b10101".U(5.W),
|
||||||
(enq === "b0100".U) -> "b01010".U(5.W),
|
(enq === "b0100".U) -> "b01010".U(5.W),
|
||||||
(enq === "b0101".U) -> "b01011".U(5.W),
|
(enq === "b0101".U) -> "b01011".U(5.W),
|
||||||
(enq === "b0110".U) -> "b01110".U(5.W),
|
(enq === "b0110".U) -> "b01110".U(5.W),
|
||||||
(enq === "b0111".U) -> "b01111".U(5.W),
|
(enq === "b0111".U) -> "b01111".U(5.W),
|
||||||
(enq === "b1000".U) -> "b10010".U(5.W),
|
(enq === "b1000".U) -> "b10010".U(5.W),
|
||||||
(enq === "b1001".U) -> "b10011".U(5.W),
|
(enq === "b1001".U) -> "b10011".U(5.W),
|
||||||
(enq === "b1010".U) -> "b10110".U(5.W),
|
(enq === "b1010".U) -> "b10110".U(5.W),
|
||||||
(enq === "b1011".U) -> "b10111".U(5.W),
|
(enq === "b1011".U) -> "b10111".U(5.W),
|
||||||
(enq === "b1100".U) -> "b11010".U(5.W),
|
(enq === "b1100".U) -> "b11010".U(5.W),
|
||||||
(enq === "b1101".U) -> "b11011".U(5.W),
|
(enq === "b1101".U) -> "b11011".U(5.W),
|
||||||
(enq === "b1110".U) -> "b11100".U(5.W),
|
(enq === "b1110".U) -> "b11100".U(5.W),
|
||||||
(enq === "b1111".U) -> "b11101".U(5.W),
|
(enq === "b1111".U) -> "b11101".U(5.W),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object b4b5Decoder{
|
object b4b5Decoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(enq === "b11110".U) -> "b0000".U(4.W),
|
(enq === "b11110".U) -> "b0000".U(4.W),
|
||||||
(enq === "b01001".U) -> "b0001".U(4.W),
|
(enq === "b01001".U) -> "b0001".U(4.W),
|
||||||
(enq === "b10100".U) -> "b0010".U(4.W),
|
(enq === "b10100".U) -> "b0010".U(4.W),
|
||||||
(enq === "b10101".U) -> "b0011".U(4.W),
|
(enq === "b10101".U) -> "b0011".U(4.W),
|
||||||
(enq === "b01010".U) -> "b0100".U(4.W),
|
(enq === "b01010".U) -> "b0100".U(4.W),
|
||||||
(enq === "b01011".U) -> "b0101".U(4.W),
|
(enq === "b01011".U) -> "b0101".U(4.W),
|
||||||
(enq === "b01110".U) -> "b0110".U(4.W),
|
(enq === "b01110".U) -> "b0110".U(4.W),
|
||||||
(enq === "b01111".U) -> "b0111".U(4.W),
|
(enq === "b01111".U) -> "b0111".U(4.W),
|
||||||
(enq === "b10010".U) -> "b1000".U(4.W),
|
(enq === "b10010".U) -> "b1000".U(4.W),
|
||||||
(enq === "b10011".U) -> "b1001".U(4.W),
|
(enq === "b10011".U) -> "b1001".U(4.W),
|
||||||
(enq === "b10110".U) -> "b1010".U(4.W),
|
(enq === "b10110".U) -> "b1010".U(4.W),
|
||||||
(enq === "b10111".U) -> "b1011".U(4.W),
|
(enq === "b10111".U) -> "b1011".U(4.W),
|
||||||
(enq === "b11010".U) -> "b1100".U(4.W),
|
(enq === "b11010".U) -> "b1100".U(4.W),
|
||||||
(enq === "b11011".U) -> "b1101".U(4.W),
|
(enq === "b11011".U) -> "b1101".U(4.W),
|
||||||
(enq === "b11100".U) -> "b1110".U(4.W),
|
(enq === "b11100".U) -> "b1110".U(4.W),
|
||||||
(enq === "b11101".U) -> "b1111".U(4.W),
|
(enq === "b11101".U) -> "b1111".U(4.W),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object Dualb4b5Encoder{
|
object Dualb4b5Encoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" )
|
require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" )
|
||||||
Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) )
|
Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object Dualb4b5Decoder{
|
object Dualb4b5Decoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" )
|
require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" )
|
||||||
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
|
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class b4b5DualEncode extends Module with RequireAsyncReset{
|
class b4b5DualEncode extends Module with RequireAsyncReset{
|
||||||
val io = IO(new Encode_Bundle)
|
val io = IO(new Encode_Bundle)
|
||||||
|
|
||||||
io.dataOut := Dualb4b5Encoder(io.dataIn)
|
io.dataOut := Dualb4b5Encoder(io.dataIn)
|
||||||
}
|
}
|
||||||
|
|
||||||
class b4b5DualDecode extends Module with RequireAsyncReset{
|
class b4b5DualDecode extends Module with RequireAsyncReset{
|
||||||
val io = IO(new Decode_Bundle)
|
val io = IO(new Decode_Bundle)
|
||||||
|
|
||||||
io.dataOut := Dualb4b5Decoder(io.dataIn)
|
io.dataOut := Dualb4b5Decoder(io.dataIn)
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1,192 +1,192 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class Encode_Bundle extends Bundle{
|
class Encode_Bundle extends Bundle{
|
||||||
val dataIn = Input(UInt(8.W))
|
val dataIn = Input(UInt(8.W))
|
||||||
val isEnable = Input(Bool())
|
val isEnable = Input(Bool())
|
||||||
val dataOut = Output(UInt(10.W))
|
val dataOut = Output(UInt(10.W))
|
||||||
}
|
}
|
||||||
|
|
||||||
class Decode_Bundle extends Bundle{
|
class Decode_Bundle extends Bundle{
|
||||||
val dataIn = Input(UInt(10.W))
|
val dataIn = Input(UInt(10.W))
|
||||||
val dataOut = Output(UInt(8.W))
|
val dataOut = Output(UInt(8.W))
|
||||||
}
|
}
|
||||||
|
|
||||||
class b8b10Encode extends Module with RequireAsyncReset{
|
class b8b10Encode extends Module with RequireAsyncReset{
|
||||||
val io = IO(new Encode_Bundle)
|
val io = IO(new Encode_Bundle)
|
||||||
|
|
||||||
val rdTest = IO(Output(Bool())) //测试使用
|
val rdTest = IO(Output(Bool())) //测试使用
|
||||||
dontTouch(rdTest)
|
dontTouch(rdTest)
|
||||||
val rd = RegInit(false.B); rdTest := rd
|
val rd = RegInit(false.B); rdTest := rd
|
||||||
|
|
||||||
|
|
||||||
val b5b6LookUp = Mux1H(Seq(
|
val b5b6LookUp = Mux1H(Seq(
|
||||||
(io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
|
(io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
|
(io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
|
(io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
|
(io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
|
||||||
(io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
|
(io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
|
(io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
|
||||||
(io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
|
(io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
|
||||||
(io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
|
(io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
|
(io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
|
(io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
|
(io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
|
(io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
|
(io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
|
(io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
|
(io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
|
||||||
(io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
|
(io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
|
(io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
|
(io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
|
(io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
|
(io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
|
(io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
|
(io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
|
(io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
|
||||||
(io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
|
(io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
|
(io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
|
(io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
|
||||||
(io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
|
(io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
|
||||||
(io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
|
(io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
|
(io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
|
||||||
(io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
|
(io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
|
(io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
|
||||||
(io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
|
(io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
|
||||||
))
|
))
|
||||||
|
|
||||||
|
|
||||||
val b5b6RD = Mux1H(Seq(
|
val b5b6RD = Mux1H(Seq(
|
||||||
(io.dataIn(4,0) === "b00000".U) -> ~rd,
|
(io.dataIn(4,0) === "b00000".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b00001".U) -> ~rd,
|
(io.dataIn(4,0) === "b00001".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b00010".U) -> ~rd,
|
(io.dataIn(4,0) === "b00010".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b00011".U) -> rd,
|
(io.dataIn(4,0) === "b00011".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b00100".U) -> ~rd,
|
(io.dataIn(4,0) === "b00100".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b00101".U) -> rd,
|
(io.dataIn(4,0) === "b00101".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b00110".U) -> rd,
|
(io.dataIn(4,0) === "b00110".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b00111".U) -> rd,
|
(io.dataIn(4,0) === "b00111".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01000".U) -> ~rd,
|
(io.dataIn(4,0) === "b01000".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b01001".U) -> rd,
|
(io.dataIn(4,0) === "b01001".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01010".U) -> rd,
|
(io.dataIn(4,0) === "b01010".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01011".U) -> rd,
|
(io.dataIn(4,0) === "b01011".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01100".U) -> rd,
|
(io.dataIn(4,0) === "b01100".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01101".U) -> rd,
|
(io.dataIn(4,0) === "b01101".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01110".U) -> rd,
|
(io.dataIn(4,0) === "b01110".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b01111".U) -> ~rd,
|
(io.dataIn(4,0) === "b01111".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b10000".U) -> ~rd,
|
(io.dataIn(4,0) === "b10000".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b10001".U) -> rd,
|
(io.dataIn(4,0) === "b10001".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10010".U) -> rd,
|
(io.dataIn(4,0) === "b10010".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10011".U) -> rd,
|
(io.dataIn(4,0) === "b10011".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10100".U) -> rd,
|
(io.dataIn(4,0) === "b10100".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10101".U) -> rd,
|
(io.dataIn(4,0) === "b10101".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10110".U) -> rd,
|
(io.dataIn(4,0) === "b10110".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b10111".U) -> ~rd,
|
(io.dataIn(4,0) === "b10111".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b11000".U) -> ~rd,
|
(io.dataIn(4,0) === "b11000".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b11001".U) -> rd,
|
(io.dataIn(4,0) === "b11001".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b11010".U) -> rd,
|
(io.dataIn(4,0) === "b11010".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b11011".U) -> ~rd,
|
(io.dataIn(4,0) === "b11011".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b11100".U) -> rd,
|
(io.dataIn(4,0) === "b11100".U) -> rd,
|
||||||
(io.dataIn(4,0) === "b11101".U) -> ~rd,
|
(io.dataIn(4,0) === "b11101".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b11110".U) -> ~rd,
|
(io.dataIn(4,0) === "b11110".U) -> ~rd,
|
||||||
(io.dataIn(4,0) === "b11111".U) -> ~rd,
|
(io.dataIn(4,0) === "b11111".U) -> ~rd,
|
||||||
))
|
))
|
||||||
|
|
||||||
val b3b4LookUp = Mux1H(Seq(
|
val b3b4LookUp = Mux1H(Seq(
|
||||||
(io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
|
(io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
|
||||||
(io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
|
(io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
|
||||||
(io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
|
(io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
|
||||||
(io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
|
(io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
|
||||||
(io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
|
(io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
|
||||||
(io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
|
(io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
|
||||||
(io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
|
(io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
|
||||||
(io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
|
(io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
|
||||||
((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases
|
((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases
|
||||||
((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases
|
((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases
|
||||||
))
|
))
|
||||||
))
|
))
|
||||||
|
|
||||||
val b3b4RD = Mux1H(Seq(
|
val b3b4RD = Mux1H(Seq(
|
||||||
(io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
|
(io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
|
||||||
(io.dataIn(7,5) === "b001".U) -> b5b6RD,
|
(io.dataIn(7,5) === "b001".U) -> b5b6RD,
|
||||||
(io.dataIn(7,5) === "b010".U) -> b5b6RD,
|
(io.dataIn(7,5) === "b010".U) -> b5b6RD,
|
||||||
(io.dataIn(7,5) === "b011".U) -> b5b6RD,
|
(io.dataIn(7,5) === "b011".U) -> b5b6RD,
|
||||||
(io.dataIn(7,5) === "b100".U) -> ~b5b6RD,
|
(io.dataIn(7,5) === "b100".U) -> ~b5b6RD,
|
||||||
(io.dataIn(7,5) === "b101".U) -> b5b6RD,
|
(io.dataIn(7,5) === "b101".U) -> b5b6RD,
|
||||||
(io.dataIn(7,5) === "b110".U) -> b5b6RD,
|
(io.dataIn(7,5) === "b110".U) -> b5b6RD,
|
||||||
(io.dataIn(7,5) === "b111".U) -> ~b5b6RD,
|
(io.dataIn(7,5) === "b111".U) -> ~b5b6RD,
|
||||||
))
|
))
|
||||||
|
|
||||||
io.dataOut := Cat(b5b6LookUp, b3b4LookUp)
|
io.dataOut := Cat(b5b6LookUp, b3b4LookUp)
|
||||||
|
|
||||||
when (io.isEnable) {
|
when (io.isEnable) {
|
||||||
rd := b3b4RD
|
rd := b3b4RD
|
||||||
assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!")
|
assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!")
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class b8b10Decode extends Module with RequireAsyncReset{
|
class b8b10Decode extends Module with RequireAsyncReset{
|
||||||
val io = IO(new Decode_Bundle)
|
val io = IO(new Decode_Bundle)
|
||||||
|
|
||||||
|
|
||||||
val b5b6LookUp = Mux1H(Seq(
|
val b5b6LookUp = Mux1H(Seq(
|
||||||
(io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U,
|
(io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U,
|
||||||
(io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U,
|
(io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U,
|
||||||
(io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U,
|
(io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U,
|
||||||
(io.dataIn(9,4) === "b110001".U(6.W)) -> "b00011".U,
|
(io.dataIn(9,4) === "b110001".U(6.W)) -> "b00011".U,
|
||||||
(io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U,
|
(io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U,
|
||||||
(io.dataIn(9,4) === "b101001".U(6.W)) -> "b00101".U,
|
(io.dataIn(9,4) === "b101001".U(6.W)) -> "b00101".U,
|
||||||
(io.dataIn(9,4) === "b011001".U(6.W)) -> "b00110".U,
|
(io.dataIn(9,4) === "b011001".U(6.W)) -> "b00110".U,
|
||||||
(io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U,
|
(io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U,
|
||||||
(io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U,
|
(io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U,
|
||||||
(io.dataIn(9,4) === "b100101".U(6.W)) -> "b01001".U,
|
(io.dataIn(9,4) === "b100101".U(6.W)) -> "b01001".U,
|
||||||
(io.dataIn(9,4) === "b010101".U(6.W)) -> "b01010".U,
|
(io.dataIn(9,4) === "b010101".U(6.W)) -> "b01010".U,
|
||||||
(io.dataIn(9,4) === "b110100".U(6.W)) -> "b01011".U,
|
(io.dataIn(9,4) === "b110100".U(6.W)) -> "b01011".U,
|
||||||
(io.dataIn(9,4) === "b001101".U(6.W)) -> "b01100".U,
|
(io.dataIn(9,4) === "b001101".U(6.W)) -> "b01100".U,
|
||||||
(io.dataIn(9,4) === "b101100".U(6.W)) -> "b01101".U,
|
(io.dataIn(9,4) === "b101100".U(6.W)) -> "b01101".U,
|
||||||
(io.dataIn(9,4) === "b011100".U(6.W)) -> "b01110".U,
|
(io.dataIn(9,4) === "b011100".U(6.W)) -> "b01110".U,
|
||||||
(io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U,
|
(io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U,
|
||||||
(io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U,
|
(io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U,
|
||||||
(io.dataIn(9,4) === "b100011".U(6.W)) -> "b10001".U,
|
(io.dataIn(9,4) === "b100011".U(6.W)) -> "b10001".U,
|
||||||
(io.dataIn(9,4) === "b010011".U(6.W)) -> "b10010".U,
|
(io.dataIn(9,4) === "b010011".U(6.W)) -> "b10010".U,
|
||||||
(io.dataIn(9,4) === "b110010".U(6.W)) -> "b10011".U,
|
(io.dataIn(9,4) === "b110010".U(6.W)) -> "b10011".U,
|
||||||
(io.dataIn(9,4) === "b001011".U(6.W)) -> "b10100".U,
|
(io.dataIn(9,4) === "b001011".U(6.W)) -> "b10100".U,
|
||||||
(io.dataIn(9,4) === "b101010".U(6.W)) -> "b10101".U,
|
(io.dataIn(9,4) === "b101010".U(6.W)) -> "b10101".U,
|
||||||
(io.dataIn(9,4) === "b011010".U(6.W)) -> "b10110".U,
|
(io.dataIn(9,4) === "b011010".U(6.W)) -> "b10110".U,
|
||||||
(io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U,
|
(io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U,
|
||||||
(io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U,
|
(io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U,
|
||||||
(io.dataIn(9,4) === "b100110".U(6.W)) -> "b11001".U,
|
(io.dataIn(9,4) === "b100110".U(6.W)) -> "b11001".U,
|
||||||
(io.dataIn(9,4) === "b010110".U(6.W)) -> "b11010".U,
|
(io.dataIn(9,4) === "b010110".U(6.W)) -> "b11010".U,
|
||||||
(io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U,
|
(io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U,
|
||||||
(io.dataIn(9,4) === "b001110".U(6.W)) -> "b11100".U,
|
(io.dataIn(9,4) === "b001110".U(6.W)) -> "b11100".U,
|
||||||
(io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U,
|
(io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U,
|
||||||
(io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U,
|
(io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U,
|
||||||
(io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U,
|
(io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U,
|
||||||
))
|
))
|
||||||
|
|
||||||
val b3b4LookUp = Mux1H(Seq(
|
val b3b4LookUp = Mux1H(Seq(
|
||||||
(io.dataIn(3,0) === "b1011".U(4.W) || io.dataIn(3,0) === "b0100".U(4.W) ) -> "b000".U,
|
(io.dataIn(3,0) === "b1011".U(4.W) || io.dataIn(3,0) === "b0100".U(4.W) ) -> "b000".U,
|
||||||
(io.dataIn(3,0) === "b1001".U(4.W)) -> "b001".U,
|
(io.dataIn(3,0) === "b1001".U(4.W)) -> "b001".U,
|
||||||
(io.dataIn(3,0) === "b0101".U(4.W)) -> "b010".U,
|
(io.dataIn(3,0) === "b0101".U(4.W)) -> "b010".U,
|
||||||
(io.dataIn(3,0) === "b1100".U(4.W) || io.dataIn(3,0) === "b0011".U(4.W) ) -> "b011".U,
|
(io.dataIn(3,0) === "b1100".U(4.W) || io.dataIn(3,0) === "b0011".U(4.W) ) -> "b011".U,
|
||||||
(io.dataIn(3,0) === "b1101".U(4.W) || io.dataIn(3,0) === "b0010".U(4.W) ) -> "b100".U,
|
(io.dataIn(3,0) === "b1101".U(4.W) || io.dataIn(3,0) === "b0010".U(4.W) ) -> "b100".U,
|
||||||
(io.dataIn(3,0) === "b1010".U(4.W)) -> "b101".U,
|
(io.dataIn(3,0) === "b1010".U(4.W)) -> "b101".U,
|
||||||
(io.dataIn(3,0) === "b0110".U(4.W)) -> "b110".U,
|
(io.dataIn(3,0) === "b0110".U(4.W)) -> "b110".U,
|
||||||
(io.dataIn(3,0) === "b1110".U(4.W) ||
|
(io.dataIn(3,0) === "b1110".U(4.W) ||
|
||||||
io.dataIn(3,0) === "b0001".U(4.W) ||
|
io.dataIn(3,0) === "b0001".U(4.W) ||
|
||||||
io.dataIn(3,0) === "b0111".U(4.W) ||
|
io.dataIn(3,0) === "b0111".U(4.W) ||
|
||||||
io.dataIn(3,0) === "b1000".U(4.W)) -> "b111".U,
|
io.dataIn(3,0) === "b1000".U(4.W)) -> "b111".U,
|
||||||
))
|
))
|
||||||
|
|
||||||
io.dataOut := Cat(b3b4LookUp, b5b6LookUp)
|
io.dataOut := Cat(b3b4LookUp, b5b6LookUp)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1,87 +1,87 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
||||||
// Copyright (C) 2009 OutputLogic.com
|
// Copyright (C) 2009 OutputLogic.com
|
||||||
// This source file may be used and distributed without restriction
|
// This source file may be used and distributed without restriction
|
||||||
// provided that this copyright statement is not removed from the file
|
// provided that this copyright statement is not removed from the file
|
||||||
// and that any derivative work contains the original copyright notice
|
// and that any derivative work contains the original copyright notice
|
||||||
// and the associated disclaimer.
|
// and the associated disclaimer.
|
||||||
//
|
//
|
||||||
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
|
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
|
||||||
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
||||||
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||||
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
||||||
// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
|
// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
|
||||||
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
class crc32_8() extends Module with RequireAsyncReset{
|
class crc32_8() extends Module with RequireAsyncReset{
|
||||||
class crc32IO_Bundle extends Bundle{
|
class crc32IO_Bundle extends Bundle{
|
||||||
val isEnable = Input(Bool())
|
val isEnable = Input(Bool())
|
||||||
val dataIn = Input(UInt(8.W))
|
val dataIn = Input(UInt(8.W))
|
||||||
|
|
||||||
val crc = Output(UInt(32.W))
|
val crc = Output(UInt(32.W))
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
}
|
}
|
||||||
|
|
||||||
val io = IO( new crc32IO_Bundle )
|
val io = IO( new crc32IO_Bundle )
|
||||||
|
|
||||||
// val LFSR_POLY = "h4c11db7".U
|
// val LFSR_POLY = "h4c11db7".U
|
||||||
|
|
||||||
val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
|
val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
|
||||||
val lfsr_q = for( i <- 0 until 32 ) yield RegInit( true.B )
|
val lfsr_q = for( i <- 0 until 32 ) yield RegInit( true.B )
|
||||||
|
|
||||||
for( i <- 0 until 32 ){
|
for( i <- 0 until 32 ){
|
||||||
when( io.flush ){
|
when( io.flush ){
|
||||||
lfsr_q(i) := true.B
|
lfsr_q(i) := true.B
|
||||||
} .elsewhen( io.isEnable ){
|
} .elsewhen( io.isEnable ){
|
||||||
lfsr_q(i) := lfsr_c(i)
|
lfsr_q(i) := lfsr_c(i)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
io.crc := Cat( lfsr_q )
|
io.crc := Cat( lfsr_q )
|
||||||
|
|
||||||
val dataIn = Wire(UInt(8.W))
|
val dataIn = Wire(UInt(8.W))
|
||||||
dataIn := Cat(io.dataIn.asBools)
|
dataIn := Cat(io.dataIn.asBools)
|
||||||
|
|
||||||
|
|
||||||
lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(6)
|
lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(6)
|
||||||
lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(7)
|
lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(7)
|
||||||
lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
|
lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
|
||||||
lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(7)
|
lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(7)
|
||||||
lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
|
lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
|
||||||
lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5)
|
lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5)
|
||||||
lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5)
|
lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5)
|
||||||
lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
|
lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
|
||||||
lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6)
|
lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6)
|
||||||
lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
|
lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
|
||||||
lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(4) ^ dataIn(5)
|
lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(4) ^ dataIn(5)
|
||||||
lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(1) ^ dataIn(5) ^ dataIn(6)
|
lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(1) ^ dataIn(5) ^ dataIn(6)
|
||||||
lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(7)
|
lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(7)
|
||||||
lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ dataIn(4)
|
lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ dataIn(4)
|
||||||
lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ dataIn(5)
|
lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ dataIn(5)
|
||||||
lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ dataIn(0)
|
lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ dataIn(0)
|
||||||
lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6)
|
lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6)
|
||||||
lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(7)
|
lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(7)
|
||||||
lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ dataIn(2) ^ dataIn(3)
|
lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ dataIn(2) ^ dataIn(3)
|
||||||
lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
|
lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
|
||||||
lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
|
lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
|
||||||
lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(2) ^ dataIn(5) ^ dataIn(6)
|
lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(2) ^ dataIn(5) ^ dataIn(6)
|
||||||
lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(6) ^ dataIn(7)
|
lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(6) ^ dataIn(7)
|
||||||
lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ dataIn(4) ^ dataIn(7)
|
lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ dataIn(4) ^ dataIn(7)
|
||||||
lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ dataIn(5)
|
lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ dataIn(5)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1,83 +1,83 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
class FDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean){
|
class FDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean){
|
||||||
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
|
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
|
||||||
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
|
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
|
||||||
|
|
||||||
val value: T =
|
val value: T =
|
||||||
if( !mode ){ pReg }
|
if( !mode ){ pReg }
|
||||||
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
||||||
|
|
||||||
|
|
||||||
private val next = WireDefault(value)
|
private val next = WireDefault(value)
|
||||||
|
|
||||||
def :=(d:T): Unit = { next := d }
|
def :=(d:T): Unit = { next := d }
|
||||||
|
|
||||||
if( !mode ){ pReg := next } else { pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init) }
|
if( !mode ){ pReg := next } else { pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init) }
|
||||||
nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init)
|
nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init)
|
||||||
|
|
||||||
def apply(): T = value
|
def apply(): T = value
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
object FDRegInit{
|
object FDRegInit{
|
||||||
def apply[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean): FDRegInit[T] = {
|
def apply[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean): FDRegInit[T] = {
|
||||||
new FDRegInit(init, pclk, nclk, reset, mode)
|
new FDRegInit(init, pclk, nclk, reset, mode)
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class FDRegNext[T<:Data](d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
|
class FDRegNext[T<:Data](d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
|
||||||
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
|
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
|
||||||
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
|
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
|
||||||
|
|
||||||
if( !mode ) { pReg := d } else { pReg := (d.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
if( !mode ) { pReg := d } else { pReg := (d.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
||||||
nReg := (d.asUInt ^ pReg.asUInt).asTypeOf(init)
|
nReg := (d.asUInt ^ pReg.asUInt).asTypeOf(init)
|
||||||
|
|
||||||
val value: T =
|
val value: T =
|
||||||
if( !mode ){ pReg }
|
if( !mode ){ pReg }
|
||||||
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
|
||||||
|
|
||||||
def apply(): T = value
|
def apply(): T = value
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
object FDRegNext{
|
object FDRegNext{
|
||||||
def apply[T<:Data]( d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): T = {
|
def apply[T<:Data]( d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): T = {
|
||||||
new FDRegNext(d, init, pclk, nclk, reset, mode ).apply()
|
new FDRegNext(d, init, pclk, nclk, reset, mode ).apply()
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
class FDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
|
class FDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
|
||||||
private val pRegs = withClockAndReset(pclk, reset) { RegInit(VecInit(Seq.fill(n)( init ))) }
|
private val pRegs = withClockAndReset(pclk, reset) { RegInit(VecInit(Seq.fill(n)( init ))) }
|
||||||
private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) }
|
private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) }
|
||||||
|
|
||||||
// 移位逻辑：首位采样输入，其他依次移位
|
// 移位逻辑：首位采样输入，其他依次移位
|
||||||
if( !mode ){ pRegs(0) := in } else { pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) }
|
if( !mode ){ pRegs(0) := in } else { pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) }
|
||||||
for(i <- 1 until n) {
|
for(i <- 1 until n) {
|
||||||
if( !mode ){ pRegs(i) := pRegs(i-1) }
|
if( !mode ){ pRegs(i) := pRegs(i-1) }
|
||||||
else { pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)}
|
else { pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)}
|
||||||
}
|
}
|
||||||
|
|
||||||
nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
|
nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
|
||||||
for(i <- 1 until n) {
|
for(i <- 1 until n) {
|
||||||
nRegs(i) := (nRegs(i-1).asUInt ^ pRegs(i).asUInt).asTypeOf(init)
|
nRegs(i) := (nRegs(i-1).asUInt ^ pRegs(i).asUInt).asTypeOf(init)
|
||||||
}
|
}
|
||||||
|
|
||||||
// 输出为 pRegs 与 nRegs 异或
|
// 输出为 pRegs 与 nRegs 异或
|
||||||
def apply(): Seq[T] =
|
def apply(): Seq[T] =
|
||||||
if( !mode ){ pRegs }
|
if( !mode ){ pRegs }
|
||||||
else (pRegs zip nRegs).map{ case (a, b) => (a.asUInt ^ b.asUInt).asTypeOf(init) }
|
else (pRegs zip nRegs).map{ case (a, b) => (a.asUInt ^ b.asUInt).asTypeOf(init) }
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
object FDShiftRegisters{
|
object FDShiftRegisters{
|
||||||
def apply[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): Seq[T] = {
|
def apply[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): Seq[T] = {
|
||||||
new FDShiftRegisters( in, n, init, en, pclk, nclk, reset, mode ).apply()
|
new FDShiftRegisters( in, n, init, en, pclk, nclk, reset, mode ).apply()
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -1,170 +1,170 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class SimCDR extends Module with RequireAsyncReset{
|
class SimCDR extends Module with RequireAsyncReset{
|
||||||
val io = IO(new Bundle{
|
val io = IO(new Bundle{
|
||||||
val data = Input( UInt(8.W) )
|
val data = Input( UInt(8.W) )
|
||||||
|
|
||||||
val multiCLK = Input(Vec(16, Bool()))
|
val multiCLK = Input(Vec(16, Bool()))
|
||||||
|
|
||||||
val flush = Input(Bool())
|
val flush = Input(Bool())
|
||||||
|
|
||||||
val isSuccess = Output(Bool())
|
val isSuccess = Output(Bool())
|
||||||
val isFailed = Output(Bool())
|
val isFailed = Output(Bool())
|
||||||
})
|
})
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val cdrInAxis = Module(new CDRInAxis)
|
val cdrInAxis = Module(new CDRInAxis)
|
||||||
val cdrInSample = Module(new CDRInMultiSample(clkNum = 4))
|
val cdrInSample = Module(new CDRInMultiSample(clkNum = 4))
|
||||||
|
|
||||||
val cdrOut = Module(new CDROut)
|
val cdrOut = Module(new CDROut)
|
||||||
|
|
||||||
val dataCnt = RegInit(0.U(12.W))
|
val dataCnt = RegInit(0.U(12.W))
|
||||||
val payloadLen = RegInit(("hFFF".U)(12.W))
|
val payloadLen = RegInit(("hFFF".U)(12.W))
|
||||||
|
|
||||||
val b4b5Encoder = Module(new b4b5DualEncode)
|
val b4b5Encoder = Module(new b4b5DualEncode)
|
||||||
val b4b5Decoder = Module(new b4b5DualDecode)
|
val b4b5Decoder = Module(new b4b5DualDecode)
|
||||||
|
|
||||||
val b8b10Encoder = Module(new b8b10Encode)
|
val b8b10Encoder = Module(new b8b10Encode)
|
||||||
val b8b10Decoder = Module(new b8b10Decode)
|
val b8b10Decoder = Module(new b8b10Decode)
|
||||||
|
|
||||||
val wPtr = RegInit(0.U(12.W))
|
val wPtr = RegInit(0.U(12.W))
|
||||||
val rPtr = withClockAndReset( io.multiCLK(0).asClock, reset ) { RegInit(0.U(12.W)) }
|
val rPtr = withClockAndReset( io.multiCLK(0).asClock, reset ) { RegInit(0.U(12.W)) }
|
||||||
|
|
||||||
val asyncFifo = Module(new ShareSRAM2k)
|
val asyncFifo = Module(new ShareSRAM2k)
|
||||||
|
|
||||||
when( cdrOut.io.axis.fire & dataCnt === 0.U ){
|
when( cdrOut.io.axis.fire & dataCnt === 0.U ){
|
||||||
payloadLen := Cat( io.data, 0.U(4.W) )
|
payloadLen := Cat( io.data, 0.U(4.W) )
|
||||||
} .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
|
} .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
|
||||||
payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
|
payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( cdrOut.io.axis.fire ){
|
when( cdrOut.io.axis.fire ){
|
||||||
when( dataCnt >= payloadLen - 1.U ){
|
when( dataCnt >= payloadLen - 1.U ){
|
||||||
dataCnt := 0.U
|
dataCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
dataCnt := dataCnt + 1.U
|
dataCnt := dataCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
cdrOut.io.flush := io.flush
|
cdrOut.io.flush := io.flush
|
||||||
|
|
||||||
cdrInAxis.clock := io.multiCLK(0).asClock
|
cdrInAxis.clock := io.multiCLK(0).asClock
|
||||||
cdrInSample.clock := io.multiCLK(0).asClock
|
cdrInSample.clock := io.multiCLK(0).asClock
|
||||||
cdrInAxis.io.flush := io.flush
|
cdrInAxis.io.flush := io.flush
|
||||||
|
|
||||||
// cdrInSample.multiCLK := io.multiCLK
|
// cdrInSample.multiCLK := io.multiCLK
|
||||||
cdrInSample.multiCLK(0) := io.multiCLK(0)
|
cdrInSample.multiCLK(0) := io.multiCLK(0)
|
||||||
cdrInSample.multiCLK(1) := io.multiCLK(4)
|
cdrInSample.multiCLK(1) := io.multiCLK(4)
|
||||||
cdrInSample.multiCLK(2) := io.multiCLK(8)
|
cdrInSample.multiCLK(2) := io.multiCLK(8)
|
||||||
cdrInSample.multiCLK(3) := io.multiCLK(12)
|
cdrInSample.multiCLK(3) := io.multiCLK(12)
|
||||||
cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
|
cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
|
||||||
|
|
||||||
|
|
||||||
cdrInSample.io.serDat := cdrOut.io.serDat
|
cdrInSample.io.serDat := cdrOut.io.serDat
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
|
val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
|
||||||
|
|
||||||
cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 32 ).reduce(_&_)
|
cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 32 ).reduce(_&_)
|
||||||
cdrOut.io.axis.bits.tdata := io.data
|
cdrOut.io.axis.bits.tdata := io.data
|
||||||
cdrOut.io.axis.bits.tuser := false.B
|
cdrOut.io.axis.bits.tuser := false.B
|
||||||
cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
|
cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
cdrInAxis.io.axis.ready := true.B
|
cdrInAxis.io.axis.ready := true.B
|
||||||
|
|
||||||
io.isFailed := cdrInAxis.io.axis.fire & (asyncFifo.io.datar =/= cdrInAxis.io.axis.bits.tdata)
|
io.isFailed := cdrInAxis.io.axis.fire & (asyncFifo.io.datar =/= cdrInAxis.io.axis.bits.tdata)
|
||||||
io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast
|
io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val isUsing8b10b = true.B
|
val isUsing8b10b = true.B
|
||||||
|
|
||||||
|
|
||||||
when( isUsing8b10b ){
|
when( isUsing8b10b ){
|
||||||
b8b10Encoder.io <> cdrOut.io.encode
|
b8b10Encoder.io <> cdrOut.io.encode
|
||||||
b8b10Decoder.io <> cdrInAxis.io.decode
|
b8b10Decoder.io <> cdrInAxis.io.decode
|
||||||
|
|
||||||
b4b5Encoder.io.isEnable := false.B
|
b4b5Encoder.io.isEnable := false.B
|
||||||
b4b5Encoder.io.dataIn := 0.U
|
b4b5Encoder.io.dataIn := 0.U
|
||||||
b4b5Decoder.io.dataIn := 0.U
|
b4b5Decoder.io.dataIn := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
b4b5Encoder.io <> cdrOut.io.encode
|
b4b5Encoder.io <> cdrOut.io.encode
|
||||||
b4b5Decoder.io <> cdrInAxis.io.decode
|
b4b5Decoder.io <> cdrInAxis.io.decode
|
||||||
|
|
||||||
b8b10Encoder.io.isEnable := false.B
|
b8b10Encoder.io.isEnable := false.B
|
||||||
b8b10Encoder.io.dataIn := 0.U
|
b8b10Encoder.io.dataIn := 0.U
|
||||||
b8b10Decoder.io.dataIn := 0.U
|
b8b10Decoder.io.dataIn := 0.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
asyncFifo.io.clockw := clock.asBool
|
asyncFifo.io.clockw := clock.asBool
|
||||||
asyncFifo.io.dataw := io.data
|
asyncFifo.io.dataw := io.data
|
||||||
asyncFifo.io.addrw := wPtr(10,0)
|
asyncFifo.io.addrw := wPtr(10,0)
|
||||||
asyncFifo.io.enw := cdrOut.io.axis.fire
|
asyncFifo.io.enw := cdrOut.io.axis.fire
|
||||||
|
|
||||||
asyncFifo.io.clockr := io.multiCLK(0)
|
asyncFifo.io.clockr := io.multiCLK(0)
|
||||||
asyncFifo.io.addrr := rPtr(10,0)
|
asyncFifo.io.addrr := rPtr(10,0)
|
||||||
asyncFifo.io.enr := true.B
|
asyncFifo.io.enr := true.B
|
||||||
|
|
||||||
when( cdrOut.io.axis.fire ){
|
when( cdrOut.io.axis.fire ){
|
||||||
wPtr := wPtr + 1.U
|
wPtr := wPtr + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
when( cdrInAxis.io.axis.fire ){
|
when( cdrInAxis.io.axis.fire ){
|
||||||
rPtr := rPtr + 1.U
|
rPtr := rPtr + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(2048))
|
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(2048))
|
||||||
assert(~isFull)
|
assert(~isFull)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
|
val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
|
||||||
when( cdrOut.io.axis.fire ){
|
when( cdrOut.io.axis.fire ){
|
||||||
for( i <- 0 until 256 ){
|
for( i <- 0 until 256 ){
|
||||||
when( io.data === i.U ){
|
when( io.data === i.U ){
|
||||||
when( b8b10Encoder.rdTest ){
|
when( b8b10Encoder.rdTest ){
|
||||||
coverData(i) := true.B
|
coverData(i) := true.B
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
coverData(256+i) := true.B
|
coverData(256+i) := true.B
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
|
// val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
|
||||||
// when( cdrOut.io.axis.fire ){
|
// when( cdrOut.io.axis.fire ){
|
||||||
// for( i <- 0 until 256 ){
|
// for( i <- 0 until 256 ){
|
||||||
// when( io.data === i.U ){
|
// when( io.data === i.U ){
|
||||||
// coverData(i) := true.B
|
// coverData(i) := true.B
|
||||||
// }
|
// }
|
||||||
// }
|
// }
|
||||||
// }
|
// }
|
||||||
|
|
||||||
val coverage = PopCount(coverData.asUInt)
|
val coverage = PopCount(coverData.asUInt)
|
||||||
when( io.isSuccess ){
|
when( io.isSuccess ){
|
||||||
printf( cf"Coverage: ${coverage}\n")
|
printf( cf"Coverage: ${coverage}\n")
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,23 +1,23 @@
|
|||||||
package test
|
package test
|
||||||
|
|
||||||
|
|
||||||
import BACK._
|
import BACK._
|
||||||
|
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.stage._
|
import chisel3.stage._
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
object testShinModule extends App {
|
object testShinModule extends App {
|
||||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
|
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
|
||||||
ChiselGeneratorAnnotation(() => { new ShinTop }),
|
ChiselGeneratorAnnotation(() => { new ShinTop }),
|
||||||
))
|
))
|
||||||
|
|
||||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
|
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
|
||||||
ChiselGeneratorAnnotation(() => { new SimCDR }),
|
ChiselGeneratorAnnotation(() => { new SimCDR }),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -1,83 +1,83 @@
|
|||||||
.PHONY:com sim clean
|
.PHONY:com sim clean
|
||||||
|
|
||||||
OUTPUT = shin_test
|
OUTPUT = shin_test
|
||||||
CPU_COUNT := $(shell nproc)
|
CPU_COUNT := $(shell nproc)
|
||||||
SPI_TYPE ?= -spi 0
|
SPI_TYPE ?= -spi 0
|
||||||
TRANS_CODE ?=
|
TRANS_CODE ?=
|
||||||
DEVCLK ?= --dev1 0 90 --dev2 0 -88
|
DEVCLK ?= --dev1 0 90 --dev2 0 -88
|
||||||
CDR_TYPE ?= -cdr 0
|
CDR_TYPE ?= -cdr 0
|
||||||
|
|
||||||
VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
|
VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
|
||||||
-full64 \
|
-full64 \
|
||||||
-o ${OUTPUT} \
|
-o ${OUTPUT} \
|
||||||
-l compile.log \
|
-l compile.log \
|
||||||
-debug_access+none \
|
-debug_access+none \
|
||||||
+define+VCS_COMPILE \
|
+define+VCS_COMPILE \
|
||||||
-fastpartcomp=j${CPU_COUNT} \
|
-fastpartcomp=j${CPU_COUNT} \
|
||||||
|
|
||||||
SIM = ./${OUTPUT} -l run.log
|
SIM = ./${OUTPUT} -l run.log
|
||||||
|
|
||||||
testShin_vcs:
|
testShin_vcs:
|
||||||
python3 ./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
|
python3 ./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
@echo "Available CPUs: ${CPU_COUNT}"
|
@echo "Available CPUs: ${CPU_COUNT}"
|
||||||
${VCS} -f ./shinTest_vcs.f 1>vcs_compile.log 2>&1
|
${VCS} -f ./shinTest_vcs.f 1>vcs_compile.log 2>&1
|
||||||
${SIM}
|
${SIM}
|
||||||
python3 ./shinTest/check_testcase.py
|
python3 ./shinTest/check_testcase.py
|
||||||
|
|
||||||
testShinClk_vcs:
|
testShinClk_vcs:
|
||||||
python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
${VCS} -f ./shinTestClk_vcs.f 1>vcs_compile.log 2>&1
|
${VCS} -f ./shinTestClk_vcs.f 1>vcs_compile.log 2>&1
|
||||||
${SIM}
|
${SIM}
|
||||||
python3 ./shinTest/check_testcase.py
|
python3 ./shinTest/check_testcase.py
|
||||||
|
|
||||||
|
|
||||||
testShinMany_vcs:
|
testShinMany_vcs:
|
||||||
python3 ./shinTest/gen_pkt_many_dev.py
|
python3 ./shinTest/gen_pkt_many_dev.py
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
@echo "Available CPUs: ${CPU_COUNT}"
|
@echo "Available CPUs: ${CPU_COUNT}"
|
||||||
${VCS} -f ./shinTest_vcs.f
|
${VCS} -f ./shinTest_vcs.f
|
||||||
${SIM}
|
${SIM}
|
||||||
python3 ./shinTest/check_testcase.py
|
python3 ./shinTest/check_testcase.py
|
||||||
|
|
||||||
sim:
|
sim:
|
||||||
${SIM}
|
${SIM}
|
||||||
|
|
||||||
testShin:
|
testShin:
|
||||||
./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
|
./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
iverilog -Wall \
|
iverilog -Wall \
|
||||||
-o ./generated/shinTest.iverilog \
|
-o ./generated/shinTest.iverilog \
|
||||||
-y ./generated/shin \
|
-y ./generated/shin \
|
||||||
-I ./generated/shin \
|
-I ./generated/shin \
|
||||||
-D RANDOMIZE_REG_INIT \
|
-D RANDOMIZE_REG_INIT \
|
||||||
./shinTest/ShinTopSpiTb.v
|
./shinTest/ShinTopSpiTb.v
|
||||||
vvp -N ./generated/shinTest.iverilog -lxt2 -fst || true
|
vvp -N ./generated/shinTest.iverilog -lxt2 -fst || true
|
||||||
./shinTest/check_testcase.py
|
./shinTest/check_testcase.py
|
||||||
|
|
||||||
testShinClk:
|
testShinClk:
|
||||||
./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
|
||||||
mkdir -p generated/log
|
mkdir -p generated/log
|
||||||
rm -rf generated/log/*
|
rm -rf generated/log/*
|
||||||
iverilog -Wall \
|
iverilog -Wall \
|
||||||
-o ./generated/shinTest_clk.iverilog \
|
-o ./generated/shinTest_clk.iverilog \
|
||||||
-y ./generated/shin \
|
-y ./generated/shin \
|
||||||
-I ./generated/shin \
|
-I ./generated/shin \
|
||||||
-D RANDOMIZE_REG_INIT \
|
-D RANDOMIZE_REG_INIT \
|
||||||
./shinTest/ShinTopSpiTb_clk.v
|
./shinTest/ShinTopSpiTb_clk.v
|
||||||
vvp -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
|
vvp -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
|
||||||
./shinTest/check_testcase.py
|
./shinTest/check_testcase.py
|
||||||
|
|
||||||
fstShin:
|
fstShin:
|
||||||
gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
|
gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
fstShinClk:
|
fstShinClk:
|
||||||
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
|
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
|
||||||
|
|
||||||
clean:
|
clean:
|
||||||
rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*
|
rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,101 +1,101 @@
|
|||||||
`timescale 1 ns / 1 ps
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
|
||||||
module SimCDRTb(
|
module SimCDRTb(
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
reg clock = 0;
|
reg clock = 0;
|
||||||
reg reset = 0;
|
reg reset = 0;
|
||||||
|
|
||||||
reg [15:0] multiCLK;
|
reg [15:0] multiCLK;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
clock = 0;
|
clock = 0;
|
||||||
reset = 1;
|
reset = 1;
|
||||||
|
|
||||||
#100
|
#100
|
||||||
reset <= 1;
|
reset <= 1;
|
||||||
|
|
||||||
#240
|
#240
|
||||||
reset <= 0;
|
reset <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
forever begin #8000000 clock <= ~clock; end
|
forever begin #8000000 clock <= ~clock; end
|
||||||
end
|
end
|
||||||
|
|
||||||
/*
|
/*
|
||||||
generate
|
generate
|
||||||
for( genvar i = 0; i < 16; i = i + 1 ) begin
|
for( genvar i = 0; i < 16; i = i + 1 ) begin
|
||||||
initial begin
|
initial begin
|
||||||
multiCLK[i] = 0;
|
multiCLK[i] = 0;
|
||||||
for( integer j = 0; j < i; j = j + 1 ) begin
|
for( integer j = 0; j < i; j = j + 1 ) begin
|
||||||
#1000176
|
#1000176
|
||||||
;
|
;
|
||||||
end
|
end
|
||||||
forever begin #8001408 multiCLK[i] <= ~multiCLK[i]; end
|
forever begin #8001408 multiCLK[i] <= ~multiCLK[i]; end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
*/
|
*/
|
||||||
|
|
||||||
`include "simCdrClk.vh"
|
`include "simCdrClk.vh"
|
||||||
|
|
||||||
reg [7:0] data;
|
reg [7:0] data;
|
||||||
wire success;
|
wire success;
|
||||||
wire failed;
|
wire failed;
|
||||||
|
|
||||||
integer seed = 606;
|
integer seed = 606;
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
data <= $random(seed);
|
data <= $random(seed);
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
SimCDR s_SimCDR(
|
SimCDR s_SimCDR(
|
||||||
.clock(clock),
|
.clock(clock),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.io_data(data),
|
.io_data(data),
|
||||||
.io_multiCLK_0(multiCLK[0]),
|
.io_multiCLK_0(multiCLK[0]),
|
||||||
.io_multiCLK_1(multiCLK[1]),
|
.io_multiCLK_1(multiCLK[1]),
|
||||||
.io_multiCLK_2(multiCLK[2]),
|
.io_multiCLK_2(multiCLK[2]),
|
||||||
.io_multiCLK_3(multiCLK[3]),
|
.io_multiCLK_3(multiCLK[3]),
|
||||||
.io_multiCLK_4(multiCLK[4]),
|
.io_multiCLK_4(multiCLK[4]),
|
||||||
.io_multiCLK_5(multiCLK[5]),
|
.io_multiCLK_5(multiCLK[5]),
|
||||||
.io_multiCLK_6(multiCLK[6]),
|
.io_multiCLK_6(multiCLK[6]),
|
||||||
.io_multiCLK_7(multiCLK[7]),
|
.io_multiCLK_7(multiCLK[7]),
|
||||||
.io_multiCLK_8(multiCLK[8]),
|
.io_multiCLK_8(multiCLK[8]),
|
||||||
.io_multiCLK_9(multiCLK[9]),
|
.io_multiCLK_9(multiCLK[9]),
|
||||||
.io_multiCLK_10(multiCLK[10]),
|
.io_multiCLK_10(multiCLK[10]),
|
||||||
.io_multiCLK_11(multiCLK[11]),
|
.io_multiCLK_11(multiCLK[11]),
|
||||||
.io_multiCLK_12(multiCLK[12]),
|
.io_multiCLK_12(multiCLK[12]),
|
||||||
.io_multiCLK_13(multiCLK[13]),
|
.io_multiCLK_13(multiCLK[13]),
|
||||||
.io_multiCLK_14(multiCLK[14]),
|
.io_multiCLK_14(multiCLK[14]),
|
||||||
.io_multiCLK_15(multiCLK[15]),
|
.io_multiCLK_15(multiCLK[15]),
|
||||||
|
|
||||||
.io_flush(1'b0),
|
.io_flush(1'b0),
|
||||||
.io_isSuccess(success),
|
.io_isSuccess(success),
|
||||||
.io_isFailed(failed)
|
.io_isFailed(failed)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
initial
|
initial
|
||||||
begin
|
begin
|
||||||
$dumpfile("./tb/build/wave_cdr.vcd"); //生成的vcd文件名称
|
$dumpfile("./tb/build/wave_cdr.vcd"); //生成的vcd文件名称
|
||||||
$dumpvars(0, SimCDRTb);//tb模块名称
|
$dumpvars(0, SimCDRTb);//tb模块名称
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
if (success) begin
|
if (success) begin
|
||||||
$display("Success onces! \n");
|
$display("Success onces! \n");
|
||||||
end
|
end
|
||||||
if (failed) begin
|
if (failed) begin
|
||||||
$display("Error! \n");
|
$display("Error! \n");
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@@ -1,158 +1,158 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
import os
|
import os
|
||||||
|
|
||||||
|
|
||||||
def parse_value(value):
|
def parse_value(value):
|
||||||
"""Parse a value with bit-width specification and return its integer representation and mask.
|
"""Parse a value with bit-width specification and return its integer representation and mask.
|
||||||
The mask will have 1s where the bits are valid and 0s where they are 'x'.
|
The mask will have 1s where the bits are valid and 0s where they are 'x'.
|
||||||
"""
|
"""
|
||||||
if 'h' in value.lower():
|
if 'h' in value.lower():
|
||||||
base = 16
|
base = 16
|
||||||
prefix_length = value.find('h') + 1
|
prefix_length = value.find('h') + 1
|
||||||
elif 'o' in value.lower():
|
elif 'o' in value.lower():
|
||||||
base = 8
|
base = 8
|
||||||
prefix_length = value.find('o') + 1
|
prefix_length = value.find('o') + 1
|
||||||
elif 'b' in value.lower():
|
elif 'b' in value.lower():
|
||||||
base = 2
|
base = 2
|
||||||
prefix_length = value.find('b') + 1
|
prefix_length = value.find('b') + 1
|
||||||
else:
|
else:
|
||||||
raise ValueError(f"Invalid format for value: {value}")
|
raise ValueError(f"Invalid format for value: {value}")
|
||||||
|
|
||||||
# Extract the numeric part
|
# Extract the numeric part
|
||||||
num_str = value[prefix_length:]
|
num_str = value[prefix_length:]
|
||||||
|
|
||||||
# Initialize parsed value and mask
|
# Initialize parsed value and mask
|
||||||
parsed_value = 0
|
parsed_value = 0
|
||||||
mask = 0
|
mask = 0
|
||||||
|
|
||||||
# Process each character in the numeric part
|
# Process each character in the numeric part
|
||||||
#print(num_str)
|
#print(num_str)
|
||||||
for char in num_str:
|
for char in num_str:
|
||||||
if char.lower() == 'x':
|
if char.lower() == 'x':
|
||||||
mask = mask * base
|
mask = mask * base
|
||||||
parsed_value = parsed_value * base
|
parsed_value = parsed_value * base
|
||||||
else:
|
else:
|
||||||
mask = (mask * base) + (base - 1)
|
mask = (mask * base) + (base - 1)
|
||||||
parsed_value = (parsed_value * base) + int(char, base)
|
parsed_value = (parsed_value * base) + int(char, base)
|
||||||
|
|
||||||
#print(value, hex(parsed_value), hex(mask))
|
#print(value, hex(parsed_value), hex(mask))
|
||||||
return parsed_value, mask
|
return parsed_value, mask
|
||||||
|
|
||||||
def compare_files(source_file, target_file):
|
def compare_files(source_file, target_file):
|
||||||
warning_need_recheck = 0
|
warning_need_recheck = 0
|
||||||
try:
|
try:
|
||||||
with open(source_file, 'r') as src, open(target_file, 'r') as tgt:
|
with open(source_file, 'r') as src, open(target_file, 'r') as tgt:
|
||||||
source_lines = src.readlines()
|
source_lines = src.readlines()
|
||||||
target_lines = tgt.readlines()
|
target_lines = tgt.readlines()
|
||||||
|
|
||||||
if len(source_lines) != len(target_lines):
|
if len(source_lines) != len(target_lines):
|
||||||
print(f"Error: The number of lines in {source_file} and {target_file} do not match.")
|
print(f"Error: The number of lines in {source_file} and {target_file} do not match.")
|
||||||
return
|
return
|
||||||
|
|
||||||
all_match = True
|
all_match = True
|
||||||
|
|
||||||
for i, (src_line, tgt_line) in enumerate(zip(source_lines, target_lines)):
|
for i, (src_line, tgt_line) in enumerate(zip(source_lines, target_lines)):
|
||||||
src_values = src_line.strip().split()
|
src_values = src_line.strip().split()
|
||||||
tgt_values = tgt_line.strip().split()
|
tgt_values = tgt_line.strip().split()
|
||||||
|
|
||||||
if len(src_values) != len(tgt_values):
|
if len(src_values) != len(tgt_values):
|
||||||
if len(src_values) != 1:
|
if len(src_values) != 1:
|
||||||
print(f"Error: Line {i+1}: The number of values in {source_file} and {target_file} do not match.")
|
print(f"Error: Line {i+1}: The number of values in {source_file} and {target_file} do not match.")
|
||||||
all_match = False
|
all_match = False
|
||||||
continue
|
continue
|
||||||
else:
|
else:
|
||||||
if src_values[0].strip().lower() == 'x':
|
if src_values[0].strip().lower() == 'x':
|
||||||
if warning_need_recheck == 0:
|
if warning_need_recheck == 0:
|
||||||
print(f'[\033[93mWARNING\033[0m] Ignored lines detected. This test case requires manual comparison. \n\t[\033[93mTARGET\033[0m] {target_file}\n\t[\033[93mSRC\033[0m] {source_file}')
|
print(f'[\033[93mWARNING\033[0m] Ignored lines detected. This test case requires manual comparison. \n\t[\033[93mTARGET\033[0m] {target_file}\n\t[\033[93mSRC\033[0m] {source_file}')
|
||||||
warning_need_recheck = 1
|
warning_need_recheck = 1
|
||||||
continue
|
continue
|
||||||
|
|
||||||
line_match = True
|
line_match = True
|
||||||
|
|
||||||
for j, (src_val, tgt_val) in enumerate(zip(src_values, tgt_values)):
|
for j, (src_val, tgt_val) in enumerate(zip(src_values, tgt_values)):
|
||||||
try:
|
try:
|
||||||
src_int, src_mask = parse_value(src_val)
|
src_int, src_mask = parse_value(src_val)
|
||||||
tgt_int, tgt_mask = parse_value(tgt_val)
|
tgt_int, tgt_mask = parse_value(tgt_val)
|
||||||
except ValueError as e:
|
except ValueError as e:
|
||||||
print(f"Error: Line {i+1}, Position {j+1}: {e}")
|
print(f"Error: Line {i+1}, Position {j+1}: {e}")
|
||||||
line_match = False
|
line_match = False
|
||||||
all_match = False
|
all_match = False
|
||||||
continue
|
continue
|
||||||
|
|
||||||
# Combine masks to determine which bits to compare
|
# Combine masks to determine which bits to compare
|
||||||
combined_mask = src_mask #& tgt_mask
|
combined_mask = src_mask #& tgt_mask
|
||||||
|
|
||||||
# Compare only the bits that are not 'x' in either source or target
|
# Compare only the bits that are not 'x' in either source or target
|
||||||
if combined_mask == 0:
|
if combined_mask == 0:
|
||||||
#print(f"Line {i+1}, Position {j+1}: Both values contain 'x' at all positions, skipping check.")
|
#print(f"Line {i+1}, Position {j+1}: Both values contain 'x' at all positions, skipping check.")
|
||||||
continue
|
continue
|
||||||
|
|
||||||
masked_src = src_int & combined_mask
|
masked_src = src_int & combined_mask
|
||||||
masked_tgt = tgt_int & combined_mask
|
masked_tgt = tgt_int & combined_mask
|
||||||
#print(hex(masked_src), hex(masked_tgt), hex(combined_mask))
|
#print(hex(masked_src), hex(masked_tgt), hex(combined_mask))
|
||||||
|
|
||||||
if masked_src == masked_tgt:
|
if masked_src == masked_tgt:
|
||||||
#print(f"Line {i+1}, Position {j+1}: Values match ({src_val} == {tgt_val}).")
|
#print(f"Line {i+1}, Position {j+1}: Values match ({src_val} == {tgt_val}).")
|
||||||
pass
|
pass
|
||||||
else:
|
else:
|
||||||
#print(f"\tLine {i+1}, Position {j+1}: Values differ ({src_val} != {tgt_val}).")
|
#print(f"\tLine {i+1}, Position {j+1}: Values differ ({src_val} != {tgt_val}).")
|
||||||
line_match = False
|
line_match = False
|
||||||
all_match = False
|
all_match = False
|
||||||
|
|
||||||
if line_match:
|
if line_match:
|
||||||
#print(f"Line {i+1}: All values on this line match.")
|
#print(f"Line {i+1}: All values on this line match.")
|
||||||
pass
|
pass
|
||||||
|
|
||||||
if all_match:
|
if all_match:
|
||||||
#print("All lines match.")
|
#print("All lines match.")
|
||||||
#pass
|
#pass
|
||||||
return True
|
return True
|
||||||
else:
|
else:
|
||||||
#print("Some lines or positions do not match.")
|
#print("Some lines or positions do not match.")
|
||||||
#pass
|
#pass
|
||||||
return False
|
return False
|
||||||
|
|
||||||
except FileNotFoundError as e:
|
except FileNotFoundError as e:
|
||||||
print(f"Error: {e}")
|
print(f"Error: {e}")
|
||||||
except Exception as e:
|
except Exception as e:
|
||||||
print(f"An unexpected error occurred: {e}")
|
print(f"An unexpected error occurred: {e}")
|
||||||
|
|
||||||
return False
|
return False
|
||||||
|
|
||||||
def list_files_in_directory(directory):
|
def list_files_in_directory(directory):
|
||||||
try:
|
try:
|
||||||
# 获取目录中的所有文件和子目录
|
# 获取目录中的所有文件和子目录
|
||||||
files = os.listdir(directory)
|
files = os.listdir(directory)
|
||||||
|
|
||||||
# 过滤出文件（排除子目录）
|
# 过滤出文件（排除子目录）
|
||||||
files_only = [f for f in files if os.path.isfile(os.path.join(directory, f))]
|
files_only = [f for f in files if os.path.isfile(os.path.join(directory, f))]
|
||||||
|
|
||||||
return files_only
|
return files_only
|
||||||
except FileNotFoundError:
|
except FileNotFoundError:
|
||||||
print(f"Error: The directory '{directory}' does not exist.")
|
print(f"Error: The directory '{directory}' does not exist.")
|
||||||
return []
|
return []
|
||||||
except PermissionError:
|
except PermissionError:
|
||||||
print(f"Error: Permission denied to access the directory '{directory}'.")
|
print(f"Error: Permission denied to access the directory '{directory}'.")
|
||||||
return []
|
return []
|
||||||
except Exception as e:
|
except Exception as e:
|
||||||
print(f"An unexpected error occurred: {e}")
|
print(f"An unexpected error occurred: {e}")
|
||||||
return []
|
return []
|
||||||
|
|
||||||
if __name__ == "__main__":
|
if __name__ == "__main__":
|
||||||
files = list_files_in_directory('generated/log')
|
files = list_files_in_directory('generated/log')
|
||||||
src_files = list_files_in_directory('tb/shinTest/testcase_result')
|
src_files = list_files_in_directory('tb/shinTest/testcase_result')
|
||||||
for fi in files:
|
for fi in files:
|
||||||
rst_f = 'generated/log/' + fi
|
rst_f = 'generated/log/' + fi
|
||||||
src_f = 'tb/shinTest/testcase_result/' + fi
|
src_f = 'tb/shinTest/testcase_result/' + fi
|
||||||
|
|
||||||
outmsg = f"TESTCASE: {fi}"
|
outmsg = f"TESTCASE: {fi}"
|
||||||
outmsg = outmsg + " " * (60 - len(outmsg))
|
outmsg = outmsg + " " * (60 - len(outmsg))
|
||||||
if not (fi in src_files):
|
if not (fi in src_files):
|
||||||
print(f"{outmsg}[\033[93mIGNORE\033[0m]")
|
print(f"{outmsg}[\033[93mIGNORE\033[0m]")
|
||||||
continue
|
continue
|
||||||
|
|
||||||
if compare_files(src_f, rst_f):
|
if compare_files(src_f, rst_f):
|
||||||
print(f"{outmsg}[\033[92mPASS\033[0m]")
|
print(f"{outmsg}[\033[92mPASS\033[0m]")
|
||||||
else:
|
else:
|
||||||
print(f"{outmsg}[\033[91mFAILED\033[0m]\n\t[\033[91mTARGET\033[0m] {rst_f}\n\t[\033[91mSRC\033[0m] {src_f}")
|
print(f"{outmsg}[\033[91mFAILED\033[0m]\n\t[\033[91mTARGET\033[0m] {rst_f}\n\t[\033[91mSRC\033[0m] {src_f}")
|
||||||
@@ -1,164 +1,164 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
from pyutils import *
|
from pyutils import *
|
||||||
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac
|
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac
|
||||||
import argparse
|
import argparse
|
||||||
|
|
||||||
|
|
||||||
if __name__ == '__main__':
|
if __name__ == '__main__':
|
||||||
parser = argparse.ArgumentParser()
|
parser = argparse.ArgumentParser()
|
||||||
|
|
||||||
# 可选参数
|
# 可选参数
|
||||||
parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
|
parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
|
||||||
parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
|
parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
|
||||||
parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")
|
parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")
|
||||||
# 解析参数
|
# 解析参数
|
||||||
args = parser.parse_args()
|
args = parser.parse_args()
|
||||||
|
|
||||||
#if args.use_8b10b:
|
#if args.use_8b10b:
|
||||||
# add_tc_2_runlist(rwregs.tc1())
|
# add_tc_2_runlist(rwregs.tc1())
|
||||||
#print(args.spi_type)
|
#print(args.spi_type)
|
||||||
environment.set_spi_interface(args.spi_type)
|
environment.set_spi_interface(args.spi_type)
|
||||||
environment.set_using_8b10b(args.use_8b10b)
|
environment.set_using_8b10b(args.use_8b10b)
|
||||||
environment.set_cdr_type(args.cdr_type)
|
environment.set_cdr_type(args.cdr_type)
|
||||||
|
|
||||||
environment.gen_slv_dev_num(4)
|
environment.gen_slv_dev_num(4)
|
||||||
environment.bringup()
|
environment.bringup()
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(errorPkt.tc1())
|
add_tc_2_runlist(errorPkt.tc1())
|
||||||
add_tc_2_runlist(errorPkt.tc2())
|
add_tc_2_runlist(errorPkt.tc2())
|
||||||
add_tc_2_runlist(errorPkt.tc3())
|
add_tc_2_runlist(errorPkt.tc3())
|
||||||
add_tc_2_runlist(errorPkt.tc4())
|
add_tc_2_runlist(errorPkt.tc4())
|
||||||
add_tc_2_runlist(errorPkt.tc5())
|
add_tc_2_runlist(errorPkt.tc5())
|
||||||
add_tc_2_runlist(errorPkt.tc6())
|
add_tc_2_runlist(errorPkt.tc6())
|
||||||
add_tc_2_runlist(errorPkt.tc7())
|
add_tc_2_runlist(errorPkt.tc7())
|
||||||
add_tc_2_runlist(errorPkt.tc8())
|
add_tc_2_runlist(errorPkt.tc8())
|
||||||
add_tc_2_runlist(errorPkt.tc9())
|
add_tc_2_runlist(errorPkt.tc9())
|
||||||
add_tc_2_runlist(errorPkt.tc10())
|
add_tc_2_runlist(errorPkt.tc10())
|
||||||
add_tc_2_runlist(errorPkt.tc11())
|
add_tc_2_runlist(errorPkt.tc11())
|
||||||
add_tc_2_runlist(errorPkt.tc12())
|
add_tc_2_runlist(errorPkt.tc12())
|
||||||
add_tc_2_runlist(errorPkt.tc13())
|
add_tc_2_runlist(errorPkt.tc13())
|
||||||
add_tc_2_runlist(errorPkt.tc14())
|
add_tc_2_runlist(errorPkt.tc14())
|
||||||
add_tc_2_runlist(errorPkt.tc15())
|
add_tc_2_runlist(errorPkt.tc15())
|
||||||
add_tc_2_runlist(errorPkt.tc16())
|
add_tc_2_runlist(errorPkt.tc16())
|
||||||
add_tc_2_runlist(errorPkt.tc17())
|
add_tc_2_runlist(errorPkt.tc17())
|
||||||
add_tc_2_runlist(errorPkt.tc18())
|
add_tc_2_runlist(errorPkt.tc18())
|
||||||
add_tc_2_runlist(errorPkt.tc19())
|
add_tc_2_runlist(errorPkt.tc19())
|
||||||
add_tc_2_runlist(errorPkt.tc20())
|
add_tc_2_runlist(errorPkt.tc20())
|
||||||
add_tc_2_runlist(errorPkt.tc21())
|
add_tc_2_runlist(errorPkt.tc21())
|
||||||
add_tc_2_runlist(errorPkt.tc22())
|
add_tc_2_runlist(errorPkt.tc22())
|
||||||
add_tc_2_runlist(errorPkt.tc23())
|
add_tc_2_runlist(errorPkt.tc23())
|
||||||
add_tc_2_runlist(errorPkt.tc24())
|
add_tc_2_runlist(errorPkt.tc24())
|
||||||
add_tc_2_runlist(errorPkt.tc25())
|
add_tc_2_runlist(errorPkt.tc25())
|
||||||
add_tc_2_runlist(errorPkt.tc26())
|
add_tc_2_runlist(errorPkt.tc26())
|
||||||
add_tc_2_runlist(errorPkt.tc27())
|
add_tc_2_runlist(errorPkt.tc27())
|
||||||
add_tc_2_runlist(errorPkt.tc28())
|
add_tc_2_runlist(errorPkt.tc28())
|
||||||
add_tc_2_runlist(errorPkt.tc29())
|
add_tc_2_runlist(errorPkt.tc29())
|
||||||
add_tc_2_runlist(errorPkt.tc30())
|
add_tc_2_runlist(errorPkt.tc30())
|
||||||
add_tc_2_runlist(errorPkt.tc31())
|
add_tc_2_runlist(errorPkt.tc31())
|
||||||
add_tc_2_runlist(errorPkt.tc32())
|
add_tc_2_runlist(errorPkt.tc32())
|
||||||
add_tc_2_runlist(errorPkt.tc33())
|
add_tc_2_runlist(errorPkt.tc33())
|
||||||
add_tc_2_runlist(errorPkt.tc34())
|
add_tc_2_runlist(errorPkt.tc34())
|
||||||
add_tc_2_runlist(errorPkt.tc35())
|
add_tc_2_runlist(errorPkt.tc35())
|
||||||
add_tc_2_runlist(errorPkt.tc36())
|
add_tc_2_runlist(errorPkt.tc36())
|
||||||
add_tc_2_runlist(errorPkt.tc37())
|
add_tc_2_runlist(errorPkt.tc37())
|
||||||
add_tc_2_runlist(errorPkt.tc38())
|
add_tc_2_runlist(errorPkt.tc38())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(rwregs.tc1())
|
add_tc_2_runlist(rwregs.tc1())
|
||||||
add_tc_2_runlist(rwregs.tc2())
|
add_tc_2_runlist(rwregs.tc2())
|
||||||
add_tc_2_runlist(rwregs.tc3())
|
add_tc_2_runlist(rwregs.tc3())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(base.tc1())
|
add_tc_2_runlist(base.tc1())
|
||||||
add_tc_2_runlist(base.tc2())
|
add_tc_2_runlist(base.tc2())
|
||||||
add_tc_2_runlist(base.tc3())
|
add_tc_2_runlist(base.tc3())
|
||||||
add_tc_2_runlist(base.tc4())
|
add_tc_2_runlist(base.tc4())
|
||||||
add_tc_2_runlist(base.tc5())
|
add_tc_2_runlist(base.tc5())
|
||||||
add_tc_2_runlist(base.tc6())
|
add_tc_2_runlist(base.tc6())
|
||||||
add_tc_2_runlist(base.tc7())
|
add_tc_2_runlist(base.tc7())
|
||||||
add_tc_2_runlist(base.tc8())
|
add_tc_2_runlist(base.tc8())
|
||||||
add_tc_2_runlist(base.tc9())
|
add_tc_2_runlist(base.tc9())
|
||||||
add_tc_2_runlist(base.tc10())
|
add_tc_2_runlist(base.tc10())
|
||||||
add_tc_2_runlist(base.tc11())
|
add_tc_2_runlist(base.tc11())
|
||||||
add_tc_2_runlist(base.tc12())
|
add_tc_2_runlist(base.tc12())
|
||||||
add_tc_2_runlist(base.tc13())
|
add_tc_2_runlist(base.tc13())
|
||||||
add_tc_2_runlist(base.tc14())
|
add_tc_2_runlist(base.tc14())
|
||||||
add_tc_2_runlist(base.tc15())
|
add_tc_2_runlist(base.tc15())
|
||||||
add_tc_2_runlist(base.tc16())
|
add_tc_2_runlist(base.tc16())
|
||||||
add_tc_2_runlist(base.tc17())
|
add_tc_2_runlist(base.tc17())
|
||||||
add_tc_2_runlist(base.tc18())
|
add_tc_2_runlist(base.tc18())
|
||||||
add_tc_2_runlist(base.tc19())
|
add_tc_2_runlist(base.tc19())
|
||||||
add_tc_2_runlist(base.tc20())
|
add_tc_2_runlist(base.tc20())
|
||||||
add_tc_2_runlist(base.tc21())
|
add_tc_2_runlist(base.tc21())
|
||||||
add_tc_2_runlist(base.tc22())
|
add_tc_2_runlist(base.tc22())
|
||||||
add_tc_2_runlist(base.tc23())
|
add_tc_2_runlist(base.tc23())
|
||||||
add_tc_2_runlist(base.tc24())
|
add_tc_2_runlist(base.tc24())
|
||||||
add_tc_2_runlist(base.tc25())
|
add_tc_2_runlist(base.tc25())
|
||||||
add_tc_2_runlist(base.tc26())
|
add_tc_2_runlist(base.tc26())
|
||||||
add_tc_2_runlist(base.tc27())
|
add_tc_2_runlist(base.tc27())
|
||||||
add_tc_2_runlist(base.tc28())
|
add_tc_2_runlist(base.tc28())
|
||||||
add_tc_2_runlist(base.tc29())
|
add_tc_2_runlist(base.tc29())
|
||||||
add_tc_2_runlist(base.tc30())
|
add_tc_2_runlist(base.tc30())
|
||||||
add_tc_2_runlist(base.tc31())
|
add_tc_2_runlist(base.tc31())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(broadcast.tc1())
|
add_tc_2_runlist(broadcast.tc1())
|
||||||
add_tc_2_runlist(broadcast.tc2())
|
add_tc_2_runlist(broadcast.tc2())
|
||||||
add_tc_2_runlist(broadcast.tc3())
|
add_tc_2_runlist(broadcast.tc3())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(sync.tc1())
|
add_tc_2_runlist(sync.tc1())
|
||||||
add_tc_2_runlist(sync.tc2())
|
add_tc_2_runlist(sync.tc2())
|
||||||
add_tc_2_runlist(sync.tc3())
|
add_tc_2_runlist(sync.tc3())
|
||||||
add_tc_2_runlist(sync.tc4())
|
add_tc_2_runlist(sync.tc4())
|
||||||
add_tc_2_runlist(sync.tc5())
|
add_tc_2_runlist(sync.tc5())
|
||||||
add_tc_2_runlist(sync.tc6())
|
add_tc_2_runlist(sync.tc6())
|
||||||
add_tc_2_runlist(sync.tc7())
|
add_tc_2_runlist(sync.tc7())
|
||||||
add_tc_2_runlist(sync.tc8())
|
add_tc_2_runlist(sync.tc8())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(ebmmu.tc1())
|
add_tc_2_runlist(ebmmu.tc1())
|
||||||
add_tc_2_runlist(ebmmu.tc2())
|
add_tc_2_runlist(ebmmu.tc2())
|
||||||
add_tc_2_runlist(ebmmu.tc3())
|
add_tc_2_runlist(ebmmu.tc3())
|
||||||
add_tc_2_runlist(ebmmu.tc4())
|
add_tc_2_runlist(ebmmu.tc4())
|
||||||
add_tc_2_runlist(ebmmu.tc5())
|
add_tc_2_runlist(ebmmu.tc5())
|
||||||
add_tc_2_runlist(ebmmu.tc6())
|
add_tc_2_runlist(ebmmu.tc6())
|
||||||
add_tc_2_runlist(ebmmu.tc7())
|
add_tc_2_runlist(ebmmu.tc7())
|
||||||
add_tc_2_runlist(ebmmu.tc8())
|
add_tc_2_runlist(ebmmu.tc8())
|
||||||
add_tc_2_runlist(ebmmu.tc9())
|
add_tc_2_runlist(ebmmu.tc9())
|
||||||
add_tc_2_runlist(ebmmu.tc10())
|
add_tc_2_runlist(ebmmu.tc10())
|
||||||
add_tc_2_runlist(ebmmu.tc11())
|
add_tc_2_runlist(ebmmu.tc11())
|
||||||
add_tc_2_runlist(ebmmu.tc12())
|
add_tc_2_runlist(ebmmu.tc12())
|
||||||
add_tc_2_runlist(ebmmu.tc13())
|
add_tc_2_runlist(ebmmu.tc13())
|
||||||
add_tc_2_runlist(ebmmu.tc14())
|
add_tc_2_runlist(ebmmu.tc14())
|
||||||
add_tc_2_runlist(ebmmu.tc15())
|
add_tc_2_runlist(ebmmu.tc15())
|
||||||
add_tc_2_runlist(ebmmu.tc16())
|
add_tc_2_runlist(ebmmu.tc16())
|
||||||
add_tc_2_runlist(ebmmu.tc17())
|
add_tc_2_runlist(ebmmu.tc17())
|
||||||
add_tc_2_runlist(ebmmu.tc18())
|
add_tc_2_runlist(ebmmu.tc18())
|
||||||
add_tc_2_runlist(ebmmu.tc19())
|
add_tc_2_runlist(ebmmu.tc19())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
add_tc_2_runlist(watchdog.tc1())
|
add_tc_2_runlist(watchdog.tc1())
|
||||||
add_tc_2_runlist(watchdog.tc2())
|
add_tc_2_runlist(watchdog.tc2())
|
||||||
add_tc_2_runlist(watchdog.tc3())
|
add_tc_2_runlist(watchdog.tc3())
|
||||||
add_tc_2_runlist(watchdog.tc4())
|
add_tc_2_runlist(watchdog.tc4())
|
||||||
|
|
||||||
#add_tc_2_runlist(mac.tc1())
|
#add_tc_2_runlist(mac.tc1())
|
||||||
#add_tc_2_runlist(mac.tc2())
|
#add_tc_2_runlist(mac.tc2())
|
||||||
#add_tc_2_runlist(mac.tc3())
|
#add_tc_2_runlist(mac.tc3())
|
||||||
#add_tc_2_runlist(mac.tc4())
|
#add_tc_2_runlist(mac.tc4())
|
||||||
#add_tc_2_runlist(mac.tc5())
|
#add_tc_2_runlist(mac.tc5())
|
||||||
#add_tc_2_runlist(mac.tc6())
|
#add_tc_2_runlist(mac.tc6())
|
||||||
#add_tc_2_runlist(mac.tc7())
|
#add_tc_2_runlist(mac.tc7())
|
||||||
|
|
||||||
environment.teardown()
|
environment.teardown()
|
||||||
|
|
||||||
gen_tc_runlist()
|
gen_tc_runlist()
|
||||||
|
|
||||||
|
|||||||
@@ -1,168 +1,168 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
from pyutils import *
|
from pyutils import *
|
||||||
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac
|
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac
|
||||||
import argparse
|
import argparse
|
||||||
|
|
||||||
if __name__ == '__main__':
|
if __name__ == '__main__':
|
||||||
|
|
||||||
parser = argparse.ArgumentParser()
|
parser = argparse.ArgumentParser()
|
||||||
|
|
||||||
# 可选参数
|
# 可选参数
|
||||||
parser.add_argument("-d1", "--dev1", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
parser.add_argument("-d1", "--dev1", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
||||||
parser.add_argument("-d2", "--dev2", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
parser.add_argument("-d2", "--dev2", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
||||||
parser.add_argument("-d3", "--dev3", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
parser.add_argument("-d3", "--dev3", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
||||||
parser.add_argument("-d4", "--dev4", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
parser.add_argument("-d4", "--dev4", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
||||||
parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
|
parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
|
||||||
parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
|
parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
|
||||||
parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")
|
parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")
|
||||||
|
|
||||||
# 解析参数
|
# 解析参数
|
||||||
args = parser.parse_args()
|
args = parser.parse_args()
|
||||||
# 使用参数
|
# 使用参数
|
||||||
dev_clk_info = dict()
|
dev_clk_info = dict()
|
||||||
if args.dev1 != [0, 0]:
|
if args.dev1 != [0, 0]:
|
||||||
dev_clk_info[1] = args.dev1
|
dev_clk_info[1] = args.dev1
|
||||||
|
|
||||||
if args.dev2 != [0, 0]:
|
if args.dev2 != [0, 0]:
|
||||||
dev_clk_info[2] = args.dev2
|
dev_clk_info[2] = args.dev2
|
||||||
|
|
||||||
if args.dev3 != [0, 0]:
|
if args.dev3 != [0, 0]:
|
||||||
dev_clk_info[3] = args.dev3
|
dev_clk_info[3] = args.dev3
|
||||||
|
|
||||||
if args.dev4 != [0, 0]:
|
if args.dev4 != [0, 0]:
|
||||||
dev_clk_info[4] = args.dev4
|
dev_clk_info[4] = args.dev4
|
||||||
|
|
||||||
environment.set_dev_clk(dev_clk_info)
|
environment.set_dev_clk(dev_clk_info)
|
||||||
environment.set_spi_interface(args.spi_type)
|
environment.set_spi_interface(args.spi_type)
|
||||||
environment.set_using_8b10b(args.use_8b10b)
|
environment.set_using_8b10b(args.use_8b10b)
|
||||||
environment.set_cdr_type(args.cdr_type)
|
environment.set_cdr_type(args.cdr_type)
|
||||||
|
|
||||||
environment.gen_slv_dev_for_clk(4)
|
environment.gen_slv_dev_for_clk(4)
|
||||||
|
|
||||||
environment.bringup()
|
environment.bringup()
|
||||||
|
|
||||||
if args.use_8b10b:
|
if args.use_8b10b:
|
||||||
add_tc_2_runlist(rwregs.tc1())
|
add_tc_2_runlist(rwregs.tc1())
|
||||||
|
|
||||||
#add_tc_2_runlist(errorPkt.tc1())
|
#add_tc_2_runlist(errorPkt.tc1())
|
||||||
#add_tc_2_runlist(errorPkt.tc2())
|
#add_tc_2_runlist(errorPkt.tc2())
|
||||||
#add_tc_2_runlist(errorPkt.tc3())
|
#add_tc_2_runlist(errorPkt.tc3())
|
||||||
#add_tc_2_runlist(errorPkt.tc4())
|
#add_tc_2_runlist(errorPkt.tc4())
|
||||||
#add_tc_2_runlist(errorPkt.tc5())
|
#add_tc_2_runlist(errorPkt.tc5())
|
||||||
#add_tc_2_runlist(errorPkt.tc6())
|
#add_tc_2_runlist(errorPkt.tc6())
|
||||||
#add_tc_2_runlist(errorPkt.tc7())
|
#add_tc_2_runlist(errorPkt.tc7())
|
||||||
#add_tc_2_runlist(errorPkt.tc8())
|
#add_tc_2_runlist(errorPkt.tc8())
|
||||||
#add_tc_2_runlist(errorPkt.tc9())
|
#add_tc_2_runlist(errorPkt.tc9())
|
||||||
#add_tc_2_runlist(errorPkt.tc10())
|
#add_tc_2_runlist(errorPkt.tc10())
|
||||||
#add_tc_2_runlist(errorPkt.tc11())
|
#add_tc_2_runlist(errorPkt.tc11())
|
||||||
#add_tc_2_runlist(errorPkt.tc12())
|
#add_tc_2_runlist(errorPkt.tc12())
|
||||||
#add_tc_2_runlist(errorPkt.tc13())
|
#add_tc_2_runlist(errorPkt.tc13())
|
||||||
#add_tc_2_runlist(errorPkt.tc14())
|
#add_tc_2_runlist(errorPkt.tc14())
|
||||||
#add_tc_2_runlist(errorPkt.tc15())
|
#add_tc_2_runlist(errorPkt.tc15())
|
||||||
#add_tc_2_runlist(errorPkt.tc16())
|
#add_tc_2_runlist(errorPkt.tc16())
|
||||||
#add_tc_2_runlist(errorPkt.tc17())
|
#add_tc_2_runlist(errorPkt.tc17())
|
||||||
#add_tc_2_runlist(errorPkt.tc18())
|
#add_tc_2_runlist(errorPkt.tc18())
|
||||||
#add_tc_2_runlist(errorPkt.tc19())
|
#add_tc_2_runlist(errorPkt.tc19())
|
||||||
#add_tc_2_runlist(errorPkt.tc20())
|
#add_tc_2_runlist(errorPkt.tc20())
|
||||||
#add_tc_2_runlist(errorPkt.tc21())
|
#add_tc_2_runlist(errorPkt.tc21())
|
||||||
#add_tc_2_runlist(errorPkt.tc22())
|
#add_tc_2_runlist(errorPkt.tc22())
|
||||||
#add_tc_2_runlist(errorPkt.tc23())
|
#add_tc_2_runlist(errorPkt.tc23())
|
||||||
#add_tc_2_runlist(errorPkt.tc24())
|
#add_tc_2_runlist(errorPkt.tc24())
|
||||||
#add_tc_2_runlist(errorPkt.tc25())
|
#add_tc_2_runlist(errorPkt.tc25())
|
||||||
#add_tc_2_runlist(errorPkt.tc26())
|
#add_tc_2_runlist(errorPkt.tc26())
|
||||||
#add_tc_2_runlist(errorPkt.tc27())
|
#add_tc_2_runlist(errorPkt.tc27())
|
||||||
#add_tc_2_runlist(errorPkt.tc28())
|
#add_tc_2_runlist(errorPkt.tc28())
|
||||||
#add_tc_2_runlist(errorPkt.tc29())
|
#add_tc_2_runlist(errorPkt.tc29())
|
||||||
#add_tc_2_runlist(errorPkt.tc30())
|
#add_tc_2_runlist(errorPkt.tc30())
|
||||||
#add_tc_2_runlist(errorPkt.tc31())
|
#add_tc_2_runlist(errorPkt.tc31())
|
||||||
#add_tc_2_runlist(errorPkt.tc32())
|
#add_tc_2_runlist(errorPkt.tc32())
|
||||||
#add_tc_2_runlist(errorPkt.tc33())
|
#add_tc_2_runlist(errorPkt.tc33())
|
||||||
#add_tc_2_runlist(errorPkt.tc34())
|
#add_tc_2_runlist(errorPkt.tc34())
|
||||||
#add_tc_2_runlist(errorPkt.tc35())
|
#add_tc_2_runlist(errorPkt.tc35())
|
||||||
#add_tc_2_runlist(errorPkt.tc36())
|
#add_tc_2_runlist(errorPkt.tc36())
|
||||||
#add_tc_2_runlist(errorPkt.tc37())
|
#add_tc_2_runlist(errorPkt.tc37())
|
||||||
#add_tc_2_runlist(errorPkt.tc38())
|
#add_tc_2_runlist(errorPkt.tc38())
|
||||||
|
|
||||||
|
|
||||||
#add_tc_2_runlist(base.tc1())
|
#add_tc_2_runlist(base.tc1())
|
||||||
#add_tc_2_runlist(base.tc2())
|
#add_tc_2_runlist(base.tc2())
|
||||||
#add_tc_2_runlist(base.tc3())
|
#add_tc_2_runlist(base.tc3())
|
||||||
#add_tc_2_runlist(base.tc4())
|
#add_tc_2_runlist(base.tc4())
|
||||||
#add_tc_2_runlist(base.tc5())
|
#add_tc_2_runlist(base.tc5())
|
||||||
#add_tc_2_runlist(base.tc6())
|
#add_tc_2_runlist(base.tc6())
|
||||||
#add_tc_2_runlist(base.tc7())
|
#add_tc_2_runlist(base.tc7())
|
||||||
#add_tc_2_runlist(base.tc8())
|
#add_tc_2_runlist(base.tc8())
|
||||||
#add_tc_2_runlist(base.tc9())
|
#add_tc_2_runlist(base.tc9())
|
||||||
#add_tc_2_runlist(base.tc10())
|
#add_tc_2_runlist(base.tc10())
|
||||||
#add_tc_2_runlist(base.tc11())
|
#add_tc_2_runlist(base.tc11())
|
||||||
#add_tc_2_runlist(base.tc12())
|
#add_tc_2_runlist(base.tc12())
|
||||||
#add_tc_2_runlist(base.tc13())
|
#add_tc_2_runlist(base.tc13())
|
||||||
#add_tc_2_runlist(base.tc14())
|
#add_tc_2_runlist(base.tc14())
|
||||||
#add_tc_2_runlist(base.tc15())
|
#add_tc_2_runlist(base.tc15())
|
||||||
#add_tc_2_runlist(base.tc16())
|
#add_tc_2_runlist(base.tc16())
|
||||||
#add_tc_2_runlist(base.tc17())
|
#add_tc_2_runlist(base.tc17())
|
||||||
#add_tc_2_runlist(base.tc18())
|
#add_tc_2_runlist(base.tc18())
|
||||||
#add_tc_2_runlist(base.tc19())
|
#add_tc_2_runlist(base.tc19())
|
||||||
#add_tc_2_runlist(base.tc20())
|
#add_tc_2_runlist(base.tc20())
|
||||||
#add_tc_2_runlist(base.tc21())
|
#add_tc_2_runlist(base.tc21())
|
||||||
#add_tc_2_runlist(base.tc22())
|
#add_tc_2_runlist(base.tc22())
|
||||||
#add_tc_2_runlist(base.tc23())
|
#add_tc_2_runlist(base.tc23())
|
||||||
#add_tc_2_runlist(base.tc24())
|
#add_tc_2_runlist(base.tc24())
|
||||||
#add_tc_2_runlist(base.tc25())
|
#add_tc_2_runlist(base.tc25())
|
||||||
#add_tc_2_runlist(base.tc26())
|
#add_tc_2_runlist(base.tc26())
|
||||||
#add_tc_2_runlist(base.tc27())
|
#add_tc_2_runlist(base.tc27())
|
||||||
#add_tc_2_runlist(base.tc28())
|
#add_tc_2_runlist(base.tc28())
|
||||||
#add_tc_2_runlist(base.tc29())
|
#add_tc_2_runlist(base.tc29())
|
||||||
add_tc_2_runlist(base.tc29())
|
add_tc_2_runlist(base.tc29())
|
||||||
add_tc_2_runlist(base.tc30())
|
add_tc_2_runlist(base.tc30())
|
||||||
|
|
||||||
|
|
||||||
#add_tc_2_runlist(broadcast.tc1())
|
#add_tc_2_runlist(broadcast.tc1())
|
||||||
#add_tc_2_runlist(broadcast.tc2())
|
#add_tc_2_runlist(broadcast.tc2())
|
||||||
#add_tc_2_runlist(broadcast.tc3())
|
#add_tc_2_runlist(broadcast.tc3())
|
||||||
|
|
||||||
|
|
||||||
#add_tc_2_runlist(sync.tc1())
|
#add_tc_2_runlist(sync.tc1())
|
||||||
#add_tc_2_runlist(sync.tc2())
|
#add_tc_2_runlist(sync.tc2())
|
||||||
#add_tc_2_runlist(sync.tc3())
|
#add_tc_2_runlist(sync.tc3())
|
||||||
#add_tc_2_runlist(sync.tc4())
|
#add_tc_2_runlist(sync.tc4())
|
||||||
#add_tc_2_runlist(sync.tc5())
|
#add_tc_2_runlist(sync.tc5())
|
||||||
#add_tc_2_runlist(sync.tc6())
|
#add_tc_2_runlist(sync.tc6())
|
||||||
#add_tc_2_runlist(sync.tc7())
|
#add_tc_2_runlist(sync.tc7())
|
||||||
|
|
||||||
#add_tc_2_runlist(ebmmu.tc1())
|
#add_tc_2_runlist(ebmmu.tc1())
|
||||||
#add_tc_2_runlist(ebmmu.tc2())
|
#add_tc_2_runlist(ebmmu.tc2())
|
||||||
#add_tc_2_runlist(ebmmu.tc3())
|
#add_tc_2_runlist(ebmmu.tc3())
|
||||||
#add_tc_2_runlist(ebmmu.tc4())
|
#add_tc_2_runlist(ebmmu.tc4())
|
||||||
#add_tc_2_runlist(ebmmu.tc5())
|
#add_tc_2_runlist(ebmmu.tc5())
|
||||||
#add_tc_2_runlist(ebmmu.tc6())
|
#add_tc_2_runlist(ebmmu.tc6())
|
||||||
#add_tc_2_runlist(ebmmu.tc7())
|
#add_tc_2_runlist(ebmmu.tc7())
|
||||||
#add_tc_2_runlist(ebmmu.tc8())
|
#add_tc_2_runlist(ebmmu.tc8())
|
||||||
#add_tc_2_runlist(ebmmu.tc9())
|
#add_tc_2_runlist(ebmmu.tc9())
|
||||||
#add_tc_2_runlist(ebmmu.tc10())
|
#add_tc_2_runlist(ebmmu.tc10())
|
||||||
#add_tc_2_runlist(ebmmu.tc11())
|
#add_tc_2_runlist(ebmmu.tc11())
|
||||||
#add_tc_2_runlist(ebmmu.tc12())
|
#add_tc_2_runlist(ebmmu.tc12())
|
||||||
#add_tc_2_runlist(ebmmu.tc13())
|
#add_tc_2_runlist(ebmmu.tc13())
|
||||||
#add_tc_2_runlist(ebmmu.tc14())
|
#add_tc_2_runlist(ebmmu.tc14())
|
||||||
#add_tc_2_runlist(ebmmu.tc15())
|
#add_tc_2_runlist(ebmmu.tc15())
|
||||||
#add_tc_2_runlist(ebmmu.tc16())
|
#add_tc_2_runlist(ebmmu.tc16())
|
||||||
#add_tc_2_runlist(ebmmu.tc17())
|
#add_tc_2_runlist(ebmmu.tc17())
|
||||||
#add_tc_2_runlist(ebmmu.tc18())
|
#add_tc_2_runlist(ebmmu.tc18())
|
||||||
#add_tc_2_runlist(ebmmu.tc19())
|
#add_tc_2_runlist(ebmmu.tc19())
|
||||||
|
|
||||||
#add_tc_2_runlist(watchdog.tc1())
|
#add_tc_2_runlist(watchdog.tc1())
|
||||||
#add_tc_2_runlist(watchdog.tc2())
|
#add_tc_2_runlist(watchdog.tc2())
|
||||||
|
|
||||||
#add_tc_2_runlist(mac.tc1())
|
#add_tc_2_runlist(mac.tc1())
|
||||||
#add_tc_2_runlist(mac.tc2())
|
#add_tc_2_runlist(mac.tc2())
|
||||||
#add_tc_2_runlist(mac.tc3())
|
#add_tc_2_runlist(mac.tc3())
|
||||||
#add_tc_2_runlist(mac.tc4())
|
#add_tc_2_runlist(mac.tc4())
|
||||||
#add_tc_2_runlist(mac.tc5())
|
#add_tc_2_runlist(mac.tc5())
|
||||||
#add_tc_2_runlist(mac.tc6())
|
#add_tc_2_runlist(mac.tc6())
|
||||||
#add_tc_2_runlist(mac.tc7())
|
#add_tc_2_runlist(mac.tc7())
|
||||||
|
|
||||||
environment.teardown()
|
environment.teardown()
|
||||||
|
|
||||||
gen_tc_runlist()
|
gen_tc_runlist()
|
||||||
|
|
||||||
|
|||||||
@@ -1,140 +1,140 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
from pyutils import *
|
from pyutils import *
|
||||||
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac, manydev
|
from testcase import environment, rwregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac, manydev
|
||||||
|
|
||||||
if __name__ == '__main__':
|
if __name__ == '__main__':
|
||||||
environment.gen_slv_dev_num(200)
|
environment.gen_slv_dev_num(200)
|
||||||
environment.bringup()
|
environment.bringup()
|
||||||
|
|
||||||
|
|
||||||
add_tc_2_runlist(manydev.tc1())
|
add_tc_2_runlist(manydev.tc1())
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(errorPkt.tc1())
|
add_tc_2_runlist(errorPkt.tc1())
|
||||||
add_tc_2_runlist(errorPkt.tc2())
|
add_tc_2_runlist(errorPkt.tc2())
|
||||||
add_tc_2_runlist(errorPkt.tc3())
|
add_tc_2_runlist(errorPkt.tc3())
|
||||||
add_tc_2_runlist(errorPkt.tc4())
|
add_tc_2_runlist(errorPkt.tc4())
|
||||||
add_tc_2_runlist(errorPkt.tc5())
|
add_tc_2_runlist(errorPkt.tc5())
|
||||||
add_tc_2_runlist(errorPkt.tc6())
|
add_tc_2_runlist(errorPkt.tc6())
|
||||||
add_tc_2_runlist(errorPkt.tc7())
|
add_tc_2_runlist(errorPkt.tc7())
|
||||||
add_tc_2_runlist(errorPkt.tc8())
|
add_tc_2_runlist(errorPkt.tc8())
|
||||||
add_tc_2_runlist(errorPkt.tc9())
|
add_tc_2_runlist(errorPkt.tc9())
|
||||||
add_tc_2_runlist(errorPkt.tc10())
|
add_tc_2_runlist(errorPkt.tc10())
|
||||||
add_tc_2_runlist(errorPkt.tc11())
|
add_tc_2_runlist(errorPkt.tc11())
|
||||||
add_tc_2_runlist(errorPkt.tc12())
|
add_tc_2_runlist(errorPkt.tc12())
|
||||||
add_tc_2_runlist(errorPkt.tc13())
|
add_tc_2_runlist(errorPkt.tc13())
|
||||||
add_tc_2_runlist(errorPkt.tc14())
|
add_tc_2_runlist(errorPkt.tc14())
|
||||||
add_tc_2_runlist(errorPkt.tc15())
|
add_tc_2_runlist(errorPkt.tc15())
|
||||||
add_tc_2_runlist(errorPkt.tc16())
|
add_tc_2_runlist(errorPkt.tc16())
|
||||||
add_tc_2_runlist(errorPkt.tc17())
|
add_tc_2_runlist(errorPkt.tc17())
|
||||||
add_tc_2_runlist(errorPkt.tc18())
|
add_tc_2_runlist(errorPkt.tc18())
|
||||||
add_tc_2_runlist(errorPkt.tc19())
|
add_tc_2_runlist(errorPkt.tc19())
|
||||||
add_tc_2_runlist(errorPkt.tc20())
|
add_tc_2_runlist(errorPkt.tc20())
|
||||||
add_tc_2_runlist(errorPkt.tc21())
|
add_tc_2_runlist(errorPkt.tc21())
|
||||||
add_tc_2_runlist(errorPkt.tc22())
|
add_tc_2_runlist(errorPkt.tc22())
|
||||||
add_tc_2_runlist(errorPkt.tc23())
|
add_tc_2_runlist(errorPkt.tc23())
|
||||||
add_tc_2_runlist(errorPkt.tc24())
|
add_tc_2_runlist(errorPkt.tc24())
|
||||||
add_tc_2_runlist(errorPkt.tc25())
|
add_tc_2_runlist(errorPkt.tc25())
|
||||||
add_tc_2_runlist(errorPkt.tc26())
|
add_tc_2_runlist(errorPkt.tc26())
|
||||||
add_tc_2_runlist(errorPkt.tc27())
|
add_tc_2_runlist(errorPkt.tc27())
|
||||||
add_tc_2_runlist(errorPkt.tc28())
|
add_tc_2_runlist(errorPkt.tc28())
|
||||||
add_tc_2_runlist(errorPkt.tc29())
|
add_tc_2_runlist(errorPkt.tc29())
|
||||||
add_tc_2_runlist(errorPkt.tc30())
|
add_tc_2_runlist(errorPkt.tc30())
|
||||||
add_tc_2_runlist(errorPkt.tc31())
|
add_tc_2_runlist(errorPkt.tc31())
|
||||||
add_tc_2_runlist(errorPkt.tc32())
|
add_tc_2_runlist(errorPkt.tc32())
|
||||||
add_tc_2_runlist(errorPkt.tc33())
|
add_tc_2_runlist(errorPkt.tc33())
|
||||||
add_tc_2_runlist(errorPkt.tc34())
|
add_tc_2_runlist(errorPkt.tc34())
|
||||||
add_tc_2_runlist(errorPkt.tc35())
|
add_tc_2_runlist(errorPkt.tc35())
|
||||||
add_tc_2_runlist(errorPkt.tc36())
|
add_tc_2_runlist(errorPkt.tc36())
|
||||||
add_tc_2_runlist(errorPkt.tc37())
|
add_tc_2_runlist(errorPkt.tc37())
|
||||||
add_tc_2_runlist(errorPkt.tc38())
|
add_tc_2_runlist(errorPkt.tc38())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(base.tc1())
|
add_tc_2_runlist(base.tc1())
|
||||||
add_tc_2_runlist(base.tc2())
|
add_tc_2_runlist(base.tc2())
|
||||||
add_tc_2_runlist(base.tc3())
|
add_tc_2_runlist(base.tc3())
|
||||||
add_tc_2_runlist(base.tc4())
|
add_tc_2_runlist(base.tc4())
|
||||||
add_tc_2_runlist(base.tc5())
|
add_tc_2_runlist(base.tc5())
|
||||||
add_tc_2_runlist(base.tc6())
|
add_tc_2_runlist(base.tc6())
|
||||||
add_tc_2_runlist(base.tc7())
|
add_tc_2_runlist(base.tc7())
|
||||||
add_tc_2_runlist(base.tc8())
|
add_tc_2_runlist(base.tc8())
|
||||||
add_tc_2_runlist(base.tc9())
|
add_tc_2_runlist(base.tc9())
|
||||||
add_tc_2_runlist(base.tc10())
|
add_tc_2_runlist(base.tc10())
|
||||||
add_tc_2_runlist(base.tc11())
|
add_tc_2_runlist(base.tc11())
|
||||||
add_tc_2_runlist(base.tc12())
|
add_tc_2_runlist(base.tc12())
|
||||||
add_tc_2_runlist(base.tc13())
|
add_tc_2_runlist(base.tc13())
|
||||||
add_tc_2_runlist(base.tc14())
|
add_tc_2_runlist(base.tc14())
|
||||||
add_tc_2_runlist(base.tc15())
|
add_tc_2_runlist(base.tc15())
|
||||||
add_tc_2_runlist(base.tc16())
|
add_tc_2_runlist(base.tc16())
|
||||||
add_tc_2_runlist(base.tc17())
|
add_tc_2_runlist(base.tc17())
|
||||||
add_tc_2_runlist(base.tc18())
|
add_tc_2_runlist(base.tc18())
|
||||||
add_tc_2_runlist(base.tc19())
|
add_tc_2_runlist(base.tc19())
|
||||||
add_tc_2_runlist(base.tc20())
|
add_tc_2_runlist(base.tc20())
|
||||||
add_tc_2_runlist(base.tc21())
|
add_tc_2_runlist(base.tc21())
|
||||||
add_tc_2_runlist(base.tc22())
|
add_tc_2_runlist(base.tc22())
|
||||||
add_tc_2_runlist(base.tc23())
|
add_tc_2_runlist(base.tc23())
|
||||||
add_tc_2_runlist(base.tc24())
|
add_tc_2_runlist(base.tc24())
|
||||||
add_tc_2_runlist(base.tc25())
|
add_tc_2_runlist(base.tc25())
|
||||||
add_tc_2_runlist(base.tc26())
|
add_tc_2_runlist(base.tc26())
|
||||||
add_tc_2_runlist(base.tc27())
|
add_tc_2_runlist(base.tc27())
|
||||||
add_tc_2_runlist(base.tc28())
|
add_tc_2_runlist(base.tc28())
|
||||||
|
|
||||||
add_tc_2_runlist(base.tc29())
|
add_tc_2_runlist(base.tc29())
|
||||||
add_tc_2_runlist(base.tc30())
|
add_tc_2_runlist(base.tc30())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(broadcast.tc1())
|
add_tc_2_runlist(broadcast.tc1())
|
||||||
add_tc_2_runlist(broadcast.tc2())
|
add_tc_2_runlist(broadcast.tc2())
|
||||||
add_tc_2_runlist(broadcast.tc3())
|
add_tc_2_runlist(broadcast.tc3())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
|
|
||||||
#add_tc_2_runlist(sync.tc1())
|
#add_tc_2_runlist(sync.tc1())
|
||||||
#add_tc_2_runlist(sync.tc2())
|
#add_tc_2_runlist(sync.tc2())
|
||||||
#add_tc_2_runlist(sync.tc3())
|
#add_tc_2_runlist(sync.tc3())
|
||||||
#add_tc_2_runlist(sync.tc4())
|
#add_tc_2_runlist(sync.tc4())
|
||||||
#add_tc_2_runlist(sync.tc5())
|
#add_tc_2_runlist(sync.tc5())
|
||||||
#add_tc_2_runlist(sync.tc6())
|
#add_tc_2_runlist(sync.tc6())
|
||||||
#add_tc_2_runlist(sync.tc7())
|
#add_tc_2_runlist(sync.tc7())
|
||||||
|
|
||||||
'''
|
'''
|
||||||
add_tc_2_runlist(ebmmu.tc1())
|
add_tc_2_runlist(ebmmu.tc1())
|
||||||
add_tc_2_runlist(ebmmu.tc2())
|
add_tc_2_runlist(ebmmu.tc2())
|
||||||
add_tc_2_runlist(ebmmu.tc3())
|
add_tc_2_runlist(ebmmu.tc3())
|
||||||
add_tc_2_runlist(ebmmu.tc4())
|
add_tc_2_runlist(ebmmu.tc4())
|
||||||
add_tc_2_runlist(ebmmu.tc5())
|
add_tc_2_runlist(ebmmu.tc5())
|
||||||
add_tc_2_runlist(ebmmu.tc6())
|
add_tc_2_runlist(ebmmu.tc6())
|
||||||
add_tc_2_runlist(ebmmu.tc7())
|
add_tc_2_runlist(ebmmu.tc7())
|
||||||
add_tc_2_runlist(ebmmu.tc8())
|
add_tc_2_runlist(ebmmu.tc8())
|
||||||
add_tc_2_runlist(ebmmu.tc9())
|
add_tc_2_runlist(ebmmu.tc9())
|
||||||
add_tc_2_runlist(ebmmu.tc10())
|
add_tc_2_runlist(ebmmu.tc10())
|
||||||
add_tc_2_runlist(ebmmu.tc11())
|
add_tc_2_runlist(ebmmu.tc11())
|
||||||
add_tc_2_runlist(ebmmu.tc12())
|
add_tc_2_runlist(ebmmu.tc12())
|
||||||
add_tc_2_runlist(ebmmu.tc13())
|
add_tc_2_runlist(ebmmu.tc13())
|
||||||
add_tc_2_runlist(ebmmu.tc14())
|
add_tc_2_runlist(ebmmu.tc14())
|
||||||
add_tc_2_runlist(ebmmu.tc15())
|
add_tc_2_runlist(ebmmu.tc15())
|
||||||
add_tc_2_runlist(ebmmu.tc16())
|
add_tc_2_runlist(ebmmu.tc16())
|
||||||
add_tc_2_runlist(ebmmu.tc17())
|
add_tc_2_runlist(ebmmu.tc17())
|
||||||
add_tc_2_runlist(ebmmu.tc18())
|
add_tc_2_runlist(ebmmu.tc18())
|
||||||
add_tc_2_runlist(ebmmu.tc19())
|
add_tc_2_runlist(ebmmu.tc19())
|
||||||
#'''
|
#'''
|
||||||
|
|
||||||
#add_tc_2_runlist(watchdog.tc1())
|
#add_tc_2_runlist(watchdog.tc1())
|
||||||
#add_tc_2_runlist(watchdog.tc2())
|
#add_tc_2_runlist(watchdog.tc2())
|
||||||
|
|
||||||
#add_tc_2_runlist(mac.tc1())
|
#add_tc_2_runlist(mac.tc1())
|
||||||
#add_tc_2_runlist(mac.tc2())
|
#add_tc_2_runlist(mac.tc2())
|
||||||
#add_tc_2_runlist(mac.tc3())
|
#add_tc_2_runlist(mac.tc3())
|
||||||
#add_tc_2_runlist(mac.tc4())
|
#add_tc_2_runlist(mac.tc4())
|
||||||
#add_tc_2_runlist(mac.tc5())
|
#add_tc_2_runlist(mac.tc5())
|
||||||
#add_tc_2_runlist(mac.tc6())
|
#add_tc_2_runlist(mac.tc6())
|
||||||
#add_tc_2_runlist(mac.tc7())
|
#add_tc_2_runlist(mac.tc7())
|
||||||
|
|
||||||
environment.teardown()
|
environment.teardown()
|
||||||
|
|
||||||
gen_tc_runlist()
|
gen_tc_runlist()
|
||||||
|
|
||||||
|
|||||||
@@ -1,52 +1,52 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
import argparse
|
import argparse
|
||||||
from pyutils import *
|
from pyutils import *
|
||||||
|
|
||||||
|
|
||||||
def set_cdr_clk(v_ph, v_t):
|
def set_cdr_clk(v_ph, v_t):
|
||||||
ph = int(8 * 1000000 * (int(abs(v_ph))%360) / 360.0)
|
ph = int(8 * 1000000 * (int(abs(v_ph))%360) / 360.0)
|
||||||
period = int(1000000 + v_t)
|
period = int(1000000 + v_t)
|
||||||
code_for_clk = __gen_clk(ph, period)
|
code_for_clk = __gen_clk(ph, period)
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
gen_file_def = "simCdrClk"
|
gen_file_def = "simCdrClk"
|
||||||
genPkt.addAfterExc(code_for_clk)
|
genPkt.addAfterExc(code_for_clk)
|
||||||
genPkt.gen("./generated/SimCDR/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/SimCDR/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
def __gen_clk(ph, period):
|
def __gen_clk(ph, period):
|
||||||
slv_code =(
|
slv_code =(
|
||||||
""
|
""
|
||||||
#"\tinitial begin\n"
|
#"\tinitial begin\n"
|
||||||
#+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk)
|
#+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk)
|
||||||
#+"\tend\n\n"
|
#+"\tend\n\n"
|
||||||
|
|
||||||
+"\tgenerate\n"
|
+"\tgenerate\n"
|
||||||
+"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n"
|
+"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n"
|
||||||
+"\t\tinitial begin\n"
|
+"\t\tinitial begin\n"
|
||||||
+ "\t\t\t//相位信息\n"
|
+ "\t\t\t//相位信息\n"
|
||||||
+ "\t\t\t#%d\n"%(ph)
|
+ "\t\t\t#%d\n"%(ph)
|
||||||
+ "\t\t\tmultiCLK[i] = 0;\n"
|
+ "\t\t\tmultiCLK[i] = 0;\n"
|
||||||
+ "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n"
|
+ "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n"
|
||||||
+ "\t\t\t\t#%d\n"%(period, )
|
+ "\t\t\t\t#%d\n"%(period, )
|
||||||
+ "\t\t\t\t;\n"
|
+ "\t\t\t\t;\n"
|
||||||
+ "\t\t\tend\n"
|
+ "\t\t\tend\n"
|
||||||
+ "\t\t\tforever begin #%d multiCLK[i] <= ~multiCLK[i]; end\n"%(period * 8, )
|
+ "\t\t\tforever begin #%d multiCLK[i] <= ~multiCLK[i]; end\n"%(period * 8, )
|
||||||
+"\t\tend\n"
|
+"\t\tend\n"
|
||||||
+"\tend\n"
|
+"\tend\n"
|
||||||
+"\tendgenerate\n")
|
+"\tendgenerate\n")
|
||||||
|
|
||||||
return slv_code
|
return slv_code
|
||||||
|
|
||||||
if __name__ == '__main__':
|
if __name__ == '__main__':
|
||||||
|
|
||||||
parser = argparse.ArgumentParser()
|
parser = argparse.ArgumentParser()
|
||||||
|
|
||||||
# 可选参数
|
# 可选参数
|
||||||
parser.add_argument("-c", "--clk", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
parser.add_argument("-c", "--clk", nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
|
||||||
|
|
||||||
args = parser.parse_args()
|
args = parser.parse_args()
|
||||||
|
|
||||||
set_cdr_clk(args.clk[0], args.clk[1]);
|
set_cdr_clk(args.clk[0], args.clk[1]);
|
||||||
|
|
||||||
|
|||||||
@@ -1,411 +1,411 @@
|
|||||||
#!/usr/bin/env python
|
#!/usr/bin/env python
|
||||||
#encoding=utf-8
|
#encoding=utf-8
|
||||||
import copy
|
import copy
|
||||||
import random
|
import random
|
||||||
|
|
||||||
class GenPkt(object):
|
class GenPkt(object):
|
||||||
def __init__(self):
|
def __init__(self):
|
||||||
super(GenPkt, self).__init__()
|
super(GenPkt, self).__init__()
|
||||||
|
|
||||||
self.pkt_buf = list() #bytearray(b'\0' * 2048)
|
self.pkt_buf = list() #bytearray(b'\0' * 2048)
|
||||||
self.pkt_type = 0
|
self.pkt_type = 0
|
||||||
self.pkt_sub_pkt = 0
|
self.pkt_sub_pkt = 0
|
||||||
self.sub_pkt = list()
|
self.sub_pkt = list()
|
||||||
self.pkt_data = None
|
self.pkt_data = None
|
||||||
|
|
||||||
def clean(self):
|
def clean(self):
|
||||||
self.pkt_buf = list() #bytearray(b'\0' * 2048)
|
self.pkt_buf = list() #bytearray(b'\0' * 2048)
|
||||||
self.pkt_type = 0
|
self.pkt_type = 0
|
||||||
self.pkt_sub_pkt = 0
|
self.pkt_sub_pkt = 0
|
||||||
self.sub_pkt = list()
|
self.sub_pkt = list()
|
||||||
self.pkt_data = None
|
self.pkt_data = None
|
||||||
|
|
||||||
def setPktType(self, type):
|
def setPktType(self, type):
|
||||||
if (type != 0) and (type != 1):
|
if (type != 0) and (type != 1):
|
||||||
print('Error...set type failed:', type)
|
print('Error...set type failed:', type)
|
||||||
else:
|
else:
|
||||||
self.pkt_type = type
|
self.pkt_type = type
|
||||||
|
|
||||||
def setPkt(self, type, data = None):
|
def setPkt(self, type, data = None):
|
||||||
if (type != 0) and (type != 1):
|
if (type != 0) and (type != 1):
|
||||||
if type == 2:
|
if type == 2:
|
||||||
self.pkt_type = 2
|
self.pkt_type = 2
|
||||||
self.pkt_data = copy.copy(data)
|
self.pkt_data = copy.copy(data)
|
||||||
else:
|
else:
|
||||||
print('Error...set type failed:', type)
|
print('Error...set type failed:', type)
|
||||||
else:
|
else:
|
||||||
self.pkt_type = type
|
self.pkt_type = type
|
||||||
|
|
||||||
def addBeforeExc(self, str):
|
def addBeforeExc(self, str):
|
||||||
self.sub_pkt.append([1, str])
|
self.sub_pkt.append([1, str])
|
||||||
|
|
||||||
def addAfterExc(self, str):
|
def addAfterExc(self, str):
|
||||||
self.sub_pkt.append([2, str])
|
self.sub_pkt.append([2, str])
|
||||||
|
|
||||||
def addSubPkt(self, dev_idx, ptype, addr, cmd, len, data):
|
def addSubPkt(self, dev_idx, ptype, addr, cmd, len, data):
|
||||||
if (len > 2032):
|
if (len > 2032):
|
||||||
print('Error, bad subpkt len:%d', len)
|
print('Error, bad subpkt len:%d', len)
|
||||||
return
|
return
|
||||||
if not (ptype in [0, 2]):
|
if not (ptype in [0, 2]):
|
||||||
print('Error, bad subpkt type:', ptype)
|
print('Error, bad subpkt type:', ptype)
|
||||||
return
|
return
|
||||||
if not (cmd in [0, 1, 2, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf]):
|
if not (cmd in [0, 1, 2, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf]):
|
||||||
print('Error, bad cmd:', cmd)
|
print('Error, bad cmd:', cmd)
|
||||||
return
|
return
|
||||||
|
|
||||||
self.pkt_sub_pkt = self.pkt_sub_pkt + 1
|
self.pkt_sub_pkt = self.pkt_sub_pkt + 1
|
||||||
self.sub_pkt.append([0, dev_idx, ptype, addr, cmd, len, data])
|
self.sub_pkt.append([0, dev_idx, ptype, addr, cmd, len, data])
|
||||||
|
|
||||||
def gen(self, filename="pkt_verilog_test.v", filetype=0, appendgen=False, gen_name=None):
|
def gen(self, filename="pkt_verilog_test.v", filetype=0, appendgen=False, gen_name=None):
|
||||||
gen_pkt_type = 0
|
gen_pkt_type = 0
|
||||||
pkt_len = 4
|
pkt_len = 4
|
||||||
for sp in self.sub_pkt:
|
for sp in self.sub_pkt:
|
||||||
if sp[0] != 0:
|
if sp[0] != 0:
|
||||||
pass
|
pass
|
||||||
else:
|
else:
|
||||||
pkt_len = pkt_len + sp[5] + 8
|
pkt_len = pkt_len + sp[5] + 8
|
||||||
|
|
||||||
if pkt_len > 2044:
|
if pkt_len > 2044:
|
||||||
print('Error, bad pkt_len:', pkt_len)
|
print('Error, bad pkt_len:', pkt_len)
|
||||||
return
|
return
|
||||||
|
|
||||||
i = 4
|
i = 4
|
||||||
if (self.pkt_type == 1):
|
if (self.pkt_type == 1):
|
||||||
pkt_len = 4
|
pkt_len = 4
|
||||||
'''
|
'''
|
||||||
self.pkt_buf[0] = 0
|
self.pkt_buf[0] = 0
|
||||||
self.pkt_buf[1] = (self.pkt_type & 0x3)
|
self.pkt_buf[1] = (self.pkt_type & 0x3)
|
||||||
self.pkt_buf[2] = 0x3f
|
self.pkt_buf[2] = 0x3f
|
||||||
self.pkt_buf[3] = 0xff
|
self.pkt_buf[3] = 0xff
|
||||||
'''
|
'''
|
||||||
self.pkt_buf.append(0)
|
self.pkt_buf.append(0)
|
||||||
self.pkt_buf.append(self.pkt_type & 0x3)
|
self.pkt_buf.append(self.pkt_type & 0x3)
|
||||||
self.pkt_buf.append(0x3f)
|
self.pkt_buf.append(0x3f)
|
||||||
self.pkt_buf.append(0xff)
|
self.pkt_buf.append(0xff)
|
||||||
gen_pkt_type = 1
|
gen_pkt_type = 1
|
||||||
elif (self.pkt_type == 2):
|
elif (self.pkt_type == 2):
|
||||||
pkt_len = len(self.pkt_data)
|
pkt_len = len(self.pkt_data)
|
||||||
|
|
||||||
for d in self.pkt_data:
|
for d in self.pkt_data:
|
||||||
self.pkt_buf.append(d)
|
self.pkt_buf.append(d)
|
||||||
i = pkt_len
|
i = pkt_len
|
||||||
gen_pkt_type = 2
|
gen_pkt_type = 2
|
||||||
#print("-----------------------------", filename, self.pkt_type, pkt_len, self.pkt_buf)
|
#print("-----------------------------", filename, self.pkt_type, pkt_len, self.pkt_buf)
|
||||||
else:
|
else:
|
||||||
#for i in range(pkt_len):
|
#for i in range(pkt_len):
|
||||||
'''
|
'''
|
||||||
self.pkt_buf[0] = ((pkt_len - 4) >> 4) & 0xff
|
self.pkt_buf[0] = ((pkt_len - 4) >> 4) & 0xff
|
||||||
self.pkt_buf[1] = (((pkt_len - 4) << 4) & 0xf0) | (self.pkt_type & 0x3)
|
self.pkt_buf[1] = (((pkt_len - 4) << 4) & 0xf0) | (self.pkt_type & 0x3)
|
||||||
self.pkt_buf[2] = 0
|
self.pkt_buf[2] = 0
|
||||||
self.pkt_buf[3] = 0
|
self.pkt_buf[3] = 0
|
||||||
'''
|
'''
|
||||||
self.pkt_buf.append(((pkt_len - 4) >> 4) & 0xff)
|
self.pkt_buf.append(((pkt_len - 4) >> 4) & 0xff)
|
||||||
self.pkt_buf.append((((pkt_len - 4) << 4) & 0xf0) | (self.pkt_type & 0x3))
|
self.pkt_buf.append((((pkt_len - 4) << 4) & 0xf0) | (self.pkt_type & 0x3))
|
||||||
self.pkt_buf.append(0)
|
self.pkt_buf.append(0)
|
||||||
self.pkt_buf.append(0)
|
self.pkt_buf.append(0)
|
||||||
|
|
||||||
for sp in self.sub_pkt:
|
for sp in self.sub_pkt:
|
||||||
if sp[0] != 0:
|
if sp[0] != 0:
|
||||||
pass
|
pass
|
||||||
#elif sp[0] == 0:
|
#elif sp[0] == 0:
|
||||||
else:
|
else:
|
||||||
gen_pkt_type = 3
|
gen_pkt_type = 3
|
||||||
#设备索引(14bit)+类型(2bit)
|
#设备索引(14bit)+类型(2bit)
|
||||||
temp = ((sp[1] & 0x3fff) << 2) | (sp[2] & 0x3)
|
temp = ((sp[1] & 0x3fff) << 2) | (sp[2] & 0x3)
|
||||||
|
|
||||||
#self.pkt_buf[i] = (temp >> 8) & 0xff
|
#self.pkt_buf[i] = (temp >> 8) & 0xff
|
||||||
self.pkt_buf.append((temp >> 8) & 0xff)
|
self.pkt_buf.append((temp >> 8) & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
#self.pkt_buf[i] = temp & 0xff
|
#self.pkt_buf[i] = temp & 0xff
|
||||||
self.pkt_buf.append(temp & 0xff)
|
self.pkt_buf.append(temp & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
|
|
||||||
#地址
|
#地址
|
||||||
#self.pkt_buf[i] = (sp[3] >> 8) & 0xff
|
#self.pkt_buf[i] = (sp[3] >> 8) & 0xff
|
||||||
self.pkt_buf.append((sp[3] >> 8) & 0xff)
|
self.pkt_buf.append((sp[3] >> 8) & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
#self.pkt_buf[i] = sp[3] & 0xff
|
#self.pkt_buf[i] = sp[3] & 0xff
|
||||||
self.pkt_buf.append(sp[3] & 0xff)
|
self.pkt_buf.append(sp[3] & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
|
|
||||||
#命令类型(4bit)+长度(12bit)
|
#命令类型(4bit)+长度(12bit)
|
||||||
temp = (sp[4] << 12) | (sp[5] & 0xfff)
|
temp = (sp[4] << 12) | (sp[5] & 0xfff)
|
||||||
|
|
||||||
#self.pkt_buf[i] = (temp >> 8) & 0xff
|
#self.pkt_buf[i] = (temp >> 8) & 0xff
|
||||||
self.pkt_buf.append((temp >> 8) & 0xff)
|
self.pkt_buf.append((temp >> 8) & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
#self.pkt_buf[i] = temp & 0xff
|
#self.pkt_buf[i] = temp & 0xff
|
||||||
self.pkt_buf.append(temp & 0xff)
|
self.pkt_buf.append(temp & 0xff)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
|
|
||||||
#数据
|
#数据
|
||||||
if sp[6] == None:
|
if sp[6] == None:
|
||||||
#for _k in range(sp[5]):
|
#for _k in range(sp[5]):
|
||||||
# #self.pkt_buf[_k + i] = random.randint(0, 255)
|
# #self.pkt_buf[_k + i] = random.randint(0, 255)
|
||||||
# self.pkt_buf.append(random.randint(0, 255))
|
# self.pkt_buf.append(random.randint(0, 255))
|
||||||
temp = list(range(sp[5]))
|
temp = list(range(sp[5]))
|
||||||
temp = [(i & 0xff) for i in temp]
|
temp = [(i & 0xff) for i in temp]
|
||||||
self.pkt_buf = self.pkt_buf + temp
|
self.pkt_buf = self.pkt_buf + temp
|
||||||
else:
|
else:
|
||||||
for _k in range(sp[5]):
|
for _k in range(sp[5]):
|
||||||
#self.pkt_buf[_k + i] = sp[6][_k]
|
#self.pkt_buf[_k + i] = sp[6][_k]
|
||||||
self.pkt_buf.append(sp[6][_k])
|
self.pkt_buf.append(sp[6][_k])
|
||||||
|
|
||||||
i = i + sp[5]
|
i = i + sp[5]
|
||||||
|
|
||||||
#工作计数
|
#工作计数
|
||||||
#self.pkt_buf[i] = 0
|
#self.pkt_buf[i] = 0
|
||||||
self.pkt_buf.append(0)
|
self.pkt_buf.append(0)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
#self.pkt_buf[i] = 0
|
#self.pkt_buf[i] = 0
|
||||||
self.pkt_buf.append(0)
|
self.pkt_buf.append(0)
|
||||||
i = i + 1
|
i = i + 1
|
||||||
|
|
||||||
#print("pkt_len:%d, data_len:%d"%(pkt_len, pkt_len - 4))
|
#print("pkt_len:%d, data_len:%d"%(pkt_len, pkt_len - 4))
|
||||||
open_mode = "wt+"
|
open_mode = "wt+"
|
||||||
if appendgen:
|
if appendgen:
|
||||||
open_mode = "at"
|
open_mode = "at"
|
||||||
f = open(filename, open_mode)
|
f = open(filename, open_mode)
|
||||||
if filetype == 1:
|
if filetype == 1:
|
||||||
for md in self.sub_pkt:
|
for md in self.sub_pkt:
|
||||||
if md[0] == 1:
|
if md[0] == 1:
|
||||||
f.write("%s\n"%(md[1],))
|
f.write("%s\n"%(md[1],))
|
||||||
define_str = "`define DEF_"
|
define_str = "`define DEF_"
|
||||||
|
|
||||||
if appendgen and (gen_name == None):
|
if appendgen and (gen_name == None):
|
||||||
print("Error, gen_name not define.")
|
print("Error, gen_name not define.")
|
||||||
raise "Error, gen_name not define."
|
raise "Error, gen_name not define."
|
||||||
|
|
||||||
if not appendgen:
|
if not appendgen:
|
||||||
pos1 = filename.rfind("/")
|
pos1 = filename.rfind("/")
|
||||||
if (pos1 < -1):
|
if (pos1 < -1):
|
||||||
pos1 = 0
|
pos1 = 0
|
||||||
else:
|
else:
|
||||||
pos1 = pos1 + 1
|
pos1 = pos1 + 1
|
||||||
|
|
||||||
pos2 = filename.rfind(".")
|
pos2 = filename.rfind(".")
|
||||||
if (pos1 > pos2):
|
if (pos1 > pos2):
|
||||||
define_str = define_str + filename[pos1:]
|
define_str = define_str + filename[pos1:]
|
||||||
else:
|
else:
|
||||||
define_str = define_str + filename[pos1:pos2]
|
define_str = define_str + filename[pos1:pos2]
|
||||||
else:
|
else:
|
||||||
define_str = define_str + gen_name
|
define_str = define_str + gen_name
|
||||||
|
|
||||||
if gen_pkt_type != 0:
|
if gen_pkt_type != 0:
|
||||||
f.write(define_str + "_len \t%d\n"%(pkt_len))
|
f.write(define_str + "_len \t%d\n"%(pkt_len))
|
||||||
f.write(define_str + "_sm(array) \\\n\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\\\n\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(
|
f.write(define_str + "_sm(array) \\\n\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\\\n\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(
|
||||||
0, pkt_len & 0xff,
|
0, pkt_len & 0xff,
|
||||||
1, pkt_len >> 8
|
1, pkt_len >> 8
|
||||||
))
|
))
|
||||||
|
|
||||||
f.write(define_str + "(array) \\\n")
|
f.write(define_str + "(array) \\\n")
|
||||||
for _k in range(i):
|
for _k in range(i):
|
||||||
if _k < (i - 1):
|
if _k < (i - 1):
|
||||||
if type(self.pkt_buf[_k]) == int:
|
if type(self.pkt_buf[_k]) == int:
|
||||||
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\\\n"%(_k, self.pkt_buf[_k]))
|
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\\\n"%(_k, self.pkt_buf[_k]))
|
||||||
else:
|
else:
|
||||||
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=%s;\\\n"%(_k, self.pkt_buf[_k]))
|
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=%s;\\\n"%(_k, self.pkt_buf[_k]))
|
||||||
else:
|
else:
|
||||||
if type(self.pkt_buf[_k]) == int:
|
if type(self.pkt_buf[_k]) == int:
|
||||||
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(_k, self.pkt_buf[_k]))
|
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(_k, self.pkt_buf[_k]))
|
||||||
else:
|
else:
|
||||||
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=%s;\n"%(_k, self.pkt_buf[_k]))
|
f.write("\tarray``[`ARRAY_IDX_OFF + %d]=%s;\n"%(_k, self.pkt_buf[_k]))
|
||||||
|
|
||||||
for md in self.sub_pkt:
|
for md in self.sub_pkt:
|
||||||
if md[0] == 2:
|
if md[0] == 2:
|
||||||
f.write("%s\n"%(md[1],))
|
f.write("%s\n"%(md[1],))
|
||||||
else:
|
else:
|
||||||
for _k in range(i):
|
for _k in range(i):
|
||||||
f.write("txBuf[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(_k, self.pkt_buf[_k]))
|
f.write("txBuf[`ARRAY_IDX_OFF + %d]=8'h%02X;\n"%(_k, self.pkt_buf[_k]))
|
||||||
f.close()
|
f.close()
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
def genWriteTransLenCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
def genWriteTransLenCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
||||||
return '''\n//写入发送长度\n'''\
|
return '''\n//写入发送长度\n'''\
|
||||||
+ '''$fdisplay(spidata_file, "--写数据交换长度");\n'''\
|
+ '''$fdisplay(spidata_file, "--写数据交换长度");\n'''\
|
||||||
+ '''`DEF_%s_sm(txBuf);\n'''%(gen_name, )\
|
+ '''`DEF_%s_sm(txBuf);\n'''%(gen_name, )\
|
||||||
+ '''%s( (`MST_TX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, dev_idx)\
|
+ '''%s( (`MST_TX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, dev_idx)\
|
||||||
+ '''%s( (`MST_RX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, dev_idx)
|
+ '''%s( (`MST_RX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, dev_idx)
|
||||||
|
|
||||||
def genWriteTransPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
def genWriteTransPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
||||||
return f'''\n$fdisplay(spidata_file, "<<准备发包，使用SM{sm_idx}：");\n'''\
|
return f'''\n$fdisplay(spidata_file, "<<准备发包，使用SM{sm_idx}：");\n'''\
|
||||||
+ '''`DEF_%s(txBuf);\n'''%(gen_name, )\
|
+ '''`DEF_%s(txBuf);\n'''%(gen_name, )\
|
||||||
+ '''%s( (`MST_TX%d_ADDR), (`SPI_WRITE), (`DEF_%s_len), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, gen_name, dev_idx)
|
+ '''%s( (`MST_TX%d_ADDR), (`SPI_WRITE), (`DEF_%s_len), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, gen_name, dev_idx)
|
||||||
|
|
||||||
def genTrgTransPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
def genTrgTransPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
||||||
return '''\n//请求发送\n'''\
|
return '''\n//请求发送\n'''\
|
||||||
+ '''$fdisplay(spidata_file, "--请求发送");\n'''\
|
+ '''$fdisplay(spidata_file, "--请求发送");\n'''\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF] = `MST_TX_TRIGGER(%d);\n'''%(sm_idx, )\
|
+ '''txBuf[`ARRAY_IDX_OFF] = `MST_TX_TRIGGER(%d);\n'''%(sm_idx, )\
|
||||||
+ '''%s( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
+ '''%s( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
||||||
|
|
||||||
def genReadAckPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
def genReadAckPktCode(gen_name, sm_idx, wlog=True, dev_idx=0):
|
||||||
return '''\n//等待回包\n'''\
|
return '''\n//等待回包\n'''\
|
||||||
+ '''wait_comm_finished(`IF_IDX(%d));\n'''%(dev_idx, )\
|
+ '''wait_comm_finished(`IF_IDX(%d));\n'''%(dev_idx, )\
|
||||||
+ f'''$fdisplay(spidata_file, ">>读取回包，使用SM{sm_idx}：");\n'''\
|
+ f'''$fdisplay(spidata_file, ">>读取回包，使用SM{sm_idx}：");\n'''\
|
||||||
+ '''%s( (`MST_RX%d_ADDR), (`SPI_READ), (`DEF_%s_len), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, gen_name, dev_idx)
|
+ '''%s( (`MST_RX%d_ADDR), (`SPI_READ), (`DEF_%s_len), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", sm_idx, gen_name, dev_idx)
|
||||||
|
|
||||||
def genEnableInsertTimeCode(pos, enableTime=True, enableDelay=True, wlog=True, dev_idx=0):
|
def genEnableInsertTimeCode(pos, enableTime=True, enableDelay=True, wlog=True, dev_idx=0):
|
||||||
data = pos & 0x3fff
|
data = pos & 0x3fff
|
||||||
if enableTime:
|
if enableTime:
|
||||||
data = data | 0x8000
|
data = data | 0x8000
|
||||||
if enableDelay:
|
if enableDelay:
|
||||||
data = data | 0x4000
|
data = data | 0x4000
|
||||||
return '''//写入替换时间戳替换地址\n'''\
|
return '''//写入替换时间戳替换地址\n'''\
|
||||||
+ '''$fdisplay(spidata_file, "--增加时间戳插入");\n'''\
|
+ '''$fdisplay(spidata_file, "--增加时间戳插入");\n'''\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h%x;\n'''%(data & 0xff, )\
|
+ '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h%x;\n'''%(data & 0xff, )\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h%x;\n'''%((data >> 8) & 0xff, )\
|
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h%x;\n'''%((data >> 8) & 0xff, )\
|
||||||
+ '''%s( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
+ '''%s( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
||||||
|
|
||||||
def genDisableInsertTimeCode(wlog=True, dev_idx=0):
|
def genDisableInsertTimeCode(wlog=True, dev_idx=0):
|
||||||
return '''\n//清除替换时间戳替换地址\n'''\
|
return '''\n//清除替换时间戳替换地址\n'''\
|
||||||
+ '''$fdisplay(spidata_file, "--清除时间戳插入");\n'''\
|
+ '''$fdisplay(spidata_file, "--清除时间戳插入");\n'''\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h00;\n'''\
|
+ '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h00;\n'''\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h00;\n'''\
|
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h00;\n'''\
|
||||||
+ '''%s( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(%d)) ); //清除替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
+ '''%s( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(%d)) ); //清除替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
||||||
|
|
||||||
def genCheckInsertTimeCode(wlog=True, dev_idx=0):
|
def genCheckInsertTimeCode(wlog=True, dev_idx=0):
|
||||||
return '''\n//检查替换时间戳替换地址\n'''\
|
return '''\n//检查替换时间戳替换地址\n'''\
|
||||||
+ '''$fdisplay(spidata_file, "--检查时间戳插入");\n'''\
|
+ '''$fdisplay(spidata_file, "--检查时间戳插入");\n'''\
|
||||||
+ '''%s( (16'h24), (`SPI_READ), (2), (`IF_IDX(%d)) ); //检查替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
+ '''%s( (16'h24), (`SPI_READ), (2), (`IF_IDX(%d)) ); //检查替换时间戳替换地址寄存器\n'''%("`SPI_TRANS" if wlog else "spi_trans", dev_idx)
|
||||||
|
|
||||||
|
|
||||||
def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None, wlog=True, iface=4):
|
def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None, wlog=True, iface=4):
|
||||||
spi_api="IF_IDX"
|
spi_api="IF_IDX"
|
||||||
spi_offset = "`ARRAY_IDX_OFF"
|
spi_offset = "`ARRAY_IDX_OFF"
|
||||||
if iface == 0:
|
if iface == 0:
|
||||||
spi_api = "IF_IQSPI"
|
spi_api = "IF_IQSPI"
|
||||||
spi_offset = "3"
|
spi_offset = "3"
|
||||||
elif iface == 1:
|
elif iface == 1:
|
||||||
spi_api = "IF_OSPI"
|
spi_api = "IF_OSPI"
|
||||||
spi_offset = "3"
|
spi_offset = "3"
|
||||||
elif iface == 2:
|
elif iface == 2:
|
||||||
spi_api = "IF_OQSPI"
|
spi_api = "IF_OQSPI"
|
||||||
spi_offset = "3"
|
spi_offset = "3"
|
||||||
elif iface == 3:
|
elif iface == 3:
|
||||||
spi_api = "IF_AQSPI"
|
spi_api = "IF_AQSPI"
|
||||||
spi_offset = "4"
|
spi_offset = "4"
|
||||||
else:
|
else:
|
||||||
spi_api = "IF_IDX"
|
spi_api = "IF_IDX"
|
||||||
spi_offset = "`ARRAY_IDX_OFF"
|
spi_offset = "`ARRAY_IDX_OFF"
|
||||||
|
|
||||||
if isWrite == True:
|
if isWrite == True:
|
||||||
if (data == None) or (len(data) == 0):
|
if (data == None) or (len(data) == 0):
|
||||||
data=list()
|
data=list()
|
||||||
|
|
||||||
code = ''
|
code = ''
|
||||||
idx = 0
|
idx = 0
|
||||||
for item in data:
|
for item in data:
|
||||||
code = code + '''txBuf[%s+%d]=8'h%02x;\n'''%(spi_offset, idx, item & 0xff)
|
code = code + '''txBuf[%s+%d]=8'h%02x;\n'''%(spi_offset, idx, item & 0xff)
|
||||||
idx = idx + 1
|
idx = idx + 1
|
||||||
|
|
||||||
code = code + '''%s( (16'h%04x), (`SPI_WRITE), (%d), (`%s(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", addr, data_len, spi_api, dev)
|
code = code + '''%s( (16'h%04x), (`SPI_WRITE), (%d), (`%s(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", addr, data_len, spi_api, dev)
|
||||||
return code
|
return code
|
||||||
else:
|
else:
|
||||||
code = ''
|
code = ''
|
||||||
code = code + '''%s( (16'h%04x), (`SPI_READ), (%d), (`%s(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", addr, data_len, spi_api, dev)
|
code = code + '''%s( (16'h%04x), (`SPI_READ), (%d), (`%s(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", addr, data_len, spi_api, dev)
|
||||||
return code
|
return code
|
||||||
|
|
||||||
def genSlvSMWriteData(dev, sm, data_len, data = None, wlog=True):
|
def genSlvSMWriteData(dev, sm, data_len, data = None, wlog=True):
|
||||||
smaddr = list()
|
smaddr = list()
|
||||||
for i in range(8):
|
for i in range(8):
|
||||||
smaddr.append(0x300 + i * 4 + 2)
|
smaddr.append(0x300 + i * 4 + 2)
|
||||||
if not ((sm == 1) or (sm == 3) or (sm == 5) or (sm == 7)):
|
if not ((sm == 1) or (sm == 3) or (sm == 5) or (sm == 7)):
|
||||||
#写入数据，lvds读；这个空间是lvds写，mcu读
|
#写入数据，lvds读；这个空间是lvds写，mcu读
|
||||||
return ''
|
return ''
|
||||||
if data_len > 2032:
|
if data_len > 2032:
|
||||||
return ''
|
return ''
|
||||||
|
|
||||||
if (data != None) and (len(data) != 0) and (len(data) < data_len):
|
if (data != None) and (len(data) != 0) and (len(data) < data_len):
|
||||||
return ''
|
return ''
|
||||||
|
|
||||||
if (data == None) or (len(data) == 0):
|
if (data == None) or (len(data) == 0):
|
||||||
data = list()
|
data = list()
|
||||||
for i in range(data_len):
|
for i in range(data_len):
|
||||||
data.append((i + dev) & 0xff)
|
data.append((i + dev) & 0xff)
|
||||||
|
|
||||||
code = '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h%02x;\n'''%(data_len & 0xff, )\
|
code = '''txBuf[`ARRAY_IDX_OFF + 0] = 8'h%02x;\n'''%(data_len & 0xff, )\
|
||||||
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h%02x;\n'''%(int(data_len/256) & 0xff,)\
|
+ '''txBuf[`ARRAY_IDX_OFF + 1] = 8'h%02x;\n'''%(int(data_len/256) & 0xff,)\
|
||||||
+ '''%s((16'h%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", smaddr[sm], dev)
|
+ '''%s((16'h%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", smaddr[sm], dev)
|
||||||
|
|
||||||
for i in range(data_len):
|
for i in range(data_len):
|
||||||
code = code + '''txBuf[`ARRAY_IDX_OFF + %d] = 8'h%02x;\n'''%(i, data[i])
|
code = code + '''txBuf[`ARRAY_IDX_OFF + %d] = 8'h%02x;\n'''%(i, data[i])
|
||||||
|
|
||||||
code = code + '''%s( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", 0x800 + sm * 2048, data_len, dev)
|
code = code + '''%s( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", 0x800 + sm * 2048, data_len, dev)
|
||||||
return code
|
return code
|
||||||
|
|
||||||
def genSlvSMReadData(dev, sm, data_len, wlog=True):
|
def genSlvSMReadData(dev, sm, data_len, wlog=True):
|
||||||
if not ((sm == 0) or (sm == 2) or (sm == 4) or (sm == 6)):
|
if not ((sm == 0) or (sm == 2) or (sm == 4) or (sm == 6)):
|
||||||
#写入数据，lvds读；这个空间是lvds写，mcu读
|
#写入数据，lvds读；这个空间是lvds写，mcu读
|
||||||
return ''
|
return ''
|
||||||
if data_len > 2032:
|
if data_len > 2032:
|
||||||
return ''
|
return ''
|
||||||
|
|
||||||
code = f'''$fdisplay(spidata_file, "--读取设备{dev} SM{sm} 中的数据，读取长度{data_len}B");\n'''
|
code = f'''$fdisplay(spidata_file, "--读取设备{dev} SM{sm} 中的数据，读取长度{data_len}B");\n'''
|
||||||
code = code + '''%s( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", 0x800 + sm * 2048, data_len, dev)
|
code = code + '''%s( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", 0x800 + sm * 2048, data_len, dev)
|
||||||
|
|
||||||
return code
|
return code
|
||||||
|
|
||||||
def setting_ebmmu_regs(regmap, index, vaddr, raddr, size, p, enable):
|
def setting_ebmmu_regs(regmap, index, vaddr, raddr, size, p, enable):
|
||||||
vaddr = int(vaddr)
|
vaddr = int(vaddr)
|
||||||
raddr = int(raddr)
|
raddr = int(raddr)
|
||||||
size = int(size)
|
size = int(size)
|
||||||
p = int(p)
|
p = int(p)
|
||||||
enable = int(enable)
|
enable = int(enable)
|
||||||
regmap[index * 0xa + 0] = (vaddr >> 0) & 0xff
|
regmap[index * 0xa + 0] = (vaddr >> 0) & 0xff
|
||||||
regmap[index * 0xa + 1] = (vaddr >> 8) & 0xff
|
regmap[index * 0xa + 1] = (vaddr >> 8) & 0xff
|
||||||
regmap[index * 0xa + 2] = (vaddr >> 16) & 0xff
|
regmap[index * 0xa + 2] = (vaddr >> 16) & 0xff
|
||||||
regmap[index * 0xa + 3] = (vaddr >> 24) & 0xff
|
regmap[index * 0xa + 3] = (vaddr >> 24) & 0xff
|
||||||
|
|
||||||
regmap[index * 0xa + 4] = (raddr >> 0) & 0xff
|
regmap[index * 0xa + 4] = (raddr >> 0) & 0xff
|
||||||
regmap[index * 0xa + 5] = (raddr >> 8) & 0xff
|
regmap[index * 0xa + 5] = (raddr >> 8) & 0xff
|
||||||
|
|
||||||
regmap[index * 0xa + 6] = (size >> 0) & 0xff
|
regmap[index * 0xa + 6] = (size >> 0) & 0xff
|
||||||
regmap[index * 0xa + 7] = (size >> 8) & 0xff
|
regmap[index * 0xa + 7] = (size >> 8) & 0xff
|
||||||
|
|
||||||
regmap[index * 0xa + 8] = p & 0x3
|
regmap[index * 0xa + 8] = p & 0x3
|
||||||
regmap[index * 0xa + 9] = enable & 0x1
|
regmap[index * 0xa + 9] = enable & 0x1
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
__run_list=list()
|
__run_list=list()
|
||||||
__pre_include_path='./generated/shin'
|
__pre_include_path='./generated/shin'
|
||||||
__pre_gen_log_path='./generated/log'
|
__pre_gen_log_path='./generated/log'
|
||||||
def add_tc_2_runlist(filename):
|
def add_tc_2_runlist(filename):
|
||||||
code_f = filename + '.vh'
|
code_f = filename + '.vh'
|
||||||
if code_f in __run_list:
|
if code_f in __run_list:
|
||||||
print("Error, Testcase duplicate name")
|
print("Error, Testcase duplicate name")
|
||||||
raise "DUPLICATE NAME"
|
raise "DUPLICATE NAME"
|
||||||
__run_list.append(code_f)
|
__run_list.append(code_f)
|
||||||
|
|
||||||
def gen_tc_runlist():
|
def gen_tc_runlist():
|
||||||
runlist_file = __pre_include_path + '/tc_runlist.vh'
|
runlist_file = __pre_include_path + '/tc_runlist.vh'
|
||||||
f = open(runlist_file, "wt+")
|
f = open(runlist_file, "wt+")
|
||||||
for tc in __run_list:
|
for tc in __run_list:
|
||||||
f.write(f'\t`include "{tc}"\n')
|
f.write(f'\t`include "{tc}"\n')
|
||||||
f.close()
|
f.close()
|
||||||
|
|
||||||
|
|
||||||
def genTcStartFrameCode(tcname, des, vardef="\n"):
|
def genTcStartFrameCode(tcname, des, vardef="\n"):
|
||||||
upper_name = tcname.upper()
|
upper_name = tcname.upper()
|
||||||
code_str = f'''\tbegin:{upper_name}_TESTCASE\n'''\
|
code_str = f'''\tbegin:{upper_name}_TESTCASE\n'''\
|
||||||
+vardef \
|
+vardef \
|
||||||
+f'''\t\t`BEGIN_TESTCASE("{__pre_gen_log_path}/{tcname}_result.log");\n'''\
|
+f'''\t\t`BEGIN_TESTCASE("{__pre_gen_log_path}/{tcname}_result.log");\n'''\
|
||||||
+'''\t\t_t_start = $realtime;\n'''\
|
+'''\t\t_t_start = $realtime;\n'''\
|
||||||
+f'''\t\t$fdisplay(spidata_file,"\\n\\n测试用例：{upper_name}");\n'''
|
+f'''\t\t$fdisplay(spidata_file,"\\n\\n测试用例：{upper_name}");\n'''
|
||||||
|
|
||||||
if len(des) > 0:
|
if len(des) > 0:
|
||||||
code_str = code_str + '''\t\t$fdisplay(spidata_file,"''' + '-' * 80 + '''");\n'''
|
code_str = code_str + '''\t\t$fdisplay(spidata_file,"''' + '-' * 80 + '''");\n'''
|
||||||
code_str = code_str + f'''\t\t$fdisplay(spidata_file,"{des}");\n'''
|
code_str = code_str + f'''\t\t$fdisplay(spidata_file,"{des}");\n'''
|
||||||
code_str = code_str + '''\t\t$fdisplay(spidata_file,"''' + '-' * 80 + '''");\n'''
|
code_str = code_str + '''\t\t$fdisplay(spidata_file,"''' + '-' * 80 + '''");\n'''
|
||||||
return code_str
|
return code_str
|
||||||
|
|
||||||
def genTcEndFrameCode(tcname):
|
def genTcEndFrameCode(tcname):
|
||||||
upper_name = tcname.upper()
|
upper_name = tcname.upper()
|
||||||
return f'''\t\t_t_end = $realtime;\n'''\
|
return f'''\t\t_t_end = $realtime;\n'''\
|
||||||
+'''\t\t$fdisplay(spidata_file, "该测试用例运行时间：%t\\n", _t_end - _t_start);\n'''\
|
+'''\t\t$fdisplay(spidata_file, "该测试用例运行时间：%t\\n", _t_end - _t_start);\n'''\
|
||||||
+f'''\t\t`END_TESTCASE("{__pre_gen_log_path}/{tcname}_result.log");\n'''\
|
+f'''\t\t`END_TESTCASE("{__pre_gen_log_path}/{tcname}_result.log");\n'''\
|
||||||
+'''\tend\n'''
|
+'''\tend\n'''
|
||||||
|
|
||||||
def genMessageCode(msg):
|
def genMessageCode(msg):
|
||||||
return f'''\t\t$fdisplay(spidata_file, "{msg}");\n'''
|
return f'''\t\t$fdisplay(spidata_file, "{msg}");\n'''
|
||||||
|
|||||||
@@ -1,2 +1,2 @@
|
|||||||
+incdir+./generated/shin
|
+incdir+./generated/shin
|
||||||
./shinTest/ShinTopSpiTb_clk.v
|
./shinTest/ShinTopSpiTb_clk.v
|
||||||
|
|||||||
@@ -1,2 +1,2 @@
|
|||||||
+incdir+./generated/shin
|
+incdir+./generated/shin
|
||||||
./shinTest/ShinTopSpiTb.v
|
./shinTest/ShinTopSpiTb.v
|
||||||
|
|||||||
@@ -1,10 +1,10 @@
|
|||||||
# testcase/__init__.py
|
# testcase/__init__.py
|
||||||
from .rwregs import *
|
from .rwregs import *
|
||||||
from .ebmmu import *
|
from .ebmmu import *
|
||||||
from .errorPkt import *
|
from .errorPkt import *
|
||||||
from .watchdog import *
|
from .watchdog import *
|
||||||
from .broadcast import *
|
from .broadcast import *
|
||||||
from .sync import *
|
from .sync import *
|
||||||
from .environment import *
|
from .environment import *
|
||||||
from .mac import *
|
from .mac import *
|
||||||
from .manydev import *
|
from .manydev import *
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,196 +1,196 @@
|
|||||||
from pyutils import *
|
from pyutils import *
|
||||||
|
|
||||||
|
|
||||||
def tc1():
|
def tc1():
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
|
|
||||||
gen_file_def = "broadcast_tc01"
|
gen_file_def = "broadcast_tc01"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "发送广播数据包，广播读取，广播读回的数据是四个从站对应寄存器位与的结果。"
|
tc_des = "发送广播数据包，广播读取，广播读回的数据是四个从站对应寄存器位与的结果。"
|
||||||
|
|
||||||
#-------------------------------------------------------------------------
|
#-------------------------------------------------------------------------
|
||||||
#>>>>>>广播读
|
#>>>>>>广播读
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
genPkt.addSubPkt(0x0, 0, 0xc0, 0xd, 4, b"\0"*4)
|
genPkt.addSubPkt(0x0, 0, 0xc0, 0xd, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x1, 0, 0xc0, 0x0, 4, b"\0"*4)
|
genPkt.addSubPkt(0x1, 0, 0xc0, 0x0, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x2, 0, 0xc0, 0x0, 4, b"\0"*4)
|
genPkt.addSubPkt(0x2, 0, 0xc0, 0x0, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x3, 0, 0xc0, 0x0, 4, b"\0"*4)
|
genPkt.addSubPkt(0x3, 0, 0xc0, 0x0, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x4, 0, 0xc0, 0x0, 4, b"\0"*4)
|
genPkt.addSubPkt(0x4, 0, 0xc0, 0x0, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
||||||
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
genPkt.addSubPkt(0x100, 0, 0xc0, 0xd, 4, b"\0"*4)
|
||||||
|
|
||||||
|
|
||||||
#gen_file_def = "bc_r_pkt"
|
#gen_file_def = "bc_r_pkt"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
def tc2():
|
def tc2():
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
gen_file_def = "broadcast_tc02"
|
gen_file_def = "broadcast_tc02"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "广播写入，写入SM0，32个字符长度的数据。"
|
tc_des = "广播写入，写入SM0，32个字符长度的数据。"
|
||||||
|
|
||||||
#-------------------------------------------------------------------------
|
#-------------------------------------------------------------------------
|
||||||
#>>>>>>广播写
|
#>>>>>>广播写
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
sm_size = 32
|
sm_size = 32
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
data = [0, ] * 2
|
data = [0, ] * 2
|
||||||
data[0] = sm_size & 0xff
|
data[0] = sm_size & 0xff
|
||||||
data[1] = (sm_size >> 8) & 0xff
|
data[1] = (sm_size >> 8) & 0xff
|
||||||
genPkt.addSubPkt(2000, 0, 0x0302, 0xe, 2, data)
|
genPkt.addSubPkt(2000, 0, 0x0302, 0xe, 2, data)
|
||||||
|
|
||||||
data = list(range(1, sm_size + 1))
|
data = list(range(1, sm_size + 1))
|
||||||
genPkt.addSubPkt(2000, 0, 0x0800, 0xe, sm_size, data)
|
genPkt.addSubPkt(2000, 0, 0x0800, 0xe, sm_size, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--读取SM的状态")
|
+genMessageCode("--读取SM的状态")
|
||||||
+genIFRwDataCode(1, 0x300, False, 0x4)
|
+genIFRwDataCode(1, 0x300, False, 0x4)
|
||||||
+genIFRwDataCode(2, 0x300, False, 0x4)
|
+genIFRwDataCode(2, 0x300, False, 0x4)
|
||||||
+genIFRwDataCode(3, 0x300, False, 0x4)
|
+genIFRwDataCode(3, 0x300, False, 0x4)
|
||||||
+genIFRwDataCode(4, 0x300, False, 0x4)
|
+genIFRwDataCode(4, 0x300, False, 0x4)
|
||||||
|
|
||||||
+genSlvSMReadData(1, 0, sm_size)
|
+genSlvSMReadData(1, 0, sm_size)
|
||||||
+genSlvSMReadData(2, 0, sm_size)
|
+genSlvSMReadData(2, 0, sm_size)
|
||||||
+genSlvSMReadData(3, 0, sm_size)
|
+genSlvSMReadData(3, 0, sm_size)
|
||||||
+genSlvSMReadData(4, 0, sm_size)
|
+genSlvSMReadData(4, 0, sm_size)
|
||||||
|
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|
||||||
def tc3():
|
def tc3():
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
|
|
||||||
gen_file_def = "broadcast_tc03"
|
gen_file_def = "broadcast_tc03"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "广播读写，读写0xc0开始的链路寄存器组。所有从站设备采用位与策略往报文中输入。"
|
tc_des = "广播读写，读写0xc0开始的链路寄存器组。所有从站设备采用位与策略往报文中输入。"
|
||||||
|
|
||||||
#-------------------------------------------------------------------------
|
#-------------------------------------------------------------------------
|
||||||
#>>>>>>广播读写
|
#>>>>>>广播读写
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
data = bytearray(b"\0"*100)
|
data = bytearray(b"\0"*100)
|
||||||
genPkt.addSubPkt(1024, 0, 0x00c0, 0xf, 4, data)
|
genPkt.addSubPkt(1024, 0, 0x00c0, 0xf, 4, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
+genMessageCode("--读取中断")
|
+genMessageCode("--读取中断")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,475 +1,475 @@
|
|||||||
from pyutils import *
|
from pyutils import *
|
||||||
|
|
||||||
|
|
||||||
global_dev_num = 4
|
global_dev_num = 4
|
||||||
global_setting_dev_clk = dict()
|
global_setting_dev_clk = dict()
|
||||||
global_using_8b10b = False
|
global_using_8b10b = False
|
||||||
global_spi_type = 0
|
global_spi_type = 0
|
||||||
global_cdr_type = 0
|
global_cdr_type = 0
|
||||||
|
|
||||||
def bringup():
|
def bringup():
|
||||||
gen_file_def = "sys_bringup"
|
gen_file_def = "sys_bringup"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "系统环境建立，包括：1.配置主从栈的角色；2.网络建立，嗅探、设置顺序地址、嗅探；3.配置中断。\\n" \
|
tc_des = "系统环境建立，包括：1.配置主从栈的角色；2.网络建立，嗅探、设置顺序地址、嗅探；3.配置中断。\\n" \
|
||||||
+ "\\n注意：网络建立第一次嗅探包发送主要是为了建立拓扑，每个从站都知道了自己的邻居状况；发送顺序地址，\\n"\
|
+ "\\n注意：网络建立第一次嗅探包发送主要是为了建立拓扑，每个从站都知道了自己的邻居状况；发送顺序地址，\\n"\
|
||||||
+ "则是让每个从站拥有合适的地址。第二次发送嗅探包非必要，主要是用于更新从站的邻居信息。"
|
+ "则是让每个从站拥有合适的地址。第二次发送嗅探包非必要，主要是用于更新从站的邻居信息。"
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+genMessageCode("--设置合适的工作模式：底层编码4b5b or 8b10b/设置CDR/SPI接口")
|
+genMessageCode("--设置合适的工作模式：底层编码4b5b or 8b10b/设置CDR/SPI接口")
|
||||||
+using_proper_workmode(0)
|
+using_proper_workmode(0)
|
||||||
+using_proper_workmode(1)
|
+using_proper_workmode(1)
|
||||||
+using_proper_workmode(2)
|
+using_proper_workmode(2)
|
||||||
+using_proper_workmode(3)
|
+using_proper_workmode(3)
|
||||||
+using_proper_workmode(4)
|
+using_proper_workmode(4)
|
||||||
|
|
||||||
+genMessageCode("--读取中断状态")
|
+genMessageCode("--读取中断状态")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
main_dev = [0x01, ]
|
main_dev = [0x01, ]
|
||||||
slave_dev =[0x02, ]
|
slave_dev =[0x02, ]
|
||||||
genPkt.addAfterExc(genMessageCode("--设置主站，协议栈工作在主站模式")
|
genPkt.addAfterExc(genMessageCode("--设置主站，协议栈工作在主站模式")
|
||||||
+genIFRwDataCode(0, 0x0, True, 1, main_dev)
|
+genIFRwDataCode(0, 0x0, True, 1, main_dev)
|
||||||
+"#5000\n"
|
+"#5000\n"
|
||||||
+genMessageCode("--设置从站，协议栈工作在从站模式")
|
+genMessageCode("--设置从站，协议栈工作在从站模式")
|
||||||
+genIFRwDataCode(1, 0x0, True, 1, slave_dev)
|
+genIFRwDataCode(1, 0x0, True, 1, slave_dev)
|
||||||
+genIFRwDataCode(2, 0x0, True, 1, slave_dev)
|
+genIFRwDataCode(2, 0x0, True, 1, slave_dev)
|
||||||
+genIFRwDataCode(3, 0x0, True, 1, slave_dev)
|
+genIFRwDataCode(3, 0x0, True, 1, slave_dev)
|
||||||
+genIFRwDataCode(4, 0x0, True, 1, slave_dev)
|
+genIFRwDataCode(4, 0x0, True, 1, slave_dev)
|
||||||
+genMessageCode("--读取寄存器，检查相关的配置")
|
+genMessageCode("--读取寄存器，检查相关的配置")
|
||||||
+genIFRwDataCode(0, 0x0, False, 1)
|
+genIFRwDataCode(0, 0x0, False, 1)
|
||||||
+genIFRwDataCode(1, 0x0, False, 1)
|
+genIFRwDataCode(1, 0x0, False, 1)
|
||||||
+genIFRwDataCode(2, 0x0, False, 1)
|
+genIFRwDataCode(2, 0x0, False, 1)
|
||||||
+genIFRwDataCode(3, 0x0, False, 1)
|
+genIFRwDataCode(3, 0x0, False, 1)
|
||||||
+genIFRwDataCode(4, 0x0, False, 1)
|
+genIFRwDataCode(4, 0x0, False, 1)
|
||||||
|
|
||||||
+genMessageCode("--使能中断")
|
+genMessageCode("--使能中断")
|
||||||
+genIFRwDataCode(0, 0x70, True, 4, [0x03, 0x00, 0x00, 0xf0])
|
+genIFRwDataCode(0, 0x70, True, 4, [0x03, 0x00, 0x00, 0xf0])
|
||||||
+genIFRwDataCode(1, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
+genIFRwDataCode(1, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
||||||
+genIFRwDataCode(2, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
+genIFRwDataCode(2, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
||||||
+genIFRwDataCode(3, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
+genIFRwDataCode(3, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
||||||
+genIFRwDataCode(4, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
+genIFRwDataCode(4, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0])
|
||||||
|
|
||||||
+genMessageCode("--设置中断为脉冲模式")
|
+genMessageCode("--设置中断为脉冲模式")
|
||||||
+genIFRwDataCode(0, 0x7c, True, 2, [0x10, 0x80])
|
+genIFRwDataCode(0, 0x7c, True, 2, [0x10, 0x80])
|
||||||
+genIFRwDataCode(1, 0x7c, True, 2, [0x10, 0x80])
|
+genIFRwDataCode(1, 0x7c, True, 2, [0x10, 0x80])
|
||||||
+genIFRwDataCode(2, 0x7c, True, 2, [0x10, 0x80])
|
+genIFRwDataCode(2, 0x7c, True, 2, [0x10, 0x80])
|
||||||
+genIFRwDataCode(3, 0x7c, True, 2, [0x10, 0x80])
|
+genIFRwDataCode(3, 0x7c, True, 2, [0x10, 0x80])
|
||||||
+genIFRwDataCode(4, 0x7c, True, 2, [0x10, 0x80])
|
+genIFRwDataCode(4, 0x7c, True, 2, [0x10, 0x80])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(1)
|
genPkt.setPktType(1)
|
||||||
gen_file_def_ap = gen_file_def+"_step01"
|
gen_file_def_ap = gen_file_def+"_step01"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第一次嗅探"))
|
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第一次嗅探"))
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genMessageCode("--嗅探后检查链路状态寄存器")
|
+genMessageCode("--嗅探后检查链路状态寄存器")
|
||||||
+genIFRwDataCode(1, 0xc0, False, 4)
|
+genIFRwDataCode(1, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(2, 0xc0, False, 4)
|
+genIFRwDataCode(2, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(3, 0xc0, False, 4)
|
+genIFRwDataCode(3, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(4, 0xc0, False, 4)
|
+genIFRwDataCode(4, 0xc0, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除主中断")
|
+genMessageCode("--清除主中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
gen_file_def_ap = gen_file_def + "_step02"
|
gen_file_def_ap = gen_file_def + "_step02"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
data = [0x3f, 0xff]
|
data = [0x3f, 0xff]
|
||||||
genPkt.addSubPkt(0x0, 0, 0x0, 0xb, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x0, 0xb, 2, data)
|
||||||
|
|
||||||
genPkt.addAfterExc(genMessageCode("--设置顺序地址")
|
genPkt.addAfterExc(genMessageCode("--设置顺序地址")
|
||||||
+genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
+genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
#+genTcEndFrameCode(gen_file_def)
|
#+genTcEndFrameCode(gen_file_def)
|
||||||
+genIFRwDataCode(1, 0xc0, False, 4)
|
+genIFRwDataCode(1, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(2, 0xc0, False, 4)
|
+genIFRwDataCode(2, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(3, 0xc0, False, 4)
|
+genIFRwDataCode(3, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(4, 0xc0, False, 4)
|
+genIFRwDataCode(4, 0xc0, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除主中断")
|
+genMessageCode("--清除主中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(1)
|
genPkt.setPktType(1)
|
||||||
gen_file_def_ap = gen_file_def+"_step03"
|
gen_file_def_ap = gen_file_def+"_step03"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第二次嗅探"))
|
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第二次嗅探"))
|
||||||
|
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
+genMessageCode("--嗅探后检查链路状态寄存器")
|
+genMessageCode("--嗅探后检查链路状态寄存器")
|
||||||
+genIFRwDataCode(1, 0xc0, False, 4)
|
+genIFRwDataCode(1, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(2, 0xc0, False, 4)
|
+genIFRwDataCode(2, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(3, 0xc0, False, 4)
|
+genIFRwDataCode(3, 0xc0, False, 4)
|
||||||
+genIFRwDataCode(4, 0xc0, False, 4)
|
+genIFRwDataCode(4, 0xc0, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
+genMessageCode("--读取中断状态")
|
+genMessageCode("--读取中断状态")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
+genMessageCode("--读取中断状态")
|
+genMessageCode("--读取中断状态")
|
||||||
+genIFRwDataCode(0, 0x74, False, 4)
|
+genIFRwDataCode(0, 0x74, False, 4)
|
||||||
+genIFRwDataCode(1, 0x74, False, 4)
|
+genIFRwDataCode(1, 0x74, False, 4)
|
||||||
+genIFRwDataCode(2, 0x74, False, 4)
|
+genIFRwDataCode(2, 0x74, False, 4)
|
||||||
+genIFRwDataCode(3, 0x74, False, 4)
|
+genIFRwDataCode(3, 0x74, False, 4)
|
||||||
+genIFRwDataCode(4, 0x74, False, 4)
|
+genIFRwDataCode(4, 0x74, False, 4)
|
||||||
|
|
||||||
+genMessageCode("--读取看门狗")
|
+genMessageCode("--读取看门狗")
|
||||||
+genIFRwDataCode(0, 0x400, False, 8)
|
+genIFRwDataCode(0, 0x400, False, 8)
|
||||||
+genIFRwDataCode(1, 0x400, False, 8)
|
+genIFRwDataCode(1, 0x400, False, 8)
|
||||||
+genIFRwDataCode(2, 0x400, False, 8)
|
+genIFRwDataCode(2, 0x400, False, 8)
|
||||||
+genIFRwDataCode(3, 0x400, False, 8)
|
+genIFRwDataCode(3, 0x400, False, 8)
|
||||||
+genIFRwDataCode(4, 0x400, False, 8)
|
+genIFRwDataCode(4, 0x400, False, 8)
|
||||||
|
|
||||||
#+genIFRwDataCode(1, 0x0044, True, 4, [0x12, 0x34, 0x56, 0x78])
|
#+genIFRwDataCode(1, 0x0044, True, 4, [0x12, 0x34, 0x56, 0x78])
|
||||||
#+genIFRwDataCode(1, 0x0044, False, 4)
|
#+genIFRwDataCode(1, 0x0044, False, 4)
|
||||||
|
|
||||||
+genTcEndFrameCode(gen_file_def)
|
+genTcEndFrameCode(gen_file_def)
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
|
|
||||||
add_tc_2_runlist(gen_file_def)
|
add_tc_2_runlist(gen_file_def)
|
||||||
|
|
||||||
def __GenDevice(id, TerminateNode = False):
|
def __GenDevice(id, TerminateNode = False):
|
||||||
global global_setting_dev_clk
|
global global_setting_dev_clk
|
||||||
dout_code = "dDat_w[%d]"%(id + 1, )
|
dout_code = "dDat_w[%d]"%(id + 1, )
|
||||||
din_code = "uDat_w[%d]"%(id + 1, )
|
din_code = "uDat_w[%d]"%(id + 1, )
|
||||||
if TerminateNode:
|
if TerminateNode:
|
||||||
dout_code = ""
|
dout_code = ""
|
||||||
din_code = "1'b0"
|
din_code = "1'b0"
|
||||||
|
|
||||||
clk = "multiCLK[0]"
|
clk = "multiCLK[0]"
|
||||||
multiclk = "multiCLK"
|
multiclk = "multiCLK"
|
||||||
try:
|
try:
|
||||||
v = global_setting_dev_clk[id + 1]
|
v = global_setting_dev_clk[id + 1]
|
||||||
clk = "multiCLK%d[0]"%(id + 1, )
|
clk = "multiCLK%d[0]"%(id + 1, )
|
||||||
multiclk = "multiCLK%d"%(id + 1, )
|
multiclk = "multiCLK%d"%(id + 1, )
|
||||||
except:
|
except:
|
||||||
pass
|
pass
|
||||||
|
|
||||||
|
|
||||||
code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, )
|
code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, )
|
||||||
+"\t.clock(%s),\n"%(clk, )
|
+"\t.clock(%s),\n"%(clk, )
|
||||||
+"\t.reset(reset | isSoftReset_reg[%d]),\n\n"%(id + 1,)
|
+"\t.reset(reset | isSoftReset_reg[%d]),\n\n"%(id + 1,)
|
||||||
|
|
||||||
+"\t.io_multiCLK_0(%s[0]),\n"%(multiclk, )
|
+"\t.io_multiCLK_0(%s[0]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_1(%s[1]),\n"%(multiclk, )
|
+"\t.io_multiCLK_1(%s[1]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_2(%s[2]),\n"%(multiclk, )
|
+"\t.io_multiCLK_2(%s[2]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_3(%s[3]),\n"%(multiclk, )
|
+"\t.io_multiCLK_3(%s[3]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_4(%s[4]),\n"%(multiclk, )
|
+"\t.io_multiCLK_4(%s[4]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_5(%s[5]),\n"%(multiclk, )
|
+"\t.io_multiCLK_5(%s[5]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_6(%s[6]),\n"%(multiclk, )
|
+"\t.io_multiCLK_6(%s[6]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_7(%s[7]),\n"%(multiclk, )
|
+"\t.io_multiCLK_7(%s[7]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_8(%s[8]),\n"%(multiclk, )
|
+"\t.io_multiCLK_8(%s[8]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_9(%s[9]),\n"%(multiclk, )
|
+"\t.io_multiCLK_9(%s[9]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_10(%s[10]),\n"%(multiclk, )
|
+"\t.io_multiCLK_10(%s[10]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_11(%s[11]),\n"%(multiclk, )
|
+"\t.io_multiCLK_11(%s[11]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_12(%s[12]),\n"%(multiclk, )
|
+"\t.io_multiCLK_12(%s[12]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_13(%s[13]),\n"%(multiclk, )
|
+"\t.io_multiCLK_13(%s[13]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_14(%s[14]),\n"%(multiclk, )
|
+"\t.io_multiCLK_14(%s[14]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLK_15(%s[15]),\n\n"%(multiclk, )
|
+"\t.io_multiCLK_15(%s[15]),\n\n"%(multiclk, )
|
||||||
|
|
||||||
+"\t.io_multiCLKDiv4_0(%s[0]),\n"%(multiclk, )
|
+"\t.io_multiCLKDiv4_0(%s[0]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLKDiv4_1(%s[4]),\n"%(multiclk, )
|
+"\t.io_multiCLKDiv4_1(%s[4]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLKDiv4_2(%s[8]),\n"%(multiclk, )
|
+"\t.io_multiCLKDiv4_2(%s[8]),\n"%(multiclk, )
|
||||||
+"\t.io_multiCLKDiv4_3(%s[12]),\n\n"%(multiclk, )
|
+"\t.io_multiCLKDiv4_3(%s[12]),\n\n"%(multiclk, )
|
||||||
|
|
||||||
+"\t.io_dDatIn(dDat_w[%d]),\n"%(id, )
|
+"\t.io_dDatIn(dDat_w[%d]),\n"%(id, )
|
||||||
+"\t.io_dDatOut(%s),\n"%(dout_code, )
|
+"\t.io_dDatOut(%s),\n"%(dout_code, )
|
||||||
+"\t.io_uDatIn(%s),\n"%(din_code, )
|
+"\t.io_uDatIn(%s),\n"%(din_code, )
|
||||||
+"\t.io_uDatOut(uDat_w[%d]),\n\n"%(id, )
|
+"\t.io_uDatOut(uDat_w[%d]),\n\n"%(id, )
|
||||||
|
|
||||||
+"\t.io_iqspi_sck(qspi_sck),\n"
|
+"\t.io_iqspi_sck(qspi_sck),\n"
|
||||||
+"\t.io_iqspi_mosi(qspi_mosi),\n"
|
+"\t.io_iqspi_mosi(qspi_mosi),\n"
|
||||||
+"\t.io_iqspi_miso(`IQSPI_MISO(%d)),\n"%(id + 1, )
|
+"\t.io_iqspi_miso(`IQSPI_MISO(%d)),\n"%(id + 1, )
|
||||||
+"\t.io_iqspi_isDirIn(),\n"
|
+"\t.io_iqspi_isDirIn(),\n"
|
||||||
+"\t.io_iqspi_csn(`IQSPI_CSN(%d)),\n\n"%(id + 1, )
|
+"\t.io_iqspi_csn(`IQSPI_CSN(%d)),\n\n"%(id + 1, )
|
||||||
|
|
||||||
+"\t.io_ospi_sck (spi_sck),\n"
|
+"\t.io_ospi_sck (spi_sck),\n"
|
||||||
+"\t.io_ospi_mosi(spi_mosi),\n"
|
+"\t.io_ospi_mosi(spi_mosi),\n"
|
||||||
+"\t.io_ospi_miso(spi_miso[%d]),\n"%(id + 1, )
|
+"\t.io_ospi_miso(spi_miso[%d]),\n"%(id + 1, )
|
||||||
+"\t.io_ospi_csn (`ESPI_CSN(%d)),\n\n"%(id + 1, )
|
+"\t.io_ospi_csn (`ESPI_CSN(%d)),\n\n"%(id + 1, )
|
||||||
|
|
||||||
+"\t.io_oqspi_sck(qspi_sck),\n"
|
+"\t.io_oqspi_sck(qspi_sck),\n"
|
||||||
+"\t.io_oqspi_mosi(qspi_mosi),\n"
|
+"\t.io_oqspi_mosi(qspi_mosi),\n"
|
||||||
+"\t.io_oqspi_miso(`EQSPI_MISO(%d)),\n"%(id + 1, )
|
+"\t.io_oqspi_miso(`EQSPI_MISO(%d)),\n"%(id + 1, )
|
||||||
+"\t.io_oqspi_isDirIn(),\n"
|
+"\t.io_oqspi_isDirIn(),\n"
|
||||||
+"\t.io_oqspi_csn(`EQSPI_CSN(%d)),\n\n"%(id + 1, )
|
+"\t.io_oqspi_csn(`EQSPI_CSN(%d)),\n\n"%(id + 1, )
|
||||||
|
|
||||||
+"\t.io_aqspi_sck(qspi_sck),\n"
|
+"\t.io_aqspi_sck(qspi_sck),\n"
|
||||||
+"\t.io_aqspi_mosi(qspi_mosi),\n"
|
+"\t.io_aqspi_mosi(qspi_mosi),\n"
|
||||||
+"\t.io_aqspi_miso(`AQSPI_MISO(%d)),\n"%(id + 1, )
|
+"\t.io_aqspi_miso(`AQSPI_MISO(%d)),\n"%(id + 1, )
|
||||||
+"\t.io_aqspi_isDirIn(),\n"
|
+"\t.io_aqspi_isDirIn(),\n"
|
||||||
+"\t.io_aqspi_csn(`AQSPI_CSN(%d)),\n"%(id + 1, )
|
+"\t.io_aqspi_csn(`AQSPI_CSN(%d)),\n"%(id + 1, )
|
||||||
|
|
||||||
+"\t.io_isSoftReset(isSoftReset[%d]),\n"%(id + 1, )
|
+"\t.io_isSoftReset(isSoftReset[%d]),\n"%(id + 1, )
|
||||||
+"\t.io_interrupt(io_int_sig[%d]),\n"%(id + 1, )
|
+"\t.io_interrupt(io_int_sig[%d]),\n"%(id + 1, )
|
||||||
+"\t.io_latchPin_0(latch0),\n"
|
+"\t.io_latchPin_0(latch0),\n"
|
||||||
+"\t.io_latchPin_1(latch1),\n"
|
+"\t.io_latchPin_1(latch1),\n"
|
||||||
+"\t.io_hwSerial(`HW_SERIAL),\n"
|
+"\t.io_hwSerial(`HW_SERIAL),\n"
|
||||||
+"\t.io_uniCode(64'h0)\n"
|
+"\t.io_uniCode(64'h0)\n"
|
||||||
+"\t);\n\n\n"
|
+"\t);\n\n\n"
|
||||||
)
|
)
|
||||||
return code_device
|
return code_device
|
||||||
|
|
||||||
def __gen_slv_dev_predef(num):
|
def __gen_slv_dev_predef(num):
|
||||||
|
|
||||||
global global_setting_dev_clk
|
global global_setting_dev_clk
|
||||||
global global_spi_type
|
global global_spi_type
|
||||||
|
|
||||||
code_for_clk = ""
|
code_for_clk = ""
|
||||||
for k in global_setting_dev_clk:
|
for k in global_setting_dev_clk:
|
||||||
code_for_clk = code_for_clk + "reg [15:0] multiCLK%d;\n"%(k, )
|
code_for_clk = code_for_clk + "reg [15:0] multiCLK%d;\n"%(k, )
|
||||||
|
|
||||||
spi_type_str = "USING_IQSPI"
|
spi_type_str = "USING_IQSPI"
|
||||||
if global_spi_type == 1:
|
if global_spi_type == 1:
|
||||||
spi_type_str = "USING_OSPI"
|
spi_type_str = "USING_OSPI"
|
||||||
elif global_spi_type == 2:
|
elif global_spi_type == 2:
|
||||||
spi_type_str = "USING_OQSPI"
|
spi_type_str = "USING_OQSPI"
|
||||||
elif global_spi_type == 3:
|
elif global_spi_type == 3:
|
||||||
spi_type_str = "USING_AQSPI"
|
spi_type_str = "USING_AQSPI"
|
||||||
else:
|
else:
|
||||||
spi_type_str = "USING_IQSPI"
|
spi_type_str = "USING_IQSPI"
|
||||||
|
|
||||||
code_predef =("`define %s \n"%(spi_type_str, )
|
code_predef =("`define %s \n"%(spi_type_str, )
|
||||||
+"`define DEV_NUM %d //slave num\n"%(num, )
|
+"`define DEV_NUM %d //slave num\n"%(num, )
|
||||||
+"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n"
|
+"`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master\n"
|
||||||
+"`define SPI_CSN_NUM (`ALL_DEV_NUM * 4)\n\n"
|
+"`define SPI_CSN_NUM (`ALL_DEV_NUM * 4)\n\n"
|
||||||
|
|
||||||
+"`define HW_SERIAL 48'h31303050584c //(48'h4c5850303031)\n\n"
|
+"`define HW_SERIAL 48'h31303050584c //(48'h4c5850303031)\n\n"
|
||||||
|
|
||||||
+"`define IQSPI_PINS(N) (N*4+3):(N*4)\n"
|
+"`define IQSPI_PINS(N) (N*4+3):(N*4)\n"
|
||||||
+"`define EQSPI_PINS(N) ((N + `ALL_DEV_NUM)*4+3):((N + `ALL_DEV_NUM)*4)\n"
|
+"`define EQSPI_PINS(N) ((N + `ALL_DEV_NUM)*4+3):((N + `ALL_DEV_NUM)*4)\n"
|
||||||
+"`define AQSPI_PINS(N) ((N + `ALL_DEV_NUM * 2)*4+3):((N + `ALL_DEV_NUM * 2)*4)\n\n"
|
+"`define AQSPI_PINS(N) ((N + `ALL_DEV_NUM * 2)*4+3):((N + `ALL_DEV_NUM * 2)*4)\n\n"
|
||||||
|
|
||||||
+"`define IQSPI_MISO(N) qspi_miso[`IQSPI_PINS(N)]\n"
|
+"`define IQSPI_MISO(N) qspi_miso[`IQSPI_PINS(N)]\n"
|
||||||
+"`define EQSPI_MISO(N) qspi_miso[`EQSPI_PINS(N)]\n"
|
+"`define EQSPI_MISO(N) qspi_miso[`EQSPI_PINS(N)]\n"
|
||||||
+"`define AQSPI_MISO(N) qspi_miso[`AQSPI_PINS(N)]\n\n"
|
+"`define AQSPI_MISO(N) qspi_miso[`AQSPI_PINS(N)]\n\n"
|
||||||
|
|
||||||
+"`define IQSPI_CSN_NUM(id) (id)\n"
|
+"`define IQSPI_CSN_NUM(id) (id)\n"
|
||||||
+"`define ESPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM))\n"
|
+"`define ESPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM))\n"
|
||||||
+"`define EQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*2)\n"
|
+"`define EQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*2)\n"
|
||||||
+"`define AQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*3)\n\n"
|
+"`define AQSPI_CSN_NUM(id) ((id)+(`ALL_DEV_NUM)*3)\n\n"
|
||||||
|
|
||||||
+"`define IQSPI_CSN(id) spi_csn[`IQSPI_CSN_NUM(id)]\n"
|
+"`define IQSPI_CSN(id) spi_csn[`IQSPI_CSN_NUM(id)]\n"
|
||||||
+"`define ESPI_CSN(id) spi_csn[`ESPI_CSN_NUM(id)]\n"
|
+"`define ESPI_CSN(id) spi_csn[`ESPI_CSN_NUM(id)]\n"
|
||||||
+"`define EQSPI_CSN(id) spi_csn[`EQSPI_CSN_NUM(id)]\n"
|
+"`define EQSPI_CSN(id) spi_csn[`EQSPI_CSN_NUM(id)]\n"
|
||||||
+"`define AQSPI_CSN(id) spi_csn[`AQSPI_CSN_NUM(id)]\n\n"
|
+"`define AQSPI_CSN(id) spi_csn[`AQSPI_CSN_NUM(id)]\n\n"
|
||||||
)
|
)
|
||||||
|
|
||||||
code_qspi_mux_init = "`define QSPI_MUX_MISO_INIT \\\n"
|
code_qspi_mux_init = "`define QSPI_MUX_MISO_INIT \\\n"
|
||||||
code_qspi_mux_init_item = ""
|
code_qspi_mux_init_item = ""
|
||||||
for i in range(num):
|
for i in range(num):
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`IQSPI_MISO(%d) & ~{4{`IQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`IQSPI_MISO(%d) & ~{4{`IQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`IQSPI_MISO(%d) & ~{4{`IQSPI_CSN(%d)}}) |\\\n"%(num, num)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`IQSPI_MISO(%d) & ~{4{`IQSPI_CSN(%d)}}) |\\\n"%(num, num)
|
||||||
|
|
||||||
for i in range(num):
|
for i in range(num):
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`EQSPI_MISO(%d) & ~{4{`EQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`EQSPI_MISO(%d) & ~{4{`EQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`EQSPI_MISO(%d) & ~{4{`EQSPI_CSN(%d)}}) |\\\n"%(num, num)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`EQSPI_MISO(%d) & ~{4{`EQSPI_CSN(%d)}}) |\\\n"%(num, num)
|
||||||
|
|
||||||
for i in range(num):
|
for i in range(num):
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}}) |\\\n"%(i, i)
|
||||||
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}})\n\n"%(num, num)
|
code_qspi_mux_init_item = code_qspi_mux_init_item + "\t\t(`AQSPI_MISO(%d) & ~{4{`AQSPI_CSN(%d)}})\n\n"%(num, num)
|
||||||
|
|
||||||
code_qspi_mux_init = code_qspi_mux_init + code_qspi_mux_init_item
|
code_qspi_mux_init = code_qspi_mux_init + code_qspi_mux_init_item
|
||||||
|
|
||||||
|
|
||||||
code_spi_mux_init = "`define SPI_MUX_MISO_INIT \\\n"
|
code_spi_mux_init = "`define SPI_MUX_MISO_INIT \\\n"
|
||||||
code_spi_mux_init_item = ""
|
code_spi_mux_init_item = ""
|
||||||
for i in range(num):
|
for i in range(num):
|
||||||
code_spi_mux_init_item = code_spi_mux_init_item + "\t\t( spi_miso[%d] & ~`ESPI_CSN(%d)) |\\\n"%(i, i)
|
code_spi_mux_init_item = code_spi_mux_init_item + "\t\t( spi_miso[%d] & ~`ESPI_CSN(%d)) |\\\n"%(i, i)
|
||||||
code_spi_mux_init_item = code_spi_mux_init_item + "\t\t( spi_miso[%d] & ~`ESPI_CSN(%d))\n\n"%(num, num)
|
code_spi_mux_init_item = code_spi_mux_init_item + "\t\t( spi_miso[%d] & ~`ESPI_CSN(%d))\n\n"%(num, num)
|
||||||
code_spi_mux_init = code_spi_mux_init + code_spi_mux_init_item
|
code_spi_mux_init = code_spi_mux_init + code_spi_mux_init_item
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
gen_file_def = "dev_predef"
|
gen_file_def = "dev_predef"
|
||||||
|
|
||||||
code = code_for_clk + code_predef + code_qspi_mux_init + code_spi_mux_init
|
code = code_for_clk + code_predef + code_qspi_mux_init + code_spi_mux_init
|
||||||
|
|
||||||
genPkt.addAfterExc(code)
|
genPkt.addAfterExc(code)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
|
|
||||||
def get_slv_dev_num():
|
def get_slv_dev_num():
|
||||||
global global_dev_num
|
global global_dev_num
|
||||||
|
|
||||||
return global_dev_num
|
return global_dev_num
|
||||||
|
|
||||||
def gen_slv_dev_num(num):
|
def gen_slv_dev_num(num):
|
||||||
global global_dev_num
|
global global_dev_num
|
||||||
|
|
||||||
global_dev_num = num
|
global_dev_num = num
|
||||||
|
|
||||||
__gen_slv_dev_predef(num)
|
__gen_slv_dev_predef(num)
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
gen_file_def = "slave_dev_def"
|
gen_file_def = "slave_dev_def"
|
||||||
|
|
||||||
code = ""
|
code = ""
|
||||||
for id in range(num - 1):
|
for id in range(num - 1):
|
||||||
code = code + __GenDevice(id)
|
code = code + __GenDevice(id)
|
||||||
|
|
||||||
code = code + __GenDevice(num - 1, True)
|
code = code + __GenDevice(num - 1, True)
|
||||||
|
|
||||||
genPkt.addAfterExc(code)
|
genPkt.addAfterExc(code)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
|
|
||||||
def gen_slv_dev_for_clk(num):
|
def gen_slv_dev_for_clk(num):
|
||||||
__gen_slv_dev_predef(num)
|
__gen_slv_dev_predef(num)
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
gen_file_def = "slave_dev_def"
|
gen_file_def = "slave_dev_def"
|
||||||
|
|
||||||
code = ""
|
code = ""
|
||||||
for id in range(num - 1):
|
for id in range(num - 1):
|
||||||
code = code + __GenDevice(id)
|
code = code + __GenDevice(id)
|
||||||
|
|
||||||
code = code + __GenDevice(num - 1, True)
|
code = code + __GenDevice(num - 1, True)
|
||||||
|
|
||||||
genPkt.addAfterExc(code)
|
genPkt.addAfterExc(code)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
|
|
||||||
def set_dev_clk(cfg):
|
def set_dev_clk(cfg):
|
||||||
global global_setting_dev_clk
|
global global_setting_dev_clk
|
||||||
global_setting_dev_clk = cfg
|
global_setting_dev_clk = cfg
|
||||||
|
|
||||||
code_for_clk = ""
|
code_for_clk = ""
|
||||||
for k in global_setting_dev_clk:
|
for k in global_setting_dev_clk:
|
||||||
v = global_setting_dev_clk[k]
|
v = global_setting_dev_clk[k]
|
||||||
ph = int(8 * 1000000 * (int(abs(v[0]))%360) / 360.0)
|
ph = int(8 * 1000000 * (int(abs(v[0]))%360) / 360.0)
|
||||||
period = int(1000000 + v[1])
|
period = int(1000000 + v[1])
|
||||||
code_for_clk = code_for_clk + __gen_slv_clk(k, ph, period)
|
code_for_clk = code_for_clk + __gen_slv_clk(k, ph, period)
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
gen_file_def = "slave_dev_clk"
|
gen_file_def = "slave_dev_clk"
|
||||||
genPkt.addAfterExc(code_for_clk)
|
genPkt.addAfterExc(code_for_clk)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
def __gen_slv_clk(clk, ph, period):
|
def __gen_slv_clk(clk, ph, period):
|
||||||
slv_code =(
|
slv_code =(
|
||||||
""
|
""
|
||||||
#"\tinitial begin\n"
|
#"\tinitial begin\n"
|
||||||
#+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk)
|
#+"\t\tforever begin #%d clock%d <= ~clock%d; end\n"%(period * 8, clk, clk)
|
||||||
#+"\tend\n\n"
|
#+"\tend\n\n"
|
||||||
|
|
||||||
+"\tgenerate\n"
|
+"\tgenerate\n"
|
||||||
+"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n"
|
+"\tfor( genvar i = 0; i < 16; i = i + 1 ) begin\n"
|
||||||
+"\t\tinitial begin\n"
|
+"\t\tinitial begin\n"
|
||||||
+ "\t\t\t//相位信息\n"
|
+ "\t\t\t//相位信息\n"
|
||||||
+ "\t\t\t#%d\n"%(ph)
|
+ "\t\t\t#%d\n"%(ph)
|
||||||
+ "\t\t\tmultiCLK%d[i] = 0;\n"%(clk, )
|
+ "\t\t\tmultiCLK%d[i] = 0;\n"%(clk, )
|
||||||
+ "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n"
|
+ "\t\t\tfor( integer j = 0; j < i; j = j + 1 ) begin\n"
|
||||||
+ "\t\t\t\t#%d\n"%(period, )
|
+ "\t\t\t\t#%d\n"%(period, )
|
||||||
+ "\t\t\t\t;\n"
|
+ "\t\t\t\t;\n"
|
||||||
+ "\t\t\tend\n"
|
+ "\t\t\tend\n"
|
||||||
+ "\t\t\tforever begin #%d multiCLK%d[i] <= ~multiCLK%d[i]; end\n"%(period * 8, clk, clk)
|
+ "\t\t\tforever begin #%d multiCLK%d[i] <= ~multiCLK%d[i]; end\n"%(period * 8, clk, clk)
|
||||||
+"\t\tend\n"
|
+"\t\tend\n"
|
||||||
+"\tend\n"
|
+"\tend\n"
|
||||||
+"\tendgenerate\n")
|
+"\tendgenerate\n")
|
||||||
|
|
||||||
return slv_code
|
return slv_code
|
||||||
|
|
||||||
def teardown():
|
def teardown():
|
||||||
#add_tc_2_runlist("")
|
#add_tc_2_runlist("")
|
||||||
pass
|
pass
|
||||||
|
|
||||||
def set_spi_interface(spi_type):
|
def set_spi_interface(spi_type):
|
||||||
global global_spi_type
|
global global_spi_type
|
||||||
global_spi_type = spi_type
|
global_spi_type = spi_type
|
||||||
|
|
||||||
def set_using_8b10b(isUsing8b10b):
|
def set_using_8b10b(isUsing8b10b):
|
||||||
global global_using_8b10b
|
global global_using_8b10b
|
||||||
global_using_8b10b = isUsing8b10b
|
global_using_8b10b = isUsing8b10b
|
||||||
|
|
||||||
def set_cdr_type(cdr_type):
|
def set_cdr_type(cdr_type):
|
||||||
global global_cdr_type
|
global global_cdr_type
|
||||||
global_cdr_type = cdr_type
|
global_cdr_type = cdr_type
|
||||||
|
|
||||||
def using_proper_workmode(dev, iface=1):
|
def using_proper_workmode(dev, iface=1):
|
||||||
global global_using_8b10b
|
global global_using_8b10b
|
||||||
global global_spi_type
|
global global_spi_type
|
||||||
global global_cdr_type
|
global global_cdr_type
|
||||||
|
|
||||||
trans_code = 0x0
|
trans_code = 0x0
|
||||||
|
|
||||||
if global_using_8b10b:
|
if global_using_8b10b:
|
||||||
trans_code = 0x1
|
trans_code = 0x1
|
||||||
|
|
||||||
return genIFRwDataCode(dev, 0x09, True, 1, [global_spi_type, ], wlog=False, iface=iface)\
|
return genIFRwDataCode(dev, 0x09, True, 1, [global_spi_type, ], wlog=False, iface=iface)\
|
||||||
+genIFRwDataCode(dev, 0x004c, True, 2, [trans_code, 0x59], wlog = False)\
|
+genIFRwDataCode(dev, 0x004c, True, 2, [trans_code, 0x59], wlog = False)\
|
||||||
+genIFRwDataCode(dev, 0x004e, True, 2, [global_cdr_type, 0x60], wlog = False)
|
+genIFRwDataCode(dev, 0x004e, True, 2, [global_cdr_type, 0x60], wlog = False)
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,190 +1,190 @@
|
|||||||
from pyutils import *
|
from pyutils import *
|
||||||
from .environment import *
|
from .environment import *
|
||||||
|
|
||||||
def tc1():
|
def tc1():
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
dev = get_slv_dev_num()
|
dev = get_slv_dev_num()
|
||||||
print("DEV:", dev)
|
print("DEV:", dev)
|
||||||
|
|
||||||
gen_file_def = "manydev_tc01"
|
gen_file_def = "manydev_tc01"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = f"{dev}个设备， 准备一下开发环境，发送一个广播包。\\n"
|
tc_des = f"{dev}个设备， 准备一下开发环境，发送一个广播包。\\n"
|
||||||
|
|
||||||
|
|
||||||
#-------------------------------------------------------------------------
|
#-------------------------------------------------------------------------
|
||||||
#>>>>>>普通数据包 sm1，2个读
|
#>>>>>>普通数据包 sm1，2个读
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(1)
|
genPkt.setPktType(1)
|
||||||
|
|
||||||
set_if_code = ""
|
set_if_code = ""
|
||||||
for i in range(dev - 4):
|
for i in range(dev - 4):
|
||||||
set_if_code = set_if_code + genIFRwDataCode(i + 5, 0x09, True, 1, [0, ], False, iface=1)
|
set_if_code = set_if_code + genIFRwDataCode(i + 5, 0x09, True, 1, [0, ], False, iface=1)
|
||||||
|
|
||||||
clear_int_code = ""
|
clear_int_code = ""
|
||||||
for i in range(dev + 1):
|
for i in range(dev + 1):
|
||||||
clear_int_code = clear_int_code + genIFRwDataCode(i, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
clear_int_code = clear_int_code + genIFRwDataCode(i, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
|
|
||||||
|
|
||||||
read_int_code = ""
|
read_int_code = ""
|
||||||
for i in range(dev + 1):
|
for i in range(dev + 1):
|
||||||
read_int_code = read_int_code + genIFRwDataCode(i, 0x74, False, 4)
|
read_int_code = read_int_code + genIFRwDataCode(i, 0x74, False, 4)
|
||||||
|
|
||||||
init_slave_code = ""
|
init_slave_code = ""
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
init_slave_code = init_slave_code + genIFRwDataCode(1 + i, 0x0, True, 1, [0x2, ]) + genIFRwDataCode(1 + i, 0x7c, True, 2, [0x10, 0x80])
|
init_slave_code = init_slave_code + genIFRwDataCode(1 + i, 0x0, True, 1, [0x2, ]) + genIFRwDataCode(1 + i, 0x7c, True, 2, [0x10, 0x80])
|
||||||
|
|
||||||
read_dev_code = ""
|
read_dev_code = ""
|
||||||
for i in range(dev + 1):
|
for i in range(dev + 1):
|
||||||
read_dev_code = read_dev_code + genIFRwDataCode(i, 0x0, False, 1)
|
read_dev_code = read_dev_code + genIFRwDataCode(i, 0x0, False, 1)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+genMessageCode("--清除中断")
|
+genMessageCode("--清除中断")
|
||||||
+set_if_code
|
+set_if_code
|
||||||
+init_slave_code
|
+init_slave_code
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
+read_int_code
|
+read_int_code
|
||||||
+read_dev_code
|
+read_dev_code
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
|
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
gen_file_def_ap = gen_file_def + "_step02"
|
gen_file_def_ap = gen_file_def + "_step02"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
data = [0x3f, 0xff]
|
data = [0x3f, 0xff]
|
||||||
genPkt.addSubPkt(0x0, 0, 0x0, 0xb, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x0, 0xb, 2, data)
|
||||||
|
|
||||||
genPkt.addAfterExc(genMessageCode("--设置顺序地址")
|
genPkt.addAfterExc(genMessageCode("--设置顺序地址")
|
||||||
+genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
+genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
#+ "#10000000"
|
#+ "#10000000"
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
|
|
||||||
+genMessageCode("--清除主中断")
|
+genMessageCode("--清除主中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(1)
|
genPkt.setPktType(1)
|
||||||
gen_file_def_ap = gen_file_def+"_step03"
|
gen_file_def_ap = gen_file_def+"_step03"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第二次嗅探"))
|
genPkt.addBeforeExc(genMessageCode("--设置环境，进行第二次嗅探"))
|
||||||
|
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
gen_file_def_ap = gen_file_def+"_step04"
|
gen_file_def_ap = gen_file_def+"_step04"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
||||||
|
|
||||||
prepare_data_code = ""
|
prepare_data_code = ""
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
prepare_data_code = prepare_data_code + genSlvSMWriteData(i + 1, 1, 2, [i, i + 1])
|
prepare_data_code = prepare_data_code + genSlvSMWriteData(i + 1, 1, 2, [i, i + 1])
|
||||||
|
|
||||||
genPkt.addBeforeExc(prepare_data_code)
|
genPkt.addBeforeExc(prepare_data_code)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
#+ "#10000000"
|
#+ "#10000000"
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
gen_file_def_ap = gen_file_def+"_step05"
|
gen_file_def_ap = gen_file_def+"_step05"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
#for i in range(dev):
|
#for i in range(dev):
|
||||||
# genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
# genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
||||||
genPkt.addSubPkt(0, 0, 0x302, 0xe, 2, [8, 0])
|
genPkt.addSubPkt(0, 0, 0x302, 0xe, 2, [8, 0])
|
||||||
genPkt.addSubPkt(0, 0, 0x800, 0xe, 8, list(range(8)))
|
genPkt.addSubPkt(0, 0, 0x800, 0xe, 8, list(range(8)))
|
||||||
|
|
||||||
read_data_code = ""
|
read_data_code = ""
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
read_data_code = read_data_code + genSlvSMReadData(i + 1, 0, 8)
|
read_data_code = read_data_code + genSlvSMReadData(i + 1, 0, 8)
|
||||||
|
|
||||||
#genPkt.addBeforeExc(prepare_data_code)
|
#genPkt.addBeforeExc(prepare_data_code)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
+read_data_code
|
+read_data_code
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
gen_file_def_ap = gen_file_def+"_step06"
|
gen_file_def_ap = gen_file_def+"_step06"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
#for i in range(dev):
|
#for i in range(dev):
|
||||||
# genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
# genPkt.addSubPkt(i + 1, 0, 0x1000, 0x0, 2, [0, 0])
|
||||||
genPkt.addSubPkt(0, 0, 0x302, 0xe, 2, [2, 0])
|
genPkt.addSubPkt(0, 0, 0x302, 0xe, 2, [2, 0])
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
genPkt.addSubPkt(i + 1, 0, 0x0800, 0x1, 2, [i & 0xff, (i + 1) & 0xff])
|
genPkt.addSubPkt(i + 1, 0, 0x0800, 0x1, 2, [i & 0xff, (i + 1) & 0xff])
|
||||||
|
|
||||||
read_data_code = ""
|
read_data_code = ""
|
||||||
for i in range(dev):
|
for i in range(dev):
|
||||||
read_data_code = read_data_code + genSlvSMReadData(i + 1, 0, 2)
|
read_data_code = read_data_code + genSlvSMReadData(i + 1, 0, 2)
|
||||||
|
|
||||||
#genPkt.addBeforeExc(prepare_data_code)
|
#genPkt.addBeforeExc(prepare_data_code)
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
+genWriteTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
+genTrgTransPktCode(gen_file_def_ap, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
+genReadAckPktCode(gen_file_def_ap, sm_idx)
|
||||||
|
|
||||||
+clear_int_code
|
+clear_int_code
|
||||||
+read_data_code
|
+read_data_code
|
||||||
|
|
||||||
+genTcEndFrameCode(gen_file_def)
|
+genTcEndFrameCode(gen_file_def)
|
||||||
)
|
)
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)
|
||||||
|
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
@@ -1,224 +1,224 @@
|
|||||||
from pyutils import *
|
from pyutils import *
|
||||||
from .environment import *
|
from .environment import *
|
||||||
|
|
||||||
import time
|
import time
|
||||||
import random
|
import random
|
||||||
|
|
||||||
def tc1():
|
def tc1():
|
||||||
gen_file_def = "regtest_tc01"
|
gen_file_def = "regtest_tc01"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "测试寄存器的读写状态，将系统改为8B10B进行通信。特别测试SPI/QSPI读写密码正确和不正确的情况下，对读写的封堵。\\n"
|
tc_des = "测试寄存器的读写状态，将系统改为8B10B进行通信。特别测试SPI/QSPI读写密码正确和不正确的情况下，对读写的封堵。\\n"
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
dev_num = get_slv_dev_num()
|
dev_num = get_slv_dev_num()
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
|
||||||
|
|
||||||
change_8b10b_code1 = ""
|
change_8b10b_code1 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
change_8b10b_code1 = change_8b10b_code1 + genIFRwDataCode(i, 0x004c, True, 2, [0x0, 0x59])\
|
change_8b10b_code1 = change_8b10b_code1 + genIFRwDataCode(i, 0x004c, True, 2, [0x0, 0x59])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
change_8b10b_code2 = ""
|
change_8b10b_code2 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
change_8b10b_code2 = change_8b10b_code2 + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x59])\
|
change_8b10b_code2 = change_8b10b_code2 + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x59])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code1 = ""
|
invalid_change_8b10b_code1 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code1 = invalid_change_8b10b_code1 + genIFRwDataCode(i, 0x004c, True, 2, [0x0, 0x32])\
|
invalid_change_8b10b_code1 = invalid_change_8b10b_code1 + genIFRwDataCode(i, 0x004c, True, 2, [0x0, 0x32])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code2 = ""
|
invalid_change_8b10b_code2 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code2 = invalid_change_8b10b_code2 + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x43])\
|
invalid_change_8b10b_code2 = invalid_change_8b10b_code2 + genIFRwDataCode(i, 0x004c, True, 2, [0x1, 0x43])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code3 = ""
|
invalid_change_8b10b_code3 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code3 = invalid_change_8b10b_code3 + genIFRwDataCode(i, 0x004c, True, 1, [0x0, ])\
|
invalid_change_8b10b_code3 = invalid_change_8b10b_code3 + genIFRwDataCode(i, 0x004c, True, 1, [0x0, ])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code4 = ""
|
invalid_change_8b10b_code4 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code4 = invalid_change_8b10b_code4 + genIFRwDataCode(i, 0x004c, True, 1, [0x1, ])\
|
invalid_change_8b10b_code4 = invalid_change_8b10b_code4 + genIFRwDataCode(i, 0x004c, True, 1, [0x1, ])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code5 = ""
|
invalid_change_8b10b_code5 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code5 = invalid_change_8b10b_code5 + genIFRwDataCode(i, 0x004c, True, 2, [0x30, 0x59])\
|
invalid_change_8b10b_code5 = invalid_change_8b10b_code5 + genIFRwDataCode(i, 0x004c, True, 2, [0x30, 0x59])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
invalid_change_8b10b_code6 = ""
|
invalid_change_8b10b_code6 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_8b10b_code6 = invalid_change_8b10b_code6 + genIFRwDataCode(i, 0x004c, True, 2, [0x23, 0x59])\
|
invalid_change_8b10b_code6 = invalid_change_8b10b_code6 + genIFRwDataCode(i, 0x004c, True, 2, [0x23, 0x59])\
|
||||||
+genIFRwDataCode(i, 0x004c, False, 2)
|
+genIFRwDataCode(i, 0x004c, False, 2)
|
||||||
|
|
||||||
default_trans_code = ""
|
default_trans_code = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
default_trans_code = default_trans_code + using_proper_workmode(i, iface = 4)
|
default_trans_code = default_trans_code + using_proper_workmode(i, iface = 4)
|
||||||
|
|
||||||
genPkt.addAfterExc(genMessageCode("--正确的key")
|
genPkt.addAfterExc(genMessageCode("--正确的key")
|
||||||
+change_8b10b_code1
|
+change_8b10b_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code4
|
+invalid_change_8b10b_code4
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code1
|
+invalid_change_8b10b_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code2
|
+invalid_change_8b10b_code2
|
||||||
+genMessageCode("--正确的key")
|
+genMessageCode("--正确的key")
|
||||||
+change_8b10b_code2
|
+change_8b10b_code2
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code3
|
+invalid_change_8b10b_code3
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code1
|
+invalid_change_8b10b_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_8b10b_code2
|
+invalid_change_8b10b_code2
|
||||||
+genMessageCode("--正确的key_错误的数据")
|
+genMessageCode("--正确的key_错误的数据")
|
||||||
+invalid_change_8b10b_code5
|
+invalid_change_8b10b_code5
|
||||||
+invalid_change_8b10b_code6
|
+invalid_change_8b10b_code6
|
||||||
+genMessageCode("--恢复默认的配置")
|
+genMessageCode("--恢复默认的配置")
|
||||||
+default_trans_code
|
+default_trans_code
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|
||||||
def tc2():
|
def tc2():
|
||||||
gen_file_def = "regtest_tc02"
|
gen_file_def = "regtest_tc02"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "测试寄存器的读写状态，交换上下行管脚。特别测试SPI/QSPI读写密码正确和不正确的情况下，对读写的封堵。\\n"
|
tc_des = "测试寄存器的读写状态，交换上下行管脚。特别测试SPI/QSPI读写密码正确和不正确的情况下，对读写的封堵。\\n"
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
|
|
||||||
dev_num = get_slv_dev_num()
|
dev_num = get_slv_dev_num()
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
|
||||||
|
|
||||||
change_pinsw_code1 = ""
|
change_pinsw_code1 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
change_pinsw_code1 = change_pinsw_code1 + genIFRwDataCode(i, 0x004a, True, 2, [0x0, 0x58])\
|
change_pinsw_code1 = change_pinsw_code1 + genIFRwDataCode(i, 0x004a, True, 2, [0x0, 0x58])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
change_pinsw_code2 = ""
|
change_pinsw_code2 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
change_pinsw_code2 = change_pinsw_code2 + genIFRwDataCode(i, 0x004a, True, 2, [0x1, 0x58])\
|
change_pinsw_code2 = change_pinsw_code2 + genIFRwDataCode(i, 0x004a, True, 2, [0x1, 0x58])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code1 = ""
|
invalid_change_pinsw_code1 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code1 = invalid_change_pinsw_code1 + genIFRwDataCode(i, 0x004a, True, 2, [0x0, 0x32])\
|
invalid_change_pinsw_code1 = invalid_change_pinsw_code1 + genIFRwDataCode(i, 0x004a, True, 2, [0x0, 0x32])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code2 = ""
|
invalid_change_pinsw_code2 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code2 = invalid_change_pinsw_code2 + genIFRwDataCode(i, 0x004a, True, 2, [0x1, 0x43])\
|
invalid_change_pinsw_code2 = invalid_change_pinsw_code2 + genIFRwDataCode(i, 0x004a, True, 2, [0x1, 0x43])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code3 = ""
|
invalid_change_pinsw_code3 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code3 = invalid_change_pinsw_code3 + genIFRwDataCode(i, 0x004a, True, 1, [0x0, ])\
|
invalid_change_pinsw_code3 = invalid_change_pinsw_code3 + genIFRwDataCode(i, 0x004a, True, 1, [0x0, ])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code4 = ""
|
invalid_change_pinsw_code4 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code4 = invalid_change_pinsw_code4 + genIFRwDataCode(i, 0x004a, True, 1, [0x1, ])\
|
invalid_change_pinsw_code4 = invalid_change_pinsw_code4 + genIFRwDataCode(i, 0x004a, True, 1, [0x1, ])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code5 = ""
|
invalid_change_pinsw_code5 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code5 = invalid_change_pinsw_code5 + genIFRwDataCode(i, 0x004a, True, 2, [0x30, 0x58])\
|
invalid_change_pinsw_code5 = invalid_change_pinsw_code5 + genIFRwDataCode(i, 0x004a, True, 2, [0x30, 0x58])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
invalid_change_pinsw_code6 = ""
|
invalid_change_pinsw_code6 = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
invalid_change_pinsw_code6 = invalid_change_pinsw_code6 + genIFRwDataCode(i, 0x004a, True, 2, [0x23, 0x58])\
|
invalid_change_pinsw_code6 = invalid_change_pinsw_code6 + genIFRwDataCode(i, 0x004a, True, 2, [0x23, 0x58])\
|
||||||
+genIFRwDataCode(i, 0x004a, False, 2)
|
+genIFRwDataCode(i, 0x004a, False, 2)
|
||||||
|
|
||||||
default_pinsw_code = ""
|
default_pinsw_code = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
default_pinsw_code = default_pinsw_code + genIFRwDataCode(i, 0x004a, True, 2, [0, 0x58])
|
default_pinsw_code = default_pinsw_code + genIFRwDataCode(i, 0x004a, True, 2, [0, 0x58])
|
||||||
|
|
||||||
genPkt.addAfterExc(genMessageCode("--正确的key")
|
genPkt.addAfterExc(genMessageCode("--正确的key")
|
||||||
+change_pinsw_code1
|
+change_pinsw_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code4
|
+invalid_change_pinsw_code4
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code1
|
+invalid_change_pinsw_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code2
|
+invalid_change_pinsw_code2
|
||||||
+genMessageCode("--正确的key")
|
+genMessageCode("--正确的key")
|
||||||
+change_pinsw_code2
|
+change_pinsw_code2
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code3
|
+invalid_change_pinsw_code3
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code1
|
+invalid_change_pinsw_code1
|
||||||
+genMessageCode("--错误的key")
|
+genMessageCode("--错误的key")
|
||||||
+invalid_change_pinsw_code2
|
+invalid_change_pinsw_code2
|
||||||
+genMessageCode("--正确的key_错误的数据")
|
+genMessageCode("--正确的key_错误的数据")
|
||||||
+invalid_change_pinsw_code5
|
+invalid_change_pinsw_code5
|
||||||
+invalid_change_pinsw_code6
|
+invalid_change_pinsw_code6
|
||||||
+genMessageCode("--恢复默认的配置")
|
+genMessageCode("--恢复默认的配置")
|
||||||
+default_pinsw_code
|
+default_pinsw_code
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
def tc3():
|
def tc3():
|
||||||
gen_file_def = "regtest_tc03"
|
gen_file_def = "regtest_tc03"
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
tc_des = "测试SM0~SM7的的长度寄存器的读写，要求在内部有元素的情况下，不能改写其长度。\\n"
|
tc_des = "测试SM0~SM7的的长度寄存器的读写，要求在内部有元素的情况下，不能改写其长度。\\n"
|
||||||
|
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
dev_num = get_slv_dev_num()
|
dev_num = get_slv_dev_num()
|
||||||
|
|
||||||
chang_sm_length = ""
|
chang_sm_length = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
chang_sm_length = chang_sm_length + genIFRwDataCode(i, 0x0302, True, 2, [0x20, 0x00])
|
chang_sm_length = chang_sm_length + genIFRwDataCode(i, 0x0302, True, 2, [0x20, 0x00])
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+chang_sm_length
|
+chang_sm_length
|
||||||
+genMessageCode("--清除主中断")
|
+genMessageCode("--清除主中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
)
|
)
|
||||||
|
|
||||||
genPkt.addSubPkt(0x0, 0x0, 0x0800, 0xe, 0x20, [0, ] * 0x20)
|
genPkt.addSubPkt(0x0, 0x0, 0x0800, 0xe, 0x20, [0, ] * 0x20)
|
||||||
|
|
||||||
chang_sm_length = ""
|
chang_sm_length = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
chang_sm_length = chang_sm_length + genIFRwDataCode(i, 0x0302, True, 2, [0x40, 0x00])
|
chang_sm_length = chang_sm_length + genIFRwDataCode(i, 0x0302, True, 2, [0x40, 0x00])
|
||||||
|
|
||||||
read_sm_status = ""
|
read_sm_status = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
read_sm_status = read_sm_status + genIFRwDataCode(i, 0x0300, False, 4)
|
read_sm_status = read_sm_status + genIFRwDataCode(i, 0x0300, False, 4)
|
||||||
|
|
||||||
reset_sm = ""
|
reset_sm = ""
|
||||||
for i in range(dev_num + 1):
|
for i in range(dev_num + 1):
|
||||||
reset_sm = reset_sm + genIFRwDataCode(i, 0x0300, True, 1, [0, ])
|
reset_sm = reset_sm + genIFRwDataCode(i, 0x0300, True, 1, [0, ])
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
+chang_sm_length
|
+chang_sm_length
|
||||||
+read_sm_status
|
+read_sm_status
|
||||||
+reset_sm
|
+reset_sm
|
||||||
+read_sm_status
|
+read_sm_status
|
||||||
+genMessageCode("--清除主中断")
|
+genMessageCode("--清除主中断")
|
||||||
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,370 +1,370 @@
|
|||||||
from pyutils import *
|
from pyutils import *
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
'''
|
'''
|
||||||
看门狗0超时逻辑：
|
看门狗0超时逻辑：
|
||||||
1. 看门狗0从系统发送下行包时，触发工作；
|
1. 看门狗0从系统发送下行包时，触发工作；
|
||||||
2. 系统上行时，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作，此时有上行包，不予响应；
|
2. 系统上行时，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作，此时有上行包，不予响应；
|
||||||
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
||||||
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
||||||
|
|
||||||
|
|
||||||
SM0/2/4/6与SM1/3/5/7超时逻辑：
|
SM0/2/4/6与SM1/3/5/7超时逻辑：
|
||||||
1. 看门狗从读写第一个字节被触发计时工作；第二次读写第一个字节，不影响看门狗工作；
|
1. 看门狗从读写第一个字节被触发计时工作；第二次读写第一个字节，不影响看门狗工作；
|
||||||
2. 读写最后一个字节，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作，此时系统读到最后一个字节，不予响应。
|
2. 读写最后一个字节，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作，此时系统读到最后一个字节，不予响应。
|
||||||
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
||||||
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
||||||
|
|
||||||
看门狗17超时逻辑：
|
看门狗17超时逻辑：
|
||||||
1. 看门狗17从系统发送第一个下行包时，触发工作；
|
1. 看门狗17从系统发送第一个下行包时，触发工作；
|
||||||
2. 系统发送第二个下行包时，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作；
|
2. 系统发送第二个下行包时，停止看门狗工作并复位看门狗计数器；若发生超时，报超时状态，复位继续工作；
|
||||||
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
3. 看门狗不使能，则对应的看门狗停止工作，也不会报相关的状态位与中断；
|
||||||
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
4. 写对应的看门狗状态寄存器，对应看门狗被复位；需要重新触发才能工作。
|
||||||
|
|
||||||
|
|
||||||
复位继续工作，指看门狗需要重新被触发开始计数直至超时或者复位。写看门狗状态，无论超时没超时，对应bit为1，则对应看门狗被复位。
|
复位继续工作，指看门狗需要重新被触发开始计数直至超时或者复位。写看门狗状态，无论超时没超时，对应bit为1，则对应看门狗被复位。
|
||||||
'''
|
'''
|
||||||
|
|
||||||
def watchdog_test_sm_wr_timeout(tc_id, wd_id):
|
def watchdog_test_sm_wr_timeout(tc_id, wd_id):
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
slave_sm_id = int((wd_id - 1) / 2)
|
slave_sm_id = int((wd_id - 1) / 2)
|
||||||
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只写一半，看Watchdog是否超时。\\n"
|
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只写一半，看Watchdog是否超时。\\n"
|
||||||
"清除中断后，错误消失，出问题的设备恢复正常。"
|
"清除中断后，错误消失，出问题的设备恢复正常。"
|
||||||
)
|
)
|
||||||
|
|
||||||
#--------------------------------------------------------------------------
|
#--------------------------------------------------------------------------
|
||||||
#>>>>>> 测试用例1 看门狗测试
|
#>>>>>> 测试用例1 看门狗测试
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
data = 1 << wd_id ##使能看门狗
|
data = 1 << wd_id ##使能看门狗
|
||||||
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0x002000 ##看门狗的超时值
|
data = 0x002000 ##看门狗的超时值
|
||||||
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0xffffffff ##清除中断
|
data = 0xffffffff ##清除中断
|
||||||
data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
||||||
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
||||||
+ genIFRwDataCode(1, 0x078, True, 4, data2)
|
+ genIFRwDataCode(1, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(2, 0x078, True, 4, data2)
|
+ genIFRwDataCode(2, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(3, 0x078, True, 4, data2)
|
+ genIFRwDataCode(3, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(4, 0x078, True, 4, data2)
|
+ genIFRwDataCode(4, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x400, False, 0x04))
|
+ genIFRwDataCode(1, 0x400, False, 0x04))
|
||||||
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
||||||
|
|
||||||
data = [0,] * 2
|
data = [0,] * 2
|
||||||
data[0] = 0x80
|
data[0] = 0x80
|
||||||
data[1] = 0x00
|
data[1] = 0x00
|
||||||
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
||||||
|
|
||||||
data = [0,] * 0x50
|
data = [0,] * 0x50
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
sm_addr = slave_sm_id * 0x1000 + 0x800
|
sm_addr = slave_sm_id * 0x1000 + 0x800
|
||||||
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x50, data)
|
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x50, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
+genMessageCode("--检查中断寄存器")
|
+genMessageCode("--检查中断寄存器")
|
||||||
+genIFRwDataCode(0, 0x074, False, 0x04)
|
+genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(2, 0x074, False, 0x04)
|
+genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(3, 0x074, False, 0x04)
|
+genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(4, 0x074, False, 0x04)
|
+genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#700000\n"
|
+"#700000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genMessageCode("--复位数据缓冲区")
|
+genMessageCode("--复位数据缓冲区")
|
||||||
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#1200000\n"
|
+"#1200000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
def watchdog_test_sm_wr_no_timeout(tc_id, wd_id):
|
def watchdog_test_sm_wr_no_timeout(tc_id, wd_id):
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
slave_sm_id = int((wd_id - 1) / 2)
|
slave_sm_id = int((wd_id - 1) / 2)
|
||||||
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只写一半，看Watchdog是否超时。\\n"
|
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只写一半，看Watchdog是否超时。\\n"
|
||||||
"清除中断后，错误消失，出问题的设备恢复正常。"
|
"清除中断后，错误消失，出问题的设备恢复正常。"
|
||||||
)
|
)
|
||||||
|
|
||||||
#--------------------------------------------------------------------------
|
#--------------------------------------------------------------------------
|
||||||
#>>>>>> 测试用例1 看门狗测试
|
#>>>>>> 测试用例1 看门狗测试
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
data = 1 << wd_id ##使能看门狗
|
data = 1 << wd_id ##使能看门狗
|
||||||
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0x002000 ##看门狗的超时值
|
data = 0x002000 ##看门狗的超时值
|
||||||
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0xffffffff ##清除中断
|
data = 0xffffffff ##清除中断
|
||||||
data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
||||||
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
||||||
+ genIFRwDataCode(1, 0x078, True, 4, data2)
|
+ genIFRwDataCode(1, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(2, 0x078, True, 4, data2)
|
+ genIFRwDataCode(2, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(3, 0x078, True, 4, data2)
|
+ genIFRwDataCode(3, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(4, 0x078, True, 4, data2)
|
+ genIFRwDataCode(4, 0x078, True, 4, data2)
|
||||||
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x400, False, 0x04))
|
+ genIFRwDataCode(1, 0x400, False, 0x04))
|
||||||
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
||||||
|
|
||||||
data = [0,] * 2
|
data = [0,] * 2
|
||||||
data[0] = 0x80
|
data[0] = 0x80
|
||||||
data[1] = 0x00
|
data[1] = 0x00
|
||||||
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
||||||
|
|
||||||
data = [0,] * 0x80
|
data = [0,] * 0x80
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
sm_addr = slave_sm_id * 0x1000 + 0x800
|
sm_addr = slave_sm_id * 0x1000 + 0x800
|
||||||
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x80, data)
|
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x80, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
+genMessageCode("--检查中断寄存器")
|
+genMessageCode("--检查中断寄存器")
|
||||||
+genIFRwDataCode(0, 0x074, False, 0x04)
|
+genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(2, 0x074, False, 0x04)
|
+genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(3, 0x074, False, 0x04)
|
+genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(4, 0x074, False, 0x04)
|
+genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#700000\n"
|
+"#700000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genMessageCode("--复位数据缓冲区")
|
+genMessageCode("--复位数据缓冲区")
|
||||||
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#1200000\n"
|
+"#1200000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|
||||||
def watchdog_test_sm_rd_timeout(tc_id, wd_id):
|
def watchdog_test_sm_rd_timeout(tc_id, wd_id):
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
slave_sm_id = int((wd_id - 1) / 2)
|
slave_sm_id = int((wd_id - 1) / 2)
|
||||||
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只读一半，看Watchdog是否超时。\\n"
|
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只读一半，看Watchdog是否超时。\\n"
|
||||||
"清除中断后，错误消失，出问题的设备恢复正常。"
|
"清除中断后，错误消失，出问题的设备恢复正常。"
|
||||||
)
|
)
|
||||||
|
|
||||||
#--------------------------------------------------------------------------
|
#--------------------------------------------------------------------------
|
||||||
#>>>>>> 测试用例1 看门狗测试
|
#>>>>>> 测试用例1 看门狗测试
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
data = 1 << wd_id ##使能看门狗
|
data = 1 << wd_id ##使能看门狗
|
||||||
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0x002000 ##看门狗的超时值
|
data = 0x002000 ##看门狗的超时值
|
||||||
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
||||||
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
||||||
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(2, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(2, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(3, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(3, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(4, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(4, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x400, False, 0x04)
|
+ genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
)
|
)
|
||||||
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
||||||
|
|
||||||
data = [0,] * 2
|
data = [0,] * 2
|
||||||
data[0] = 0x10
|
data[0] = 0x10
|
||||||
data[1] = 0x00
|
data[1] = 0x00
|
||||||
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
||||||
|
|
||||||
data = list(range(0x10))
|
data = list(range(0x10))
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
sm_addr = slave_sm_id * 0x1000 + 0x800
|
sm_addr = slave_sm_id * 0x1000 + 0x800
|
||||||
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x10, data)
|
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x10, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
+genMessageCode("--检查中断寄存器")
|
+genMessageCode("--检查中断寄存器")
|
||||||
+genIFRwDataCode(0, 0x074, False, 0x04)
|
+genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(2, 0x074, False, 0x04)
|
+genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(3, 0x074, False, 0x04)
|
+genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(4, 0x074, False, 0x04)
|
+genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+genMessageCode("--读缓冲区")
|
+genMessageCode("--读缓冲区")
|
||||||
+genIFRwDataCode(1, 0x800 + slave_sm_id * 0x1000, False, 8)
|
+genIFRwDataCode(1, 0x800 + slave_sm_id * 0x1000, False, 8)
|
||||||
|
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#2000000\n"
|
+"#2000000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genMessageCode("--复位数据缓冲区")
|
+genMessageCode("--复位数据缓冲区")
|
||||||
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#2000000\n"
|
+"#2000000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
|
|
||||||
def watchdog_test_sm_rd_no_timeout(tc_id, wd_id):
|
def watchdog_test_sm_rd_no_timeout(tc_id, wd_id):
|
||||||
genPkt = GenPkt()
|
genPkt = GenPkt()
|
||||||
|
|
||||||
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
gen_file_def = "watchdog_tc%02d"%(tc_id, )
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
slave_sm_id = int((wd_id - 1) / 2)
|
slave_sm_id = int((wd_id - 1) / 2)
|
||||||
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只读一半，看Watchdog是否超时。\\n"
|
tc_des = (f"使能看门狗{wd_id}，监视SM{slave_sm_id}，写数据到SM中，只读一半，看Watchdog是否超时。\\n"
|
||||||
"清除中断后，错误消失，出问题的设备恢复正常。"
|
"清除中断后，错误消失，出问题的设备恢复正常。"
|
||||||
)
|
)
|
||||||
|
|
||||||
#--------------------------------------------------------------------------
|
#--------------------------------------------------------------------------
|
||||||
#>>>>>> 测试用例1 看门狗测试
|
#>>>>>> 测试用例1 看门狗测试
|
||||||
genPkt.clean()
|
genPkt.clean()
|
||||||
genPkt.setPktType(0)
|
genPkt.setPktType(0)
|
||||||
|
|
||||||
data = 1 << wd_id ##使能看门狗
|
data = 1 << wd_id ##使能看门狗
|
||||||
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
data = 0x002000 ##看门狗的超时值
|
data = 0x002000 ##看门狗的超时值
|
||||||
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff]
|
||||||
|
|
||||||
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
|
||||||
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
+ genIFRwDataCode(1, 0x404, True, 4, data0)
|
||||||
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
+ genIFRwDataCode(1, 0x40C + (wd_id - 1) * 4, True, 4, data1)
|
||||||
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(0, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(2, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(2, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(3, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(3, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(4, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(4, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+ genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
+ genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
+ genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
+ genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
+ genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
+ genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+ genIFRwDataCode(1, 0x400, False, 0x04)
|
+ genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
)
|
)
|
||||||
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
#genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff]))
|
||||||
|
|
||||||
data = [0,] * 2
|
data = [0,] * 2
|
||||||
data[0] = 0x10
|
data[0] = 0x10
|
||||||
data[1] = 0x00
|
data[1] = 0x00
|
||||||
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
genPkt.addSubPkt(0x0, 0, 0x302 + slave_sm_id * 4, 0xe, 2, data)
|
||||||
|
|
||||||
data = list(range(0x10))
|
data = list(range(0x10))
|
||||||
|
|
||||||
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
#subPkt参数：索引、索引类型、地址、命令、长度、数据
|
||||||
sm_addr = slave_sm_id * 0x1000 + 0x800
|
sm_addr = slave_sm_id * 0x1000 + 0x800
|
||||||
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x10, data)
|
genPkt.addSubPkt(1, 0, sm_addr, 0x1, 0x10, data)
|
||||||
|
|
||||||
sm_idx = 0
|
sm_idx = 0
|
||||||
|
|
||||||
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
|
||||||
+genWriteTransPktCode(gen_file_def, sm_idx)
|
+genWriteTransPktCode(gen_file_def, sm_idx)
|
||||||
+genTrgTransPktCode(gen_file_def, sm_idx)
|
+genTrgTransPktCode(gen_file_def, sm_idx)
|
||||||
+genReadAckPktCode(gen_file_def, sm_idx)
|
+genReadAckPktCode(gen_file_def, sm_idx)
|
||||||
+genMessageCode("--检查中断寄存器")
|
+genMessageCode("--检查中断寄存器")
|
||||||
+genIFRwDataCode(0, 0x074, False, 0x04)
|
+genIFRwDataCode(0, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(2, 0x074, False, 0x04)
|
+genIFRwDataCode(2, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(3, 0x074, False, 0x04)
|
+genIFRwDataCode(3, 0x074, False, 0x04)
|
||||||
+genIFRwDataCode(4, 0x074, False, 0x04)
|
+genIFRwDataCode(4, 0x074, False, 0x04)
|
||||||
+genMessageCode("--读缓冲区")
|
+genMessageCode("--读缓冲区")
|
||||||
+genIFRwDataCode(1, 0x800 + slave_sm_id * 0x1000, False, 0x10)
|
+genIFRwDataCode(1, 0x800 + slave_sm_id * 0x1000, False, 0x10)
|
||||||
|
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#2000000\n"
|
+"#2000000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
+genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff])
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genMessageCode("--复位数据缓冲区")
|
+genMessageCode("--复位数据缓冲区")
|
||||||
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
+genIFRwDataCode(1, 0x300 + slave_sm_id * 4, True, 1, [0, ])
|
||||||
+genMessageCode("--延时后检查看门狗寄存器")
|
+genMessageCode("--延时后检查看门狗寄存器")
|
||||||
+"#2000000\n"
|
+"#2000000\n"
|
||||||
+genIFRwDataCode(1, 0x400, False, 0x04)
|
+genIFRwDataCode(1, 0x400, False, 0x04)
|
||||||
+genIFRwDataCode(1, 0x074, False, 0x04)
|
+genIFRwDataCode(1, 0x074, False, 0x04)
|
||||||
+genTcEndFrameCode(gen_file_def))
|
+genTcEndFrameCode(gen_file_def))
|
||||||
|
|
||||||
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
|
||||||
|
|
||||||
return gen_file_def
|
return gen_file_def
|
||||||
|
|
||||||
def tc1():
|
def tc1():
|
||||||
return watchdog_test_sm_wr_timeout(1, 1)
|
return watchdog_test_sm_wr_timeout(1, 1)
|
||||||
|
|
||||||
|
|
||||||
def tc2():
|
def tc2():
|
||||||
return watchdog_test_sm_rd_timeout(2, 2)
|
return watchdog_test_sm_rd_timeout(2, 2)
|
||||||
|
|
||||||
def tc3():
|
def tc3():
|
||||||
return watchdog_test_sm_wr_no_timeout(3, 1)
|
return watchdog_test_sm_wr_no_timeout(3, 1)
|
||||||
|
|
||||||
def tc4():
|
def tc4():
|
||||||
return watchdog_test_sm_rd_no_timeout(4, 2)
|
return watchdog_test_sm_rd_no_timeout(4, 2)
|
||||||
@@ -1,100 +1,100 @@
|
|||||||
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
16'h004c 8'h00 16'h0002 8'h00 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h01
|
16'h004c 8'h00 16'h0001 8'h01
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h01
|
16'h004c 8'h00 16'h0001 8'h01
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h01
|
16'h004c 8'h00 16'h0001 8'h01
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h01
|
16'h004c 8'h00 16'h0001 8'h01
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h01
|
16'h004c 8'h00 16'h0001 8'h01
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
16'h004c 8'h00 16'h0002 8'h01 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h00
|
16'h004c 8'h00 16'h0001 8'h00
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h00
|
16'h004c 8'h00 16'h0001 8'h00
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h00
|
16'h004c 8'h00 16'h0001 8'h00
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h00
|
16'h004c 8'h00 16'h0001 8'h00
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0001 8'h00
|
16'h004c 8'h00 16'h0001 8'h00
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
16'h004c 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
16'h004c 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
16'h004c 8'h00 16'h0002 8'h30 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
16'h004c 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
16'h004c 8'h00 16'h0002 8'h23 8'h59
|
||||||
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
16'h004c 8'h80 16'h0002 8'h01 8'h00
|
||||||
|
|||||||
@@ -1,105 +1,105 @@
|
|||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h01
|
16'h004a 8'h00 16'h0001 8'h01
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h01
|
16'h004a 8'h00 16'h0001 8'h01
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h01
|
16'h004a 8'h00 16'h0001 8'h01
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h01
|
16'h004a 8'h00 16'h0001 8'h01
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h01
|
16'h004a 8'h00 16'h0001 8'h01
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
16'h004a 8'h00 16'h0002 8'h01 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h00
|
16'h004a 8'h00 16'h0001 8'h00
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h00
|
16'h004a 8'h00 16'h0001 8'h00
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h00
|
16'h004a 8'h00 16'h0001 8'h00
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h00
|
16'h004a 8'h00 16'h0001 8'h00
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0001 8'h00
|
16'h004a 8'h00 16'h0001 8'h00
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
16'h004a 8'h00 16'h0002 8'h00 8'h32
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
16'h004a 8'h00 16'h0002 8'h01 8'h43
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
16'h004a 8'h00 16'h0002 8'h30 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
16'h004a 8'h80 16'h0002 8'h00 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
16'h004a 8'h00 16'h0002 8'h23 8'h58
|
||||||
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
16'h004a 8'h80 16'h0002 8'h01 8'h00
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
16'h004a 8'h00 16'h0002 8'h00 8'h58
|
||||||
|
|||||||
@@ -1,36 +1,36 @@
|
|||||||
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
16'h0302 8'h00 16'h0002 8'h20 8'h00
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
16'h0302 8'h00 16'h0002 8'h2c 8'h00
|
16'h0302 8'h00 16'h0002 8'h2c 8'h00
|
||||||
16'h0306 8'h00 16'h0002 8'h2c 8'h00
|
16'h0306 8'h00 16'h0002 8'h2c 8'h00
|
||||||
16'h1000 8'h00 16'h002c 8'h02 8'h80 8'h00 8'h00 8'h00 8'h00 8'h08 8'h00 8'he0 8'h20 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00
|
16'h1000 8'h00 16'h002c 8'h02 8'h80 8'h00 8'h00 8'h00 8'h00 8'h08 8'h00 8'he0 8'h20 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00
|
||||||
16'h0020 8'h00 16'h0001 8'h01
|
16'h0020 8'h00 16'h0001 8'h01
|
||||||
16'h0800 8'h80 16'h002c 8'h02 8'h80 8'h00 8'h04 8'h00 8'h00 8'h08 8'h00 8'he0 8'h20 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h04
|
16'h0800 8'h80 16'h002c 8'h02 8'h80 8'h00 8'h04 8'h00 8'h00 8'h08 8'h00 8'he0 8'h20 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h04
|
||||||
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
||||||
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
16'h0302 8'h00 16'h0002 8'h40 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h40 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h40 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h01 8'h20 8'h00
|
||||||
16'h0300 8'h00 16'h0001 8'h00
|
16'h0300 8'h00 16'h0001 8'h00
|
||||||
16'h0300 8'h00 16'h0001 8'h00
|
16'h0300 8'h00 16'h0001 8'h00
|
||||||
16'h0300 8'h00 16'h0001 8'h00
|
16'h0300 8'h00 16'h0001 8'h00
|
||||||
16'h0300 8'h00 16'h0001 8'h00
|
16'h0300 8'h00 16'h0001 8'h00
|
||||||
16'h0300 8'h00 16'h0001 8'h00
|
16'h0300 8'h00 16'h0001 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h40 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h40 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
||||||
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
16'h0300 8'h80 16'h0004 8'h00 8'h00 8'h20 8'h00
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff
|
||||||
|
|||||||
Reference in New Issue
Block a user