240 lines
7.3 KiB
Scala
240 lines
7.3 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class QSPIInterfaceIO extends Bundle{
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val sck = Input(Bool())
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val mosi = Input(UInt(4.W))
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val miso = Output(UInt(4.W))
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val isDirIn = Output(Bool())
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val csn = Input(Bool())
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}
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class SSPIInterfaceIO extends Bundle{
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val sck = Input(Bool())
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val mosi = Input(Bool())
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val miso = Output(Bool())
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val csn = Input(Bool())
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}
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class RegAccessInterfaceIO extends Bundle{
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val addrw = Output(UInt(16.W))
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val addrr = Output(UInt(16.W))
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val dataw = Output( UInt(8.W) )
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val datar = Input( UInt(8.W) )
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val isEnW = Output(Bool())
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val isEnR = Output(Bool())
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}
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abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
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val io = IO(new RegAccessInterfaceIO)
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val sck = Wire(Bool())
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val csn = Wire(Bool())
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//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
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val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
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val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
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val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
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val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
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val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
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val exRego = RegInit(0.U(8.W))
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val exRegi = RegInit(0.U(8.W))
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val addrw = RegInit(0.U(16.W))
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val addrr = RegInit(0.U(16.W))
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val spiCmd = RegInit(0.U(1.W))
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val isSpiWrite = spiCmd === 0.U
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val isSpiRead = spiCmd === 1.U
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val bitSel = RegInit(0.U(3.W))
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val bitSelNext = RegNext(bitSel, 0.U(3.W))
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val byteSel = RegInit(0.U(12.W))
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val byteSelNext = RegNext(byteSel, 0.U(12.W))
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io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
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io.dataw := exRegi
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io.addrr := addrr
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io.addrw := addrw
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when( shiftCSn(2) & ~shiftCSn(1) ){
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byteSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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when( bitSel.andR ){
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byteSel := byteSel + 1.U
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}
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}
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}
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class SSpiInterface extends SpiInterfaceBase{
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val spi = IO(new SSPIInterfaceIO)
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val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
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sck := spi.sck
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csn := spi.csn
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io.isEnR :=
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(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === 1.U & byteSel === 2.U ) |
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(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U )
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when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
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spiCmd := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
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spiCmd := shiftMOSI(1)
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}
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spi.miso := exRego.extract(7)
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := bitSel + 1.U
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}
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//输入看SCK上升沿
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when( isSckPosedge & ~shiftCSn(1) ){
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when( bitSel === 0.U ){
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exRegi := Cat( 0.U, shiftMOSI(1) )
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}.otherwise{
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exRegi := Cat( exRegi(6,0), shiftMOSI(1) )
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}
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}
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//输出在SCK上升沿准备数据
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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exRego := 0.U //第一个byte 地址0
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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when( bitSel.andR ){
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when((byteSel === 0.U || byteSel === 1.U) ){
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exRego := 0.U //地址1，cmd
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} .elsewhen( isSpiRead ){
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exRego := io.datar
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}
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}.otherwise{
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exRego := exRego << 1
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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addrr := 0.U
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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addrr := Cat( exRegi(6,0), shiftMOSI(1) )
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
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} .otherwise{ // byteSel > 1.U
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when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
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addrr := addrr + 1.U
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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addrw := 0.U
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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addrw := Cat( exRegi(6,0), shiftMOSI(1) )
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI(1) )
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} .otherwise{ // byteSel > 1.U
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when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
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addrw := addrw + 1.U
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}
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}
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}
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class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
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val qspi = IO(new QSPIInterfaceIO)
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val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
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sck := qspi.sck
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csn := qspi.csn
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qspi.miso := exRego(7, 4)
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qspi.isDirIn := ~isSpiRead
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io.isEnR :=
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(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
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(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
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when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
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spiCmd := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
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spiCmd := shiftMOSI(1).extract(3)
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := ~bitSel
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}
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//输入看SCK上升沿
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when( isSckPosedge & ~shiftCSn(1) ){
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when( bitSel === 0.U ){
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exRegi := Cat( 0.U, shiftMOSI(1) )
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}.otherwise{
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exRegi := Cat( exRegi(3,0), shiftMOSI(1) )
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}
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}
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//输出在SCK XX沿准备数据
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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exRego := 0.U //第一个byte 地址0
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} .elsewhen(
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(if( edge ) {isSckPosedge} else {isSckNegedge})
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& ~shiftCSn(1)
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){
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when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
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when( byteSel === 0.U || byteSel === 1.U || ( if( edge ) { false.B } else { byteSel === 2.U } ) ){
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exRego := 0.U //地址1，cmd
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} .elsewhen( isSpiRead ){
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exRego := io.datar
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}
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}.otherwise{
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exRego := exRego << 4
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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addrr := 0.U
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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addrr := Cat( exRegi(3,0), shiftMOSI(1) )
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
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} .otherwise{ // byteSel > 1.U
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when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
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addrr := addrr + 1.U
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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addrw := 0.U
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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addrw := Cat( exRegi(3,0), shiftMOSI(1) )
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} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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addrw := Cat(addrw(7,0), exRegi(3,0), shiftMOSI(1) )
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} .otherwise{ // byteSel > 1.U
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when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
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addrw := addrw + 1.U
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}
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}
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}
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