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分时复用一个CDR

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This commit is contained in:
RuigeLee
2024-10-31 15:12:32 +08:00
parent 69f3f0e66b
commit 20a52f2506
3 changed files with 38 additions and 46 deletions
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23
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -11,9 +11,10 @@ import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
class TLCDRIO extends Bundle{
val overCLK = Input(Bool())
val datIn = Input(Bool())
val datOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
@@ -21,14 +22,17 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val interrupt = Output(Vec(4, Bool()))
}
val io: TLCDRIO = IO(new TLCDRIO)
val io: TLCDRIO = IO(new TLCDRIO)
val dirSel = RegInit(false.B)
val CDRIn = Module(new CDRIn)
CDRIn.io.serDat := io.datIn
CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn )
CDRIn.io.overCLK := io.overCLK
val CDROut = Module(new CDROut)
io.datOut := CDROut.io.serDat
io.dDatOut := ~dirSel & CDROut.io.serDat
io.uDatOut := dirSel & CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
@@ -192,6 +196,8 @@ trait TLCDRRx{ this: TLCDRBase =>
class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
val isWriteTransDir = io.tla.fire & io.tla.bits.address(6,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W))
val tlAReady = RegInit(true.B)
@@ -199,6 +205,11 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
val isRead = Reg(Bool())
when( isWriteTransDir ){
dirSel := io.tla.bits.data
}
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid