first test

2023-07-28 15:38:46 +08:00
parent 85fe9175e6
commit 2048a4d286
6 changed files with 305 additions and 7 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
      ChiselGeneratorAnnotation(() => {
-    new BackBoardSlv
+    new BackBoardSlvTest
  })
    ))