diff --git a/Makefile b/Makefile index ca8324a..e894771 100644 --- a/Makefile +++ b/Makefile @@ -72,3 +72,28 @@ sw: fst: gtkwave ./tb/build/wave.fst & + + +VSimBack: + rm -rf ./tb/build/ + mkdir -p ./tb/build/ + verilator -Wno-fatal \ + --timescale "1 ns / 1 ps" \ + -y ${PWD}/tb/ \ + -y ${PWD}/generated/ \ + --top-module BackBoardSlvTest \ + --trace-fst \ + --cc ./generated/BackBoardSlvTest.v \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_DELAY=0 \ + --exe --build \ + ${PWD}/tb/sim_backSlv.cpp \ + -Mdir ./tb/build/ \ + -j 30 + + + + diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index cf3deb1..ce3f3c8 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -13,7 +13,7 @@ class BackBoardSlvIO extends Bundle{ val upStreamRespdat = Output(Bool()) val downStreamRespdat = Output(Bool()) - val refClk = Input( Vec(4, Bool()) ) + val clk4 = Input( Bool() ) } @@ -21,14 +21,14 @@ abstract class BackBoardSlvBase extends Module{ val io: BackBoardSlvIO = IO(new BackBoardSlvIO) - val upStreamReq = Module(new CDR4InBus) - val downStreamReq = Module(new CDR4InBus) + val upStreamReq = Module(new CDR4MultiIn) + val downStreamReq = Module(new CDR4MultiIn) val upStreamResp = Module(new CDROutBus) val downStreamResp = Module(new CDROutBus) - upStreamReq.io.refClk := io.refClk - downStreamReq.io.refClk := io.refClk + upStreamReq.io.clk4 := io.clk4 + downStreamReq.io.clk4 := io.clk4 upStreamReq.io.dat := io.upStreamReqDat downStreamReq.io.dat := io.downStreamReqDat @@ -101,5 +101,5 @@ trait StatusControl{ this: BackBoardSlvBase => } -class BackBoardSlv extends BackBoardSlvBase with LocalRegisters +class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters diff --git a/src/main/scala/backBoard/CDR4MultiIn.scala b/src/main/scala/backBoard/CDR4MultiIn.scala new file mode 100644 index 0000000..c0cddf8 --- /dev/null +++ b/src/main/scala/backBoard/CDR4MultiIn.scala @@ -0,0 +1,63 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + + +import freechips.rocketchip.util._ + + + + +class CDR4MultiInIO() extends Bundle{ + val dat = Input(Bool()) + val clk4 = Input(Bool()) + + val latDat = Decoupled(new CDRData) +} + + + +class CDR4MultiIn() extends Module{ + val io: CDR4MultiInIO = IO(new CDR4MultiInIO()) + + val inBusToAsync = Wire( new AsyncBundle(new CDRData) ) + + withClockAndReset( io.clk4.asClock, reset ){ + val latAValid = RegInit(false.B) + val latAInfo = Reg(new CDRData) + val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) ) + val latAReady = Wire(Bool()) + + val transInfo = Wire(new CDRData) + + transInfo := + Cat( + ( 0 until (6+8+32+16) ).map{ i => shiftDat( 4*(i+1) + 1 ) } + ).asTypeOf(new CDRData) + + + when( latAValid & latAReady ){ + shiftDat := 0.U + latAValid := false.B + } .elsewhen( shiftDat.extract(0) =/= 1.U ){ + shiftDat := Cat(io.dat, shiftDat( ((1+6+8+32+16)*4+2)-1, 1) ) + } .elsewhen( shiftDat.extract(0) === 1.U ){ + latAValid := true.B + latAInfo := transInfo + } + + val inBusASyncIO = Wire( new DecoupledIO(new CDRData) ) + inBusASyncIO.valid := latAValid + inBusASyncIO.bits := latAInfo + latAReady := inBusASyncIO.ready + inBusToAsync <> ToAsyncBundle( inBusASyncIO, AsyncQueueParams(sync=2) ) + } + + + io.latDat <> FromAsyncBundle( inBusToAsync, 2 ) + +} + + diff --git a/src/test/scala/gcd/BackPlaneSlvTest.scala b/src/test/scala/gcd/BackPlaneSlvTest.scala new file mode 100644 index 0000000..84849a0 --- /dev/null +++ b/src/test/scala/gcd/BackPlaneSlvTest.scala @@ -0,0 +1,63 @@ + +package BACK + +import chisel3._ +import chisel3.util._ + + + + +class BackBoardSlvTestIO extends Bundle{ + val localHost = Input(UInt(6.W)) + + val upStreamRespdat = Output(Bool()) + val downStreamRespdat = Output(Bool()) + + val clk4 = Input( Bool() ) + + + val req = Flipped(Decoupled(new CDRData)) + val rsp = Flipped(Decoupled(new CDRData)) +} + + +class BackBoardSlvTest extends Module{ + val io: BackBoardSlvTestIO = IO(new BackBoardSlvTestIO) + + val dut = Module( new BackBoardSlv) + + dut.io.localHost := "h12".U + dut.io.clk4 := io.clk4 + + io.upStreamRespdat := dut.io.upStreamRespdat + io.downStreamRespdat := dut.io.downStreamRespdat + + io.req.ready := true.B + io.rsp.ready := true.B + + val reqInfo = RegInit(0.U((new CDRData).getWidth.W)) + val rspInfo = RegInit(0.U((new CDRData).getWidth.W)) + val reqDat = RegInit(false.B); dut.io.upStreamReqDat := reqDat + val rspDat = RegInit(false.B); dut.io.downStreamReqDat := rspDat + + when( io.req.fire ){ + reqInfo := io.req.bits.asUInt + reqDat := true.B + } .otherwise{ + reqDat := reqInfo.extract( 6+8+32+16-1 ) + reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) + } + + when( io.rsp.fire ){ + rspInfo := io.rsp.bits.asUInt + rspDat := true.B + } .otherwise{ + rspDat := rspInfo.extract( 6+8+32+16-1 ) + rspInfo := Cat( rspInfo( 6+8+32+16-2,0 ), 0.U(1.W) ) + } + +} + + + + diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 37ac971..46f0062 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._ object testModule extends App { (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { - new BackBoardSlv + new BackBoardSlvTest }) )) diff --git a/tb/sim_backSlv.cpp b/tb/sim_backSlv.cpp new file mode 100644 index 0000000..da2fa8f --- /dev/null +++ b/tb/sim_backSlv.cpp @@ -0,0 +1,147 @@ +/* + Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +#include +#include "VBackBoardSlvTest.h" +#include +#include +#include + +#include + + + +#if VM_TRACE +#include "verilated_fst_c.h" +#endif + + +char* img; +VBackBoardSlvTest *top; +#if VM_TRACE +VerilatedFstC* tfp; +#endif +vluint64_t main_time = 0; + +double sc_time_stamp () { + return main_time; +} + + + +static void sim_exit(){ +#if VM_TRACE + tfp->close(); +#endif + + top->final(); + + delete top; +} + + + + + + +int main(int argc, char **argv, char **env) { + + + top = new VBackBoardSlvTest(); + +#if VM_TRACE + tfp = new VerilatedFstC; + Verilated::traceEverOn(true); + top->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("./tb/build/wave.fst"); +#endif + + + + + top->reset = 1; + top->clock = 0; + top->io_clk4 = 0; + + while(!Verilated::gotFinish()) { + + Verilated::timeInc(1); + + if ( main_time != 1000 ){ + } else { + top->reset = 0; + } + + if ( main_time % 400 == 100 ) { + top->clock = 1; + } else if ( main_time % 400 == 300 ) { + top->clock = 0; + } + + if ( main_time % 100 == 10 ) { + top->io_clk4 = 1; + } else if ( main_time % 100 == 60 ) { + top->io_clk4 = 0; + } + + + if( main_time == 50000 ){ + top->io_req_valid = 1; + top->io_req_bits_address = 0x12; + top->io_req_bits_register = 0x0; + top->io_req_bits_data = 0xaa; + } else if( main_time == 50400 ){ + top->io_req_valid = 0; + } + + if( main_time == 100000 ){ + top->io_rsp_valid = 1; + top->io_rsp_bits_address = 0x12; + top->io_rsp_bits_register = 0x0; + top->io_rsp_bits_data = 0xaa; + } else if( main_time == 100400 ){ + top->io_rsp_valid = 0; + } + + + top->eval(); +#if VM_TRACE + tfp->dump(Verilated::time()); + +#endif + + + main_time ++; + + if( main_time > 200000 ){ + break; + } + } + + sim_exit(); + return -1; + + +} + + + + + + + +