first test

src/test/scala/gcd/BackPlaneSlvTest.scala

@@ -0,0 +1,63 @@
+
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+
+class BackBoardSlvTestIO extends Bundle{
+  val localHost = Input(UInt(6.W))
+
+  val upStreamRespdat   = Output(Bool())
+  val downStreamRespdat = Output(Bool())
+
+  val clk4            = Input( Bool() )
+
+
+  val req = Flipped(Decoupled(new CDRData))
+  val rsp = Flipped(Decoupled(new CDRData))
+}
+
+
+class BackBoardSlvTest extends Module{
+  val io: BackBoardSlvTestIO = IO(new BackBoardSlvTestIO)
+
+  val dut = Module( new BackBoardSlv)
+
+  dut.io.localHost := "h12".U
+  dut.io.clk4 := io.clk4
+
+  io.upStreamRespdat   := dut.io.upStreamRespdat
+  io.downStreamRespdat := dut.io.downStreamRespdat
+
+  io.req.ready := true.B
+  io.rsp.ready := true.B
+
+  val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
+  val rspInfo = RegInit(0.U((new CDRData).getWidth.W))
+  val reqDat = RegInit(false.B); dut.io.upStreamReqDat := reqDat
+  val rspDat = RegInit(false.B); dut.io.downStreamReqDat := rspDat
+
+  when( io.req.fire ){
+    reqInfo := io.req.bits.asUInt
+    reqDat := true.B
+  } .otherwise{
+    reqDat := reqInfo.extract( 6+8+32+16-1 )
+    reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+  }
+
+  when( io.rsp.fire ){
+    rspInfo := io.rsp.bits.asUInt
+    rspDat := true.B
+  } .otherwise{
+    rspDat := rspInfo.extract( 6+8+32+16-1 )
+    rspInfo := Cat( rspInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+  }
+
+}
+
+
+
+

src/test/scala/gcd/test.scala

@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    new BackBoardSlv
+    new BackBoardSlvTest
   })
     ))