first test

src/main/scala/backBoard/BackBoardSlv.scala

@@ -13,7 +13,7 @@ class BackBoardSlvIO extends Bundle{
   val upStreamRespdat   = Output(Bool())
   val downStreamRespdat = Output(Bool())
 
-  val refClk            = Input( Vec(4, Bool()) )
+  val clk4            = Input( Bool() )
 }
 
 
@@ -21,14 +21,14 @@ abstract class BackBoardSlvBase extends Module{
   val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
 
 
-  val upStreamReq    = Module(new CDR4InBus)
-  val downStreamReq  = Module(new CDR4InBus)
+  val upStreamReq    = Module(new CDR4MultiIn)
+  val downStreamReq  = Module(new CDR4MultiIn)
 
   val upStreamResp   = Module(new CDROutBus)
   val downStreamResp = Module(new CDROutBus)
 
-  upStreamReq.io.refClk   := io.refClk
-  downStreamReq.io.refClk := io.refClk
+  upStreamReq.io.clk4   := io.clk4
+  downStreamReq.io.clk4 := io.clk4
   upStreamReq.io.dat      := io.upStreamReqDat
   downStreamReq.io.dat    := io.downStreamReqDat
 
@@ -101,5 +101,5 @@ trait StatusControl{ this: BackBoardSlvBase =>
 }
 
 
-class BackBoardSlv extends BackBoardSlvBase with LocalRegisters
+class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters