first test

src/main/scala/backBoard/BackBoardSlv.scala

@@ -13,7 +13,7 @@ class BackBoardSlvIO extends Bundle{
   val upStreamRespdat   = Output(Bool())
   val downStreamRespdat = Output(Bool())
 
-  val refClk            = Input( Vec(4, Bool()) )
+  val clk4            = Input( Bool() )
 }
 
 
@@ -21,14 +21,14 @@ abstract class BackBoardSlvBase extends Module{
   val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
 
 
-  val upStreamReq    = Module(new CDR4InBus)
-  val downStreamReq  = Module(new CDR4InBus)
+  val upStreamReq    = Module(new CDR4MultiIn)
+  val downStreamReq  = Module(new CDR4MultiIn)
 
   val upStreamResp   = Module(new CDROutBus)
   val downStreamResp = Module(new CDROutBus)
 
-  upStreamReq.io.refClk   := io.refClk
-  downStreamReq.io.refClk := io.refClk
+  upStreamReq.io.clk4   := io.clk4
+  downStreamReq.io.clk4 := io.clk4
   upStreamReq.io.dat      := io.upStreamReqDat
   downStreamReq.io.dat    := io.downStreamReqDat
 
@@ -101,5 +101,5 @@ trait StatusControl{ this: BackBoardSlvBase =>
 }
 
 
-class BackBoardSlv extends BackBoardSlvBase with LocalRegisters
+class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters
 

src/main/scala/backBoard/CDR4MultiIn.scala

@@ -0,0 +1,63 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+import freechips.rocketchip.util._
+
+
+
+
+class CDR4MultiInIO() extends Bundle{
+  val dat = Input(Bool())
+  val clk4 = Input(Bool())
+
+  val latDat = Decoupled(new CDRData)
+}
+
+
+
+class CDR4MultiIn() extends Module{
+  val io: CDR4MultiInIO = IO(new CDR4MultiInIO())
+
+  val inBusToAsync = Wire( new AsyncBundle(new CDRData) )
+
+  withClockAndReset( io.clk4.asClock, reset ){
+    val latAValid = RegInit(false.B)
+    val latAInfo = Reg(new CDRData)
+    val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) )
+    val latAReady = Wire(Bool())
+
+    val transInfo = Wire(new CDRData)
+
+    transInfo := 
+      Cat(
+        ( 0 until (6+8+32+16) ).map{ i => shiftDat( 4*(i+1) + 1 ) }
+      ).asTypeOf(new CDRData)
+
+
+    when( latAValid & latAReady ){
+      shiftDat := 0.U
+      latAValid := false.B
+    } .elsewhen( shiftDat.extract(0) =/= 1.U ){
+      shiftDat := Cat(io.dat, shiftDat( ((1+6+8+32+16)*4+2)-1, 1) ) 
+    } .elsewhen( shiftDat.extract(0) === 1.U ){
+      latAValid := true.B
+      latAInfo  := transInfo
+    }
+
+    val inBusASyncIO  = Wire( new DecoupledIO(new CDRData) )
+    inBusASyncIO.valid := latAValid
+    inBusASyncIO.bits  := latAInfo
+    latAReady := inBusASyncIO.ready
+    inBusToAsync <> ToAsyncBundle( inBusASyncIO, AsyncQueueParams(sync=2) )
+  }
+
+
+    io.latDat <> FromAsyncBundle( inBusToAsync, 2 )
+
+}
+
+

src/test/scala/gcd/BackPlaneSlvTest.scala

@@ -0,0 +1,63 @@
+
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+
+class BackBoardSlvTestIO extends Bundle{
+  val localHost = Input(UInt(6.W))
+
+  val upStreamRespdat   = Output(Bool())
+  val downStreamRespdat = Output(Bool())
+
+  val clk4            = Input( Bool() )
+
+
+  val req = Flipped(Decoupled(new CDRData))
+  val rsp = Flipped(Decoupled(new CDRData))
+}
+
+
+class BackBoardSlvTest extends Module{
+  val io: BackBoardSlvTestIO = IO(new BackBoardSlvTestIO)
+
+  val dut = Module( new BackBoardSlv)
+
+  dut.io.localHost := "h12".U
+  dut.io.clk4 := io.clk4
+
+  io.upStreamRespdat   := dut.io.upStreamRespdat
+  io.downStreamRespdat := dut.io.downStreamRespdat
+
+  io.req.ready := true.B
+  io.rsp.ready := true.B
+
+  val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
+  val rspInfo = RegInit(0.U((new CDRData).getWidth.W))
+  val reqDat = RegInit(false.B); dut.io.upStreamReqDat := reqDat
+  val rspDat = RegInit(false.B); dut.io.downStreamReqDat := rspDat
+
+  when( io.req.fire ){
+    reqInfo := io.req.bits.asUInt
+    reqDat := true.B
+  } .otherwise{
+    reqDat := reqInfo.extract( 6+8+32+16-1 )
+    reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+  }
+
+  when( io.rsp.fire ){
+    rspInfo := io.rsp.bits.asUInt
+    rspDat := true.B
+  } .otherwise{
+    rspDat := rspInfo.extract( 6+8+32+16-1 )
+    rspInfo := Cat( rspInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+  }
+
+}
+
+
+
+

src/test/scala/gcd/test.scala

@@ -14,7 +14,7 @@ import org.chipsalliance.cde.config._
 object testModule extends App {
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    new BackBoardSlv
+    new BackBoardSlvTest
   })
     ))