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RuigeLee
2025-09-17 11:07:34 +08:00
parent 21ffc1b58d
commit 1e2fa0931d
3 changed files with 51 additions and 51 deletions
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9
src/main/scala/backBoard/shin/Interface.scala
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@@ -154,6 +154,7 @@ class InterfaceIO extends Bundle{
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val iqspi = new QSPIInterfaceIO
val aqspi = new QSPIInterfaceIO
val lvds = Flipped(new RegAccessInterfaceIO)
@@ -223,10 +224,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
val oSpi = Module(new SSpiInterface)
val oQSpi = Module(new QSpiInterface)
val iQSpi = Module(new QSpiInterface)
val aQSpi = Module(new SyncQSpiInterface)
io.ospi <> oSpi.spi
io.oqspi <> oQSpi.qspi
io.iqspi <> iQSpi.qspi
io.aqspi <> aQSpi.qspi
val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
@@ -557,30 +560,35 @@ trait InterfaceMCUop{ this: InterfaceBase =>
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnW,
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
( cReg.spiSel === 3.U ) -> aQSpi.io.isEnW,
))
addrr := Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.addrr,
( cReg.spiSel === 1.U ) -> oSpi.io.addrr,
( cReg.spiSel === 2.U ) -> oQSpi.io.addrr,
( cReg.spiSel === 3.U ) -> aQSpi.io.addrr,
))
addrw := Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.addrw,
( cReg.spiSel === 1.U ) -> oSpi.io.addrw,
( cReg.spiSel === 2.U ) -> oQSpi.io.addrw,
( cReg.spiSel === 3.U ) -> aQSpi.io.addrw,
))
dataw := Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
( cReg.spiSel === 1.U ) -> oSpi.io.dataw,
( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
( cReg.spiSel === 3.U ) -> aQSpi.io.dataw,
))
isEnR := Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnR,
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
( cReg.spiSel === 3.U ) -> aQSpi.io.isEnR,
))
datar := MuxCase( 0.U, Array(
@@ -598,6 +606,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
aQSpi.io.datar := Mux(cReg.spiSel === 3.U, datar, 0.U)
// when( isEnW ){
// printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw)