Merge branch 'mp_eb_dev' into feature/syncSpi
# Conflicts: # src/main/scala/backBoard/shin/SpiInterface.scala
This commit is contained in:
RuigeLee
@@ -52,6 +52,10 @@ class CommonRegisterBundle extends Bundle{
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val refTop = UInt(3.W)
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val bias = UInt(2.W)
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val dwupEx = Bool()
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val b8b4Sel = Bool()
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val cdrParam = UInt(8.W)
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val softResetCode = Vec(4, UInt(8.W))
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@@ -95,10 +99,6 @@ class CommonRegisterBundle extends Bundle{
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val syncPeroid = UInt(32.W)
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val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
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val localPeroid = UInt(32.W)
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val localPoint = UInt(64.W)
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val custom = Vec( 128, UInt(8.W) )
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val smUsedDepth = Vec(8, UInt(8.W))
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@@ -122,6 +122,7 @@ class MasterRegisterBundle extends Bundle{
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val isRecCRCErr = UInt(4.W)
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val rplTimeStampTx = UInt(16.W)
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val timeStampOffset = UInt(64.W)
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}
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@@ -140,7 +141,8 @@ class SlaveRegisterBundle extends Bundle{
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val slvDeltaTime = UInt(32.W) //从站时间戳差值
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val deltaFinal = UInt(64.W) //当前时间戳与主站时间差
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val lvdsWriteAble = UInt(16.W)
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def isLVDSWriteAble = lvdsWriteAble(15,8) === "h58".U & lvdsWriteAble.extract(0)
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}
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@@ -264,6 +266,7 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
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Seq(
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(addr === "h18".U ) -> sReg.lvdsWriteAble.extract(0),
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(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
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(addr === "h22".U & isMstMode) -> mReg.isRecCRCErr,
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//(addr === "h21".U & isMstMode) -> mReg.txLength,
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@@ -296,6 +299,10 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
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}) ++
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Seq(
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(addr === "h4a".U ) -> cReg.dwupEx,
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(addr === "h4c".U ) -> cReg.b8b4Sel,
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(addr === "h4e".U ) -> cReg.cdrParam,
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(addr === "h50".U ) -> cReg.anamuxSel,
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(addr === "h51".U ) -> cReg.ldo2p5,
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(addr === "h52".U ) -> cReg.ldo1p1,
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@@ -380,13 +387,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
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Seq(
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//本地时钟
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(addr === "h100".U ) -> cReg.timeStamp(7,0),
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(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)),
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(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
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(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
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(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
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(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
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(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
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(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
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(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h100".U)),
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(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h100".U)),
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//参考主站时钟
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(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
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@@ -412,13 +419,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
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//校准后的时钟
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(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
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(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)),
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(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
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(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
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(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
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(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
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(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
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(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
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(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h118".U)),
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(addr === "h120".U ) -> cReg.syncCfg,
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@@ -463,19 +470,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
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(addr === "h146".U ) -> cReg.syncOffset(3)(23,16),
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(addr === "h147".U ) -> cReg.syncOffset(3)(31,24),
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(addr === "h148".U ) -> cReg.localPoint(7,0),
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(addr === "h149".U ) -> cReg.localPoint(15,8),
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(addr === "h14a".U ) -> cReg.localPoint(23,16),
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(addr === "h14b".U ) -> cReg.localPoint(31,24),
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(addr === "h14c".U ) -> cReg.localPoint(39,32),
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(addr === "h14d".U ) -> cReg.localPoint(47,40),
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(addr === "h14e".U ) -> cReg.localPoint(55,48),
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(addr === "h14f".U ) -> cReg.localPoint(63,56),
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(addr === "h150".U ) -> cReg.localPeroid(7,0),
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(addr === "h151".U ) -> cReg.localPeroid(15,8),
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(addr === "h152".U ) -> cReg.localPeroid(23,16),
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(addr === "h153".U ) -> cReg.localPeroid(31,24),
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(addr === "h148".U ) -> mReg.timeStampOffset(7,0),
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(addr === "h149".U ) -> mReg.timeStampOffset(15,8),
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(addr === "h14a".U ) -> mReg.timeStampOffset(23,16),
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(addr === "h14b".U ) -> mReg.timeStampOffset(31,24),
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(addr === "h14c".U ) -> mReg.timeStampOffset(39,32),
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(addr === "h14d".U ) -> mReg.timeStampOffset(47,40),
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(addr === "h14e".U ) -> mReg.timeStampOffset(55,48),
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(addr === "h14f".U ) -> mReg.timeStampOffset(63,56),
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) ++
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( 0 until 128 ).map{ i =>
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@@ -604,7 +606,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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))
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datar := MuxCase( 0.U, Array(
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((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
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((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), 0.U(8.W), isEnR ),
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((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
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((addrr & "hF800".U) === "h1000".U) -> 0.U,
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((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
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@@ -736,34 +738,35 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
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io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U)
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}
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trait InterfaceLVDSop{ this: InterfaceBase =>
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trait InterfaceEBMMU{ this: InterfaceBase =>
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io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
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io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
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( 0 until 16 ).map{ i =>
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sReg.ebmmu(i).lAddr := Cat(
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RegEnable( io.lvds.dataw(5,0), 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).pAddr := Cat(
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).length := Cat(
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).op :=
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RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
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RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
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sReg.ebmmu(i).isEnable :=
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RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
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RegEnable( io.lvds.dataw.extract(0), false.B, sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
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}
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}
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@@ -777,10 +780,11 @@ trait InterfaceSync{ this: InterfaceBase =>
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cReg.syncWidth(i) := syncWidth(i)
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}
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val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
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val timeStampOffset = RegInit(0.U(64.W)); mReg.timeStampOffset := timeStampOffset
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val timeStampOffset_WRCopy = RegInit(0.U(64.W))
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val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint
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val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W))
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val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
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val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint
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val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid
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val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
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for( i <- 0 until 4 ) {
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@@ -793,29 +797,30 @@ trait InterfaceSync{ this: InterfaceBase =>
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}
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for( i <- 0 until 4 ){
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when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
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syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
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} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
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syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
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when( addrw === ("h122".U(16.W) + (2*i).U)){
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syncWidth(i) := Cat( syncWidth(i)(15,8), dataw )
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} .elsewhen( addrw === ("h123".U(16.W) + (2*i).U) ){
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syncWidth(i) := Cat( dataw, syncWidth(i)(7,0) )
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}
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}
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when( addrw === "h130".U ){
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syncPoint := Cat( syncPoint(63,8), dataw )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), dataw )
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} .elsewhen( addrw === "h131".U ){
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syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), dataw, syncPoint_WRCopy(7,0) )
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} .elsewhen( addrw === "h132".U ){
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syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), dataw, syncPoint_WRCopy(15,0) )
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} .elsewhen( addrw === "h133".U ){
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syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), dataw, syncPoint_WRCopy(23,0) )
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} .elsewhen( addrw === "h134".U ){
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syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), dataw, syncPoint_WRCopy(31,0) )
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} .elsewhen( addrw === "h135".U ){
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syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), dataw, syncPoint_WRCopy(39,0) )
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} .elsewhen( addrw === "h136".U ){
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syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
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syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), dataw, syncPoint_WRCopy(47,0) )
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} .elsewhen( addrw === "h137".U ){
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syncPoint := Cat( dataw, syncPoint(55,0) )
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syncPoint_WRCopy := Cat( dataw, syncPoint_WRCopy(55,0) )
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||||
syncPoint := Cat( dataw, syncPoint_WRCopy(55,0) )
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||||
}
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||||
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||||
.elsewhen( addrw === "h138".U ){
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||||
@@ -829,34 +834,24 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
}
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||||
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||||
.elsewhen( addrw === "h148".U ){
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localPoint := Cat( localPoint(63,8), dataw )
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timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,8), dataw )
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||||
} .elsewhen( addrw === "h149".U ){
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localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) )
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timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,16), dataw, timeStampOffset_WRCopy(7,0) )
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} .elsewhen( addrw === "h14a".U ){
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localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) )
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timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,24), dataw, timeStampOffset_WRCopy(15,0) )
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} .elsewhen( addrw === "h14b".U ){
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localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) )
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||||
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,32), dataw, timeStampOffset_WRCopy(23,0) )
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} .elsewhen( addrw === "h14c".U ){
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localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) )
|
||||
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,40), dataw, timeStampOffset_WRCopy(31,0) )
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||||
} .elsewhen( addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) )
|
||||
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,48), dataw, timeStampOffset_WRCopy(39,0) )
|
||||
} .elsewhen( addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) )
|
||||
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,56), dataw, timeStampOffset_WRCopy(47,0) )
|
||||
} .elsewhen( addrw === "h14f".U ){
|
||||
localPoint := Cat( dataw, localPoint(55,0) )
|
||||
timeStampOffset_WRCopy := Cat( dataw, timeStampOffset_WRCopy(55,0) )
|
||||
timeStampOffset := Cat( dataw, timeStampOffset_WRCopy(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h153".U ){
|
||||
localPeroid := Cat( dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
@@ -872,7 +867,6 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
}
|
||||
|
||||
|
||||
|
||||
when( io.lvds.isEnW ){
|
||||
|
||||
when( io.lvds.addrw === "h120".U ){
|
||||
@@ -888,21 +882,22 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h130".U ){
|
||||
syncPoint := Cat( syncPoint(63,8), io.lvds.dataw )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h131".U ){
|
||||
syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), io.lvds.dataw, syncPoint_WRCopy(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h132".U ){
|
||||
syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), io.lvds.dataw, syncPoint_WRCopy(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h133".U ){
|
||||
syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), io.lvds.dataw, syncPoint_WRCopy(23,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h134".U ){
|
||||
syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), io.lvds.dataw, syncPoint_WRCopy(31,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h135".U ){
|
||||
syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), io.lvds.dataw, syncPoint_WRCopy(39,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h136".U ){
|
||||
syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) )
|
||||
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), io.lvds.dataw, syncPoint_WRCopy(47,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h137".U ){
|
||||
syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) )
|
||||
syncPoint_WRCopy := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
|
||||
syncPoint := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h138".U ){
|
||||
@@ -915,35 +910,6 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h148".U ){
|
||||
localPoint := Cat( localPoint(63,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h149".U ){
|
||||
localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14a".U ){
|
||||
localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14b".U ){
|
||||
localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14c".U ){
|
||||
localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14f".U ){
|
||||
localPoint := Cat( io.lvds.dataw, localPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h153".U ){
|
||||
localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
|
||||
@@ -957,14 +923,14 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
}
|
||||
}
|
||||
|
||||
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
|
||||
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 1.U(64.W) )
|
||||
cReg.mstDeltaTime := io.mstDeltaTime
|
||||
|
||||
|
||||
sReg.deltaFinal := io.deltaFinal
|
||||
cReg.recoTimeStamp :=
|
||||
Mux(isMstMode, cReg.timeStamp,
|
||||
RegNext( cReg.timeStamp + sReg.deltaFinal )
|
||||
Mux(isMstMode, cReg.timeStamp + mReg.timeStampOffset,
|
||||
RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) )
|
||||
)
|
||||
sReg.slvDeltaTime := io.slvDeltaTime
|
||||
|
||||
@@ -972,19 +938,40 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
|
||||
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
|
||||
|
||||
val recoTimeStamp_Copy = RegInit(1.U(64.W))
|
||||
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
|
||||
when(
|
||||
cReg.syncPoint === recoTimeStamp_Copy ||
|
||||
(io.lvds.addrw === "h120".U & io.lvds.isEnW) || //写syncCfg
|
||||
(io.lvds.addrw === "h137".U & io.lvds.isEnW) || //写syncPoint
|
||||
(io.lvds.addrw === "h13B".U & io.lvds.isEnW) || //写syncPeroid
|
||||
(addrw === "h120".U & isEnW) || //写syncCfg
|
||||
(addrw === "h137".U & isEnW) || //写syncPoint
|
||||
(addrw === "h13B".U & isEnW) //写syncPeroid
|
||||
){
|
||||
recoTimeStamp_Copy := cReg.timeStamp + sReg.deltaFinal
|
||||
} .otherwise{
|
||||
recoTimeStamp_Copy := recoTimeStamp_Copy + 1.U
|
||||
}
|
||||
|
||||
|
||||
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
|
||||
syncSign(0) := true.B
|
||||
syncPoint := syncPoint + cReg.syncPeroid
|
||||
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
|
||||
syncSign(0) := false.B
|
||||
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||||
syncSign(0) := false.B
|
||||
}
|
||||
|
||||
when( cReg.syncPoint <= recoTimeStamp_Copy ){
|
||||
syncPoint := syncPoint + cReg.syncPeroid
|
||||
}
|
||||
|
||||
|
||||
for( i <- 1 until 4 ) {
|
||||
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
|
||||
syncOffsetCnt(i) := 0.U
|
||||
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
|
||||
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
|
||||
@@ -1018,13 +1005,6 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)
|
||||
|
||||
|
||||
val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp
|
||||
|
||||
when( isLocalSyncInt ){ //时间到达localSync时间点
|
||||
localPoint := cReg.localPoint + cReg.localPeroid
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceWdt{ this: InterfaceBase =>
|
||||
@@ -1082,6 +1062,30 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
|
||||
|
||||
|
||||
val dwupExTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
|
||||
cReg.dwupEx := RegEnable(dwupExTemp, 0.U(8.W), isEnW & addrw === "h4b".U & dataw === "h58".U )
|
||||
|
||||
val b8b4SelTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
|
||||
cReg.b8b4Sel := RegEnable(b8b4SelTemp, 0.U(8.W), isEnW & addrw === "h4d".U & dataw === "h59".U )
|
||||
|
||||
val cdrParamTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
|
||||
cReg.cdrParam := RegEnable(cdrParamTemp, 0.U(8.W), isEnW & addrw === "h4f".U & dataw === "h60".U )
|
||||
|
||||
val lvdsWriteAble = RegInit(0.U(16.W)); sReg.lvdsWriteAble := lvdsWriteAble
|
||||
when( io.lvds.isEnW & (io.lvds.addrw === "h19".U(16.W)) ){
|
||||
lvdsWriteAble := Cat( io.lvds.dataw, lvdsWriteAble(7,0) )
|
||||
} .elsewhen( isEnW & (addrw === "h19".U(16.W)) ){
|
||||
lvdsWriteAble := Cat( dataw, lvdsWriteAble(7,0) )
|
||||
} .elsewhen( io.lvds.isEnW & (io.lvds.addrw === "h18".U(16.W)) ){
|
||||
lvdsWriteAble := Cat( lvdsWriteAble(15,8), io.lvds.dataw )
|
||||
} .elsewhen( isEnW & (addrw === "h18".U(16.W)) ){
|
||||
lvdsWriteAble := Cat( lvdsWriteAble(15,8), dataw )
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceInterrupt{ this: InterfaceBase =>
|
||||
cReg.intEnable :=
|
||||
Cat(
|
||||
1.U(1.W), //复位中断，时钟为1 //31 上电复位
|
||||
@@ -1119,16 +1123,11 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
intStatus(1) := true.B
|
||||
}
|
||||
|
||||
//主站发送周期到了
|
||||
val isLocalSyncInt: Bool
|
||||
when( isLocalSyncInt ){
|
||||
intStatus(2) := true.B
|
||||
}
|
||||
|
||||
//外部latch中断
|
||||
val isLatchEvent =
|
||||
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
|
||||
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
|
||||
(RegNext( cReg.event.latchStatus(0), false.B ) =/= cReg.event.latchStatus(0)) |
|
||||
(RegNext( cReg.event.latchStatus(1), false.B ) =/= cReg.event.latchStatus(1))
|
||||
|
||||
when(isLatchEvent){
|
||||
intStatus(3) := true.B
|
||||
@@ -1165,12 +1164,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
intStatus(19) := true.B
|
||||
}
|
||||
|
||||
|
||||
val intHWErr = Seq(
|
||||
( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
|
||||
( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
|
||||
)
|
||||
//下行接收硬件错误
|
||||
when( io.intHWTrig(0) ){
|
||||
when( intHWErr(0) ){
|
||||
intStatus(29) := true.B
|
||||
}
|
||||
//上行接收硬件错误
|
||||
when( io.intHWTrig(1) ){
|
||||
when( intHWErr(1) ){
|
||||
intStatus(30) := true.B
|
||||
}
|
||||
|
||||
@@ -1200,33 +1204,29 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
val trigIntPulse =
|
||||
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
|
||||
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
|
||||
(isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了
|
||||
(isLatchEvent & cReg.intEnable(3)) | //latch Event
|
||||
(isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
|
||||
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
|
||||
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
|
||||
isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
|
||||
io.intHWTrig(0) | //下行接收硬件错误
|
||||
io.intHWTrig(1) //上行接收硬件错误
|
||||
intHWErr(0) | //下行接收硬件错误
|
||||
intHWErr(1) //上行接收硬件错误
|
||||
|
||||
when( intPulseResetCnt === intPulseWidth ){
|
||||
intPulse := false.B
|
||||
} .elsewhen( trigIntPulse ){
|
||||
when( trigIntPulse ){
|
||||
intPulse := true.B
|
||||
}
|
||||
} .elsewhen( intPulseResetCnt === intPulseWidth ){
|
||||
intPulse := false.B
|
||||
}
|
||||
|
||||
when( trigIntPulse ){
|
||||
intPulseResetCnt := 0.U
|
||||
} .elsewhen( (intPulseResetCnt < intPulseWidth) & (intPulse === true.B) ){
|
||||
} .elsewhen( (intPulseResetCnt <= intPulseWidth) & (intPulse === true.B) ){
|
||||
intPulseResetCnt := intPulseResetCnt + 1.U
|
||||
}
|
||||
|
||||
io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait InterfaceEvent{ this: InterfaceBase =>
|
||||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
@@ -1453,11 +1453,12 @@ trait InterfaceStat{ this: InterfaceBase =>
|
||||
class Interface extends InterfaceBase
|
||||
with InterfaceMCUop
|
||||
with InterfaceCheckSM
|
||||
with InterfaceLVDSop
|
||||
with InterfaceEBMMU
|
||||
with InterfaceSync
|
||||
with InterfaceStat
|
||||
with InterfaceWdt
|
||||
with InterfaceSystem
|
||||
with InterfaceInterrupt
|
||||
with InterfaceEvent
|
||||
with InterfaceAnalog
|
||||
{
|
||||
@@ -1476,9 +1477,6 @@ with InterfaceAnalog
|
||||
|
||||
sReg.localDevIndex := io.localDevIndex
|
||||
|
||||
// sReg.isDevOnLeft := io.isDevOnLeft
|
||||
// sReg.isDevOnLeftModify := io.isDevOnLeftModify
|
||||
// sReg.indexOfLeftDev := io.indexOfLeftDev
|
||||
sReg.isDevOnRight := io.isDevOnRight
|
||||
sReg.isDevOnRightModify := io.isDevOnRightModify
|
||||
sReg.indexOfRightDev := io.indexOfRightDev
|
||||
|
||||
@@ -30,13 +30,12 @@ class MasterParserIO extends Bundle{
|
||||
abstract class MasterParserBase extends Module with RequireAsyncReset{
|
||||
val io: MasterParserIO = IO(new MasterParserIO)
|
||||
|
||||
val txCnt = Reg(UInt(12.W))
|
||||
val txLen = Reg(UInt(11.W))
|
||||
val txAddr = Reg(UInt(15.W))
|
||||
|
||||
val rxCnt = Reg(UInt(12.W))
|
||||
val rxLen = Reg(UInt(11.W))
|
||||
val rxAddr = Reg(UInt(15.W))
|
||||
val txCnt = RegInit(0.U(12.W))
|
||||
val txLen = RegInit(0.U(11.W))
|
||||
val txAddr = RegInit(0.U(15.W))
|
||||
val rxCnt = RegInit(0.U(12.W))
|
||||
val rxLen = RegInit(0.U(11.W))
|
||||
val rxAddr = RegInit(0.U(15.W))
|
||||
|
||||
val reqReady = RegInit(true.B)
|
||||
|
||||
@@ -114,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
|
||||
io.downOut.bits.tdata := Mux1H(Seq(
|
||||
( txCnt < txLen ) ->
|
||||
MuxCase( io.sram_r.datar, Array(
|
||||
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
|
||||
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
|
||||
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
|
||||
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
|
||||
@@ -137,7 +136,7 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
|
||||
|
||||
|
||||
|
||||
val recCrcCheck = Reg(UInt(32.W))
|
||||
val recCrcCheck = RegInit(0.U(32.W))
|
||||
|
||||
when( io.req ){
|
||||
rxCnt := 0.U
|
||||
@@ -205,12 +204,12 @@ trait MasterParserStat{ this: MasterParserBase =>
|
||||
|
||||
class MasterParser extends MasterParserBase
|
||||
with MasterParserStat{
|
||||
val deltaTimeStamp = Reg(UInt(32.W))
|
||||
val deltaTimeStamp = RegInit(0.U(32.W))
|
||||
// dontTouch(deltaTimeStamp)
|
||||
io.deltaTimeStamp := deltaTimeStamp
|
||||
|
||||
val txStamps = Reg(UInt(32.W))
|
||||
val pkgChkCnt = Reg(UInt(4.W))
|
||||
val txStamps = RegInit(0.U(32.W))
|
||||
val pkgChkCnt = RegInit(0.U(4.W))
|
||||
|
||||
when( io.upIn.fire & io.upIn.bits.tlast ){
|
||||
pkgChkCnt := 0.U
|
||||
|
||||
@@ -38,12 +38,8 @@ class TopBase_IO_Bundle extends Bundle{
|
||||
|
||||
|
||||
class MstSlvSwitchIO extends TopBase_IO_Bundle{
|
||||
|
||||
val downCDROut = Flipped(new CDROutIO)
|
||||
val upCDROut = Flipped(new CDROutIO)
|
||||
val downCDRIn = Flipped(new CDRInIO)
|
||||
val upCDRIn = Flipped(new CDRInIO)
|
||||
|
||||
val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
|
||||
val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
|
||||
}
|
||||
|
||||
|
||||
@@ -55,24 +51,45 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
|
||||
|
||||
val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO)
|
||||
|
||||
val downCDROut = Module(new CDROut)
|
||||
val upCDROut = Module(new CDROut)
|
||||
|
||||
val downCDRInAxis = Module(new CDRInAxis)
|
||||
val upCDRInAxis = Module(new CDRInAxis)
|
||||
|
||||
val slaveParser = Module(new SlaveParser )
|
||||
val masterParser = Module(new MasterParser)
|
||||
|
||||
val b4b5DownEncoder = Module(new b4b5DualEncode)
|
||||
val b4b5DownDecoder = Module(new b4b5DualDecode)
|
||||
val b4b5UpEncoder = Module(new b4b5DualEncode)
|
||||
val b4b5UpDecoder = Module(new b4b5DualDecode)
|
||||
|
||||
|
||||
|
||||
|
||||
val b8b10DownEncoder = Module(new b8b10Encode)
|
||||
val b8b10DownDecoder = Module(new b8b10Decode)
|
||||
val b8b10UpEncoder = Module(new b8b10Encode)
|
||||
val b8b10UpDecoder = Module(new b8b10Decode)
|
||||
|
||||
val interface = Module(new Interface)
|
||||
|
||||
val downInSerDat = Wire(Bool())
|
||||
val downInSyncSerDat = Wire(Bool()); downCDRInAxis.io.syncSerDat := downInSyncSerDat
|
||||
val upInSerDat = Wire(Bool())
|
||||
val upInSyncSerDat = Wire(Bool()); upCDRInAxis.io.syncSerDat := upInSyncSerDat
|
||||
|
||||
dontTouch(downInSerDat)
|
||||
dontTouch(downInSyncSerDat)
|
||||
dontTouch(upInSerDat)
|
||||
dontTouch(upInSyncSerDat)
|
||||
|
||||
interface.io.latchPin := io.latchPin
|
||||
interface.io.uniCode := io.uniCode
|
||||
interface.io.hwSerial := io.hwSerial
|
||||
|
||||
interface.io.intTransEnd(0) := io.downCDRIn.axis.fire & io.downCDRIn.axis.bits.tlast
|
||||
interface.io.intTransEnd(1) := io.downCDROut.axis.fire & io.downCDROut.axis.bits.tlast
|
||||
interface.io.intTransEnd(2) := io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast
|
||||
interface.io.intTransEnd(3) := io.upCDROut.axis.fire & io.upCDROut.axis.bits.tlast
|
||||
interface.io.intTransEnd(0) := downCDRInAxis.io.axis.fire & downCDRInAxis.io.axis.bits.tlast
|
||||
interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast
|
||||
interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast
|
||||
interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast
|
||||
|
||||
io.isSoftReset := interface.io.isSoftReset
|
||||
io.interrupt := interface.io.interrupt
|
||||
@@ -120,13 +137,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
|
||||
|
||||
val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
|
||||
val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
|
||||
|
||||
val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B)
|
||||
val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B)
|
||||
|
||||
smUnit(0).io.enq := lvdsSMEnq(0)
|
||||
smUnit(2).io.enq := lvdsSMEnq(1)
|
||||
smUnit(4).io.enq := lvdsSMEnq(2)
|
||||
smUnit(6).io.enq := lvdsSMEnq(3)
|
||||
|
||||
smUnit(0).io.isComf := lvdsSMComf(0)
|
||||
smUnit(2).io.isComf := lvdsSMComf(1)
|
||||
smUnit(4).io.isComf := lvdsSMComf(2)
|
||||
smUnit(6).io.isComf := lvdsSMComf(3)
|
||||
|
||||
smUnit(0).io.isAbrt := lvdsSMAbrt(0)
|
||||
smUnit(2).io.isAbrt := lvdsSMAbrt(1)
|
||||
smUnit(4).io.isAbrt := lvdsSMAbrt(2)
|
||||
smUnit(6).io.isAbrt := lvdsSMAbrt(3)
|
||||
|
||||
smUnit(1).io.deq := lvdsSMDeq(0)
|
||||
smUnit(3).io.deq := lvdsSMDeq(1)
|
||||
smUnit(5).io.deq := lvdsSMDeq(2)
|
||||
@@ -153,6 +181,16 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
|
||||
smUnit(5).io.enq := interface.io.uSMenq(2)
|
||||
smUnit(7).io.enq := interface.io.uSMenq(3)
|
||||
|
||||
smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B )
|
||||
smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B )
|
||||
smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B )
|
||||
smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B )
|
||||
|
||||
smUnit(1).io.isAbrt := false.B
|
||||
smUnit(3).io.isAbrt := false.B
|
||||
smUnit(5).io.isAbrt := false.B
|
||||
smUnit(7).io.isAbrt := false.B
|
||||
|
||||
for( i <- 0 until 8 ){
|
||||
interface.io.smUsedDepth(i) := smUnit(i).io.cnt
|
||||
smUnit(i).io.flush := interface.io.isSMReset(i)
|
||||
@@ -212,24 +250,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
|
||||
slaveParser.io.sram_r(3).datar := 0.U
|
||||
masterParser.io.sram_r.datar := 0.U
|
||||
|
||||
io.downCDRIn.axis.ready := false.B
|
||||
downCDRInAxis.io.axis.ready := false.B
|
||||
slaveParser.io.downIn.valid := false.B
|
||||
slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
|
||||
slaveParser.io.downOut.ready := false.B
|
||||
masterParser.io.downOut.ready := false.B
|
||||
io.downCDROut.axis.valid := false.B
|
||||
io.downCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
downCDROut.io.axis.valid := false.B
|
||||
downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
|
||||
io.upCDRIn.axis.ready := false.B
|
||||
upCDRInAxis.io.axis.ready := false.B
|
||||
slaveParser.io.upIn.valid := false.B
|
||||
slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
masterParser.io.upIn.valid := false.B
|
||||
masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
|
||||
slaveParser.io.upOut.ready := false.B
|
||||
io.upCDROut.axis.valid := false.B
|
||||
io.upCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
upCDROut.io.axis.valid := false.B
|
||||
upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
|
||||
|
||||
interface.io.mstDeltaTime := 0.U
|
||||
|
||||
@@ -257,28 +295,35 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
|
||||
|
||||
when( interface.io.cReg.modeSel === true.B ){
|
||||
masterParser.io.downOut <> io.downCDROut.axis
|
||||
masterParser.io.upIn <> io.upCDRIn.axis
|
||||
masterParser.io.downOut <> downCDROut.io.axis
|
||||
masterParser.io.upIn <> upCDRInAxis.io.axis
|
||||
}
|
||||
|
||||
when( interface.io.cReg.modeSel === true.B ){
|
||||
|
||||
when( interface.io.txReq.bits.rxSM === 0.U ){
|
||||
smUnit(0).io.sram_w := masterParser.io.sram_w
|
||||
lvdsSMEnq(0) := masterParser.io.rxEnq
|
||||
lvdsSMEnq(0) := masterParser.io.rxEnq
|
||||
lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B)
|
||||
lvdsSMAbrt(0) := false.B
|
||||
} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
|
||||
smUnit(2).io.sram_w := masterParser.io.sram_w
|
||||
lvdsSMEnq(1) := masterParser.io.rxEnq
|
||||
lvdsSMEnq(1) := masterParser.io.rxEnq
|
||||
lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B)
|
||||
lvdsSMAbrt(1) := false.B
|
||||
} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
|
||||
smUnit(4).io.sram_w := masterParser.io.sram_w
|
||||
lvdsSMEnq(2) := masterParser.io.rxEnq
|
||||
lvdsSMEnq(2) := masterParser.io.rxEnq
|
||||
lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B)
|
||||
lvdsSMAbrt(2) := false.B
|
||||
} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
|
||||
smUnit(6).io.sram_w := masterParser.io.sram_w
|
||||
lvdsSMEnq(3) := masterParser.io.rxEnq
|
||||
lvdsSMEnq(3) := masterParser.io.rxEnq
|
||||
lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B)
|
||||
lvdsSMAbrt(3) := false.B
|
||||
}
|
||||
|
||||
when( interface.io.txReq.bits.txSM === 0.U ){
|
||||
@@ -321,10 +366,10 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
|
||||
trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
|
||||
|
||||
when( interface.io.cReg.modeSel === false.B ){
|
||||
slaveParser.io.downIn <> io.downCDRIn.axis
|
||||
io.downCDROut.axis <> slaveParser.io.downOut
|
||||
slaveParser.io.upIn <> io.upCDRIn.axis
|
||||
io.upCDROut.axis <> slaveParser.io.upOut
|
||||
slaveParser.io.downIn <> downCDRInAxis.io.axis
|
||||
downCDROut.io.axis <> slaveParser.io.downOut
|
||||
slaveParser.io.upIn <> upCDRInAxis.io.axis
|
||||
upCDROut.io.axis <> slaveParser.io.upOut
|
||||
}
|
||||
|
||||
slaveParser.io.cReg := interface.io.cReg
|
||||
@@ -346,6 +391,16 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
|
||||
lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
|
||||
lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
|
||||
|
||||
lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish
|
||||
lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish
|
||||
lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish
|
||||
lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish
|
||||
|
||||
lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError
|
||||
lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError
|
||||
lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError
|
||||
lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError
|
||||
|
||||
lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
|
||||
lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
|
||||
lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
|
||||
@@ -375,10 +430,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
|
||||
|
||||
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
|
||||
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
|
||||
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
|
||||
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
|
||||
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
|
||||
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
|
||||
downCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
|
||||
upCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
|
||||
downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
|
||||
upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
|
||||
|
||||
interface.io.lvds <> slaveParser.io.lvds
|
||||
|
||||
@@ -398,7 +453,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
|
||||
|
||||
//看门狗1~16，SM监控
|
||||
val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
|
||||
val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
|
||||
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
|
||||
|
||||
for( i <- 0 until 8 ){
|
||||
when( smUnit(i).io.enq ){
|
||||
@@ -428,14 +483,14 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
|
||||
|
||||
//看门狗0 发送后回包是否超时
|
||||
val isWdtRec2RtnEnable = RegInit(false.B)
|
||||
val wdtRec2RtnCnt = Reg(UInt(32.W))
|
||||
val wdtRec2RtnCnt = RegInit(0.U(32.W))
|
||||
|
||||
when(
|
||||
(io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) |
|
||||
(upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) |
|
||||
~interface.io.cReg.wdtEnable.extract(0)
|
||||
){
|
||||
isWdtRec2RtnEnable := false.B
|
||||
} .elsewhen( ~isWdtRec2RtnEnable & io.downCDROut.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
|
||||
} .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
|
||||
isWdtRec2RtnEnable := true.B
|
||||
}
|
||||
|
||||
@@ -450,13 +505,13 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
|
||||
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
|
||||
|
||||
//看门狗17
|
||||
val wdtRec2RecCnt = Reg(UInt(32.W))
|
||||
val wdtRec2RecCnt = RegInit(0.U(32.W))
|
||||
|
||||
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
|
||||
wdtRec2RecCnt := wdtRec2RecCnt + 1.U
|
||||
} .elsewhen(
|
||||
~interface.io.cReg.wdtEnable.extract(17) ||
|
||||
io.downCDRIn.axis.fire ||
|
||||
downCDRInAxis.io.axis.fire ||
|
||||
(wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17))
|
||||
){
|
||||
wdtRec2RecCnt := 0.U
|
||||
@@ -466,45 +521,167 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
|
||||
|
||||
}
|
||||
|
||||
trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
|
||||
val isDwUpEx = interface.io.cReg.dwupEx.extract(0)
|
||||
|
||||
when( ~isDwUpEx ){ //未交叉
|
||||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||||
downInSerDat := false.B
|
||||
upInSerDat := false.B
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
io.dDatOut := false.B
|
||||
io.uDatOut := io.dDatIn
|
||||
} .otherwise{ //非回环
|
||||
io.dDatOut := io.dDatIn
|
||||
io.uDatOut := io.uDatIn
|
||||
}
|
||||
} .otherwise{ //无硬件错误
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
downInSerDat := io.dDatIn
|
||||
upInSerDat := downCDROut.io.serDat
|
||||
io.dDatOut := false.B
|
||||
io.uDatOut := upCDROut.io.serDat
|
||||
} .otherwise{ //非回环
|
||||
downInSerDat := io.dDatIn
|
||||
upInSerDat := io.uDatIn
|
||||
io.dDatOut := downCDROut.io.serDat
|
||||
io.uDatOut := upCDROut.io.serDat
|
||||
}
|
||||
}
|
||||
} .otherwise{ //master
|
||||
downInSerDat := false.B
|
||||
upInSerDat := io.uDatIn
|
||||
io.dDatOut := downCDROut.io.serDat
|
||||
io.uDatOut := false.B
|
||||
}
|
||||
} .otherwise{ //交叉
|
||||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||||
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
io.dDatOut := io.uDatIn
|
||||
io.uDatOut := false.B
|
||||
downInSerDat := false.B
|
||||
upInSerDat := false.B
|
||||
} .otherwise{ //非回环
|
||||
io.dDatOut := io.dDatIn
|
||||
io.uDatOut := io.uDatIn
|
||||
downInSerDat := false.B
|
||||
upInSerDat := false.B
|
||||
}
|
||||
} .otherwise{ //无硬件错误
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
downInSerDat := io.uDatIn
|
||||
upInSerDat := downCDROut.io.serDat
|
||||
io.uDatOut := false.B
|
||||
io.dDatOut := upCDROut.io.serDat
|
||||
} .otherwise{ //非回环
|
||||
downInSerDat := io.uDatIn
|
||||
upInSerDat := io.dDatIn
|
||||
io.dDatOut := upCDROut.io.serDat
|
||||
io.uDatOut := downCDROut.io.serDat
|
||||
}
|
||||
}
|
||||
} .otherwise{ //master
|
||||
downInSerDat := false.B
|
||||
upInSerDat := io.dDatIn
|
||||
io.uDatOut := downCDROut.io.serDat
|
||||
io.dDatOut := false.B
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
|
||||
val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0)
|
||||
|
||||
when( isUsing8b10b ){
|
||||
b8b10DownEncoder.io <> downCDROut.io.encode
|
||||
b8b10DownDecoder.io <> downCDRInAxis.io.decode
|
||||
b8b10UpEncoder.io <> upCDROut.io.encode
|
||||
b8b10UpDecoder.io <> upCDRInAxis.io.decode
|
||||
|
||||
b4b5DownEncoder.io.isEnable := false.B
|
||||
b4b5DownEncoder.io.dataIn := 0.U
|
||||
b4b5DownDecoder.io.dataIn := 0.U
|
||||
b4b5UpEncoder.io.isEnable := false.B
|
||||
b4b5UpEncoder.io.dataIn := 0.U
|
||||
b4b5UpDecoder.io.dataIn := 0.U
|
||||
} .otherwise{
|
||||
b4b5DownEncoder.io <> downCDROut.io.encode
|
||||
b4b5DownDecoder.io <> downCDRInAxis.io.decode
|
||||
b4b5UpEncoder.io <> upCDROut.io.encode
|
||||
b4b5UpDecoder.io <> upCDRInAxis.io.decode
|
||||
|
||||
b8b10DownEncoder.io.isEnable := false.B
|
||||
b8b10DownEncoder.io.dataIn := 0.U
|
||||
b8b10DownDecoder.io.dataIn := 0.U
|
||||
b8b10UpEncoder.io.isEnable := false.B
|
||||
b8b10UpEncoder.io.dataIn := 0.U
|
||||
b8b10UpDecoder.io.dataIn := 0.U
|
||||
}
|
||||
}
|
||||
|
||||
trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
|
||||
val cdrSelB = interface.io.cReg.cdrParam === 1.U
|
||||
val cdrSelC = interface.io.cReg.cdrParam === 2.U
|
||||
val cdrSelA = ~cdrSelB & ~cdrSelC
|
||||
|
||||
// val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
|
||||
// val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
|
||||
|
||||
|
||||
|
||||
|
||||
when(cdrSelB){
|
||||
io.downCDRSampleIn(1).serDat := downInSerDat
|
||||
io.upCDRSampleIn(1).serDat := upInSerDat
|
||||
downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat
|
||||
upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat
|
||||
|
||||
io.downCDRSampleIn(0).serDat := false.B
|
||||
io.upCDRSampleIn(0).serDat := false.B
|
||||
io.downCDRSampleIn(2).serDat := false.B
|
||||
io.upCDRSampleIn(2).serDat := false.B
|
||||
} .elsewhen(cdrSelC){
|
||||
io.downCDRSampleIn(2).serDat := downInSerDat
|
||||
io.upCDRSampleIn(2).serDat := upInSerDat
|
||||
downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat
|
||||
upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat
|
||||
|
||||
io.downCDRSampleIn(0).serDat := false.B
|
||||
io.upCDRSampleIn(0).serDat := false.B
|
||||
io.downCDRSampleIn(1).serDat := false.B
|
||||
io.upCDRSampleIn(1).serDat := false.B
|
||||
} .otherwise{
|
||||
io.downCDRSampleIn(0).serDat := downInSerDat
|
||||
io.upCDRSampleIn(0).serDat := upInSerDat
|
||||
downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat
|
||||
upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat
|
||||
|
||||
io.downCDRSampleIn(1).serDat := false.B
|
||||
io.upCDRSampleIn(1).serDat := false.B
|
||||
io.downCDRSampleIn(2).serDat := false.B
|
||||
io.upCDRSampleIn(2).serDat := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
class MstSlvSwitch extends MstSlvSwitchBase
|
||||
with MstSlvSwitchMaster
|
||||
with MstSlvSwitchSlave
|
||||
with MstSlvSwitchWatchDog{
|
||||
with MstSlvSwitchWatchDog
|
||||
with MstSlvSwitchDataPath
|
||||
with MstSlvSwitchB8B4
|
||||
with MstSlvSwitchCDRIn{
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||||
io.downCDRIn.serDat := false.B
|
||||
io.upCDRIn.serDat := false.B
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
io.dDatOut := false.B
|
||||
io.uDatOut := io.dDatIn
|
||||
} .otherwise{ //非回环
|
||||
io.dDatOut := io.dDatIn
|
||||
io.uDatOut := io.uDatIn
|
||||
}
|
||||
} .otherwise{ //无硬件错误
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
io.downCDRIn.serDat := io.dDatIn
|
||||
io.upCDRIn.serDat := io.downCDROut.serDat
|
||||
io.dDatOut := false.B
|
||||
io.uDatOut := io.upCDROut.serDat
|
||||
} .otherwise{ //非回环
|
||||
io.downCDRIn.serDat := io.dDatIn
|
||||
io.upCDRIn.serDat := io.uDatIn
|
||||
io.dDatOut := io.downCDROut.serDat
|
||||
io.uDatOut := io.upCDROut.serDat
|
||||
}
|
||||
}
|
||||
} .otherwise{ //master
|
||||
io.downCDRIn.serDat := false.B
|
||||
io.upCDRIn.serDat := io.uDatIn
|
||||
io.dDatOut := io.downCDROut.serDat
|
||||
io.uDatOut := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -34,7 +34,8 @@ class SMUnitIO(depth: Int) extends Bundle {
|
||||
val cnt = Output(UInt(8.W))
|
||||
|
||||
val flush = Input(Bool())
|
||||
|
||||
val isComf = Input(Bool())
|
||||
val isAbrt = Input(Bool())
|
||||
}
|
||||
|
||||
abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
|
||||
@@ -43,16 +44,18 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
|
||||
|
||||
val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||
val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||
val cPtr = RegInit(0.U((log2Ceil(depth)+1).W))
|
||||
|
||||
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
|
||||
|
||||
val isEmpty = ( wPtr === rPtr )
|
||||
val isEmpty = ( cPtr === rPtr )
|
||||
|
||||
when(io.flush){
|
||||
wPtr := 0.U
|
||||
} .elsewhen( io.enq & ~isFull ){
|
||||
wPtr := wPtr + 1.U
|
||||
// assert( ~isFull)
|
||||
} .elsewhen( io.isAbrt ){
|
||||
wPtr := cPtr
|
||||
}
|
||||
|
||||
when(io.flush){
|
||||
@@ -82,24 +85,19 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
|
||||
( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
|
||||
})
|
||||
|
||||
val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt
|
||||
io.cnt := cPtr - rPtr
|
||||
|
||||
when( io.flush ){
|
||||
cnt := 0.U
|
||||
} .elsewhen( io.enq & ~isFull ){
|
||||
cnt := cnt + 1.U
|
||||
assert(cnt =/= depth.U)
|
||||
} .elsewhen( io.deq & ~isEmpty ){
|
||||
cnt := cnt - 1.U
|
||||
assert(cnt =/= 0.U)
|
||||
cPtr := 0.U
|
||||
} .elsewhen( io.isComf ){
|
||||
cPtr := wPtr
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
|
||||
|
||||
@@ -14,20 +14,43 @@ class ShinTop extends Module with RequireAsyncReset{
|
||||
val io: ShinTopIO = IO(new ShinTopIO)
|
||||
|
||||
val mstSlvSwitch = Module(new MstSlvSwitch)
|
||||
val downCDROut = Module(new CDROut)
|
||||
val upCDROut = Module(new CDROut)
|
||||
val downCDRIn = Module(new MPCDRIn)
|
||||
val upCDRIn = Module(new MPCDRIn)
|
||||
|
||||
|
||||
downCDRIn.multiCLK := io.multiCLK
|
||||
upCDRIn.multiCLK := io.multiCLK
|
||||
|
||||
{
|
||||
val downCDRInSampleA = Module(new CDRInMultiSample)
|
||||
val upCDRInSampleA = Module(new CDRInMultiSample)
|
||||
|
||||
downCDRInSampleA.multiCLK := io.multiCLK
|
||||
upCDRInSampleA.multiCLK := io.multiCLK
|
||||
|
||||
downCDRInSampleA.io <> mstSlvSwitch.io.downCDRSampleIn(0)
|
||||
upCDRInSampleA.io <> mstSlvSwitch.io.upCDRSampleIn(0)
|
||||
}
|
||||
|
||||
{
|
||||
val downCDRInSampleB = Module(new CDRInMultiSample)
|
||||
val upCDRInSampleB = Module(new CDRInMultiSample)
|
||||
|
||||
downCDRInSampleB.multiCLK := io.multiCLK
|
||||
upCDRInSampleB.multiCLK := io.multiCLK
|
||||
|
||||
downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
|
||||
upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
|
||||
}
|
||||
|
||||
{
|
||||
val downCDRInSampleC = Module(new CDRInMultiSample)
|
||||
val upCDRInSampleC = Module(new CDRInMultiSample)
|
||||
|
||||
downCDRInSampleC.multiCLK := io.multiCLK
|
||||
upCDRInSampleC.multiCLK := io.multiCLK
|
||||
|
||||
downCDRInSampleC.io <> mstSlvSwitch.io.downCDRSampleIn(2)
|
||||
upCDRInSampleC.io <> mstSlvSwitch.io.upCDRSampleIn(2)
|
||||
}
|
||||
|
||||
|
||||
downCDROut.io <> mstSlvSwitch.io.downCDROut
|
||||
upCDROut.io <> mstSlvSwitch.io.upCDROut
|
||||
downCDRIn.io <> mstSlvSwitch.io.downCDRIn
|
||||
upCDRIn.io <> mstSlvSwitch.io.upCDRIn
|
||||
|
||||
io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
|
||||
|
||||
|
||||
@@ -187,11 +187,10 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{
|
||||
|
||||
//接收子报文
|
||||
|
||||
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
|
||||
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
|
||||
|
||||
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
|
||||
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
|
||||
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) } //子报文头
|
||||
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) }
|
||||
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) } //子报文头
|
||||
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) }
|
||||
|
||||
|
||||
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
|
||||
@@ -485,9 +484,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
//写入 SM或寄存器空间
|
||||
|
||||
val addrw = Reg(UInt(15.W))
|
||||
val addrw = RegInit(0.U(15.W))
|
||||
val logicAddrwNext = Wire( UInt(30.W) )
|
||||
val logicAddrw = RegNext(logicAddrwNext)
|
||||
val logicAddrw = RegNext(logicAddrwNext, 0.U(30.W))
|
||||
|
||||
val isWRReg = (addrw(14,11) === "b0000".U)
|
||||
val isWRSM0 = (addrw(14,11) === "b0001".U)
|
||||
@@ -625,9 +624,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
val upTransLenCnt = RegInit(0.U)
|
||||
|
||||
|
||||
val addrr = Reg(UInt(15.W))
|
||||
val addrr = RegInit(0.U(15.W))
|
||||
val logicAddrrNext = Wire( UInt(30.W) )
|
||||
val logicAddrr = RegNext(logicAddrrNext)
|
||||
val logicAddrr = RegNext(logicAddrrNext, 0.U(30.W))
|
||||
|
||||
|
||||
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
|
||||
@@ -697,14 +696,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
|
||||
)
|
||||
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
|
||||
) & ( (RegNext(upRecParser.io.stateCurr, STATE_IDLE) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
|
||||
|
||||
val isLgcRead =
|
||||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
|
||||
)
|
||||
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
|
||||
) & ( RegNext(isUpLgcAddrrAcquireTrans, false.B) | upRecParser.io.data.fire )
|
||||
|
||||
val isLvdsEnR = isSeqRead | isLgcRead
|
||||
|
||||
@@ -840,20 +839,15 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
|
||||
val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
|
||||
val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
|
||||
val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
|
||||
val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
|
||||
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
|
||||
val downTimeStamp = RegInit(0.U(64.W)) //下行本地时间戳寄存器
|
||||
val upTimeStamp = RegInit(0.U(64.W)) //上行本地时间戳寄存器
|
||||
val mstTimeStamp = RegInit(0.U(64.W)) //主站时间戳
|
||||
val mstDeltaTimeStamp = RegInit(0.U(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
|
||||
val slvDeltaTimeStamp = RegInit(0.U(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
|
||||
|
||||
val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
|
||||
val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
|
||||
val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
|
||||
|
||||
|
||||
// val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
|
||||
|
||||
// dontTouch(recoTimeStamp)
|
||||
val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量)
|
||||
val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量)
|
||||
val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
|
||||
|
||||
// recoTimeStamp = io.timeStamp + deltaFinal
|
||||
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
|
||||
@@ -883,7 +877,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
|
||||
)
|
||||
|
||||
val syncCnt = Reg(UInt(4.W))
|
||||
val syncCnt = RegInit(0.U(4.W))
|
||||
|
||||
when( downRecParser.io.rec.fire ){
|
||||
when( isSync ){
|
||||
@@ -931,7 +925,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
}
|
||||
}
|
||||
|
||||
when( RegNext(isSync) & ~isSync ){
|
||||
when( RegNext(isSync, false.B) & ~isSync ){
|
||||
// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
|
||||
|
||||
addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
|
||||
@@ -939,7 +933,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
addrConflict(2) := true.B //组合逻辑
|
||||
deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
|
||||
|
||||
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
|
||||
} .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){
|
||||
// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
|
||||
addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
|
||||
addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
|
||||
@@ -1020,11 +1014,11 @@ with SlaveParserProbe{
|
||||
io.intHWTrig(0) := downRecParser.io.isError
|
||||
io.intHWTrig(1) := upRecParser.io.isError
|
||||
|
||||
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
|
||||
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
|
||||
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
|
||||
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
|
||||
|
||||
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
|
||||
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
|
||||
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
|
||||
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
|
||||
|
||||
io.downRecStat := downRecParser.io.stat
|
||||
io.upRecStat := upRecParser.io.stat
|
||||
|
||||
@@ -55,7 +55,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
|
||||
|
||||
crc.io.flush := stateCurr === STATE_IDLE | io.flush
|
||||
|
||||
val crcData = Reg(UInt(32.W))
|
||||
val crcData = RegInit(0.U(32.W))
|
||||
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
|
||||
|
||||
when( io.rec.fire & stateCurr === STATE_CRC ){
|
||||
@@ -72,12 +72,12 @@ class SlaveRecParser extends Module with RequireAsyncReset{
|
||||
|
||||
|
||||
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
|
||||
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
|
||||
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
|
||||
|
||||
|
||||
|
||||
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
|
||||
val frameHeader = Reg(new FrameHeader)
|
||||
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
|
||||
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
|
||||
io.frameReq.bits.frameStyle := frameHeader.frameStyle
|
||||
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
|
||||
@@ -85,8 +85,8 @@ class SlaveRecParser extends Module with RequireAsyncReset{
|
||||
io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
|
||||
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
|
||||
|
||||
val subMsgHeader = Reg(new SubMsgHeader)
|
||||
val subMsgTail = Reg(new SubMsgTail)
|
||||
val subMsgHeader = RegInit(0.U.asTypeOf(new SubMsgHeader))
|
||||
val subMsgTail = RegInit(0.U.asTypeOf(new SubMsgTail))
|
||||
|
||||
io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
|
||||
io.subMsgHeadReq.bits.style := subMsgHeader.style
|
||||
@@ -182,7 +182,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
|
||||
Mux( io.flush, STATE_IDLE,
|
||||
Mux1H(Seq(
|
||||
//必须使用上升沿触发，以避免前一帧长度超过预期
|
||||
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
|
||||
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid, false.B) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
|
||||
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
|
||||
Mux( lengthCnt === (4-1).U,
|
||||
MuxCase( STATE_ERROR, Array(
|
||||
|
||||
@@ -66,10 +66,10 @@ class SlaveSendGen extends Module with RequireAsyncReset{
|
||||
|
||||
|
||||
|
||||
val frameInfo = Reg(new FrameHeader)
|
||||
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
|
||||
|
||||
val subMsgHeadInfo = Reg(new SubMsgTxInfo)
|
||||
val subMsgTailInfo = Reg(new SubMsgTail)
|
||||
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
|
||||
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
|
||||
|
||||
|
||||
|
||||
@@ -88,8 +88,8 @@ class SlaveSendGen extends Module with RequireAsyncReset{
|
||||
|
||||
|
||||
|
||||
val lengthCnt = Reg(UInt(12.W))
|
||||
val frameLenCnt = Reg(UInt(12.W))
|
||||
val lengthCnt = RegInit(0.U(12.W))
|
||||
val frameLenCnt = RegInit(0.U(12.W))
|
||||
|
||||
when( io.send.fire ){
|
||||
when( stateCurr === STATE_FRAME_HEADER ){
|
||||
|
||||
@@ -47,8 +47,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
|
||||
val exRego = RegInit(0.U(8.W))
|
||||
val exRegi = RegInit(0.U(8.W))
|
||||
|
||||
|
||||
|
||||
val addrw = RegInit(0.U(16.W))
|
||||
val addrr = RegInit(0.U(16.W))
|
||||
val spiCmd = RegInit(0.U(1.W))
|
||||
@@ -61,15 +59,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
|
||||
val byteSel = RegInit(0.U(12.W))
|
||||
val byteSelNext = RegNext(byteSel, 0.U(12.W))
|
||||
|
||||
|
||||
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
|
||||
|
||||
|
||||
io.dataw := exRegi
|
||||
io.addrr := addrr
|
||||
io.addrw := addrw
|
||||
|
||||
|
||||
when( shiftCSn(2) & ~shiftCSn(1) ){
|
||||
byteSel := 0.U
|
||||
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
|
||||
@@ -118,8 +113,6 @@ class SSpiInterface extends SpiInterfaceBase{
|
||||
bitSel := bitSel + 1.U
|
||||
}
|
||||
|
||||
|
||||
|
||||
//输入看SCK上升沿
|
||||
when( isSckPosedge & ~shiftCSn(1) ){
|
||||
when( bitSel === 0.U ){
|
||||
|
||||
Reference in New Issue
Block a user