2k fifo抽出到顶层

src/main/scala/backBoard/shin/SMUnit.scala

@@ -8,6 +8,8 @@ class SMUnitIO extends Bundle {
   val enq = Flipped(Decoupled(UInt(8.W)))
   val deq = Decoupled(UInt(8.W))
 
+  val sram = Vec(4, new SRAM2kIO)
+
 }
 
 abstract class SMUnitBase extends Module {
@@ -21,10 +23,14 @@ abstract class SMUnitBase extends Module {
 
 
   val dataBuf =
-    for ( _ <- until 4 ) yield {
-      Module( new Queue(UInt(8.W), 2048, useSyncReadMem = true) )        
+    for ( i <- 0 until 4 ) yield {
+      val mdl = Module( new SRAM2kFifo )
+      io.sram(i) <> mdl.io.sram
+      mdl
     }
 
+  
+
   val wPtr = RegInit(0.U((2+1).W))
   val rPtr = RegInit(0.U((2+1).W))